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Merge git://git.kernel.org/pub/scm/linux/kernel/git/pablo/nf
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-mv64xxx.c
blobb4dec0841bc27396b723acf218351b0bf5ab2ed0
1 /*
2 * Driver for the i2c controller on the Marvell line of host bridges
3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/mv643xx_i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/reset.h>
21 #include <linux/io.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/of_irq.h>
25 #include <linux/clk.h>
26 #include <linux/err.h>
27 #include <linux/delay.h>
28
29 #define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1)
30 #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7)
31 #define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3)
32
33 #define MV64XXX_I2C_REG_CONTROL_ACK BIT(2)
34 #define MV64XXX_I2C_REG_CONTROL_IFLG BIT(3)
35 #define MV64XXX_I2C_REG_CONTROL_STOP BIT(4)
36 #define MV64XXX_I2C_REG_CONTROL_START BIT(5)
37 #define MV64XXX_I2C_REG_CONTROL_TWSIEN BIT(6)
38 #define MV64XXX_I2C_REG_CONTROL_INTEN BIT(7)
39
40 /* Ctlr status values */
41 #define MV64XXX_I2C_STATUS_BUS_ERR 0x00
42 #define MV64XXX_I2C_STATUS_MAST_START 0x08
43 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
44 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
45 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
46 #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
47 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
48 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
49 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
50 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
51 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
52 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
53 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
54 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
55 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
56 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
57 #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
58
59 /* Register defines (I2C bridge) */
60 #define MV64XXX_I2C_REG_TX_DATA_LO 0xc0
61 #define MV64XXX_I2C_REG_TX_DATA_HI 0xc4
62 #define MV64XXX_I2C_REG_RX_DATA_LO 0xc8
63 #define MV64XXX_I2C_REG_RX_DATA_HI 0xcc
64 #define MV64XXX_I2C_REG_BRIDGE_CONTROL 0xd0
65 #define MV64XXX_I2C_REG_BRIDGE_STATUS 0xd4
66 #define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE 0xd8
67 #define MV64XXX_I2C_REG_BRIDGE_INTR_MASK 0xdC
68 #define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0
69
70 /* Bridge Control values */
71 #define MV64XXX_I2C_BRIDGE_CONTROL_WR BIT(0)
72 #define MV64XXX_I2C_BRIDGE_CONTROL_RD BIT(1)
73 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2
74 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT BIT(12)
75 #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13
76 #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16
77 #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE BIT(19)
78 #define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START BIT(20)
79
80 /* Bridge Status values */
81 #define MV64XXX_I2C_BRIDGE_STATUS_ERROR BIT(0)
82
83 /* Driver states */
84 enum {
85 MV64XXX_I2C_STATE_INVALID,
86 MV64XXX_I2C_STATE_IDLE,
87 MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
88 MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
89 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
90 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
91 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
92 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
93 };
94
95 /* Driver actions */
96 enum {
97 MV64XXX_I2C_ACTION_INVALID,
98 MV64XXX_I2C_ACTION_CONTINUE,
99 MV64XXX_I2C_ACTION_SEND_RESTART,
100 MV64XXX_I2C_ACTION_SEND_ADDR_1,
101 MV64XXX_I2C_ACTION_SEND_ADDR_2,
102 MV64XXX_I2C_ACTION_SEND_DATA,
103 MV64XXX_I2C_ACTION_RCV_DATA,
104 MV64XXX_I2C_ACTION_RCV_DATA_STOP,
105 MV64XXX_I2C_ACTION_SEND_STOP,
106 };
107
108 struct mv64xxx_i2c_regs {
109 u8 addr;
110 u8 ext_addr;
111 u8 data;
112 u8 control;
113 u8 status;
114 u8 clock;
115 u8 soft_reset;
116 };
117
118 struct mv64xxx_i2c_data {
119 struct i2c_msg *msgs;
120 int num_msgs;
121 int irq;
122 u32 state;
123 u32 action;
124 u32 aborting;
125 u32 cntl_bits;
126 void __iomem *reg_base;
127 struct mv64xxx_i2c_regs reg_offsets;
128 u32 addr1;
129 u32 addr2;
130 u32 bytes_left;
131 u32 byte_posn;
132 u32 send_stop;
133 u32 block;
134 int rc;
135 u32 freq_m;
136 u32 freq_n;
137 struct clk *clk;
138 wait_queue_head_t waitq;
139 spinlock_t lock;
140 struct i2c_msg *msg;
141 struct i2c_adapter adapter;
142 bool offload_enabled;
143 /* 5us delay in order to avoid repeated start timing violation */
144 bool errata_delay;
145 struct reset_control *rstc;
146 bool irq_clear_inverted;
147 /* Clk div is 2 to the power n, not 2 to the power n + 1 */
148 bool clk_n_base_0;
149 };
150
151 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
152 .addr = 0x00,
153 .ext_addr = 0x10,
154 .data = 0x04,
155 .control = 0x08,
156 .status = 0x0c,
157 .clock = 0x0c,
158 .soft_reset = 0x1c,
159 };
160
161 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
162 .addr = 0x00,
163 .ext_addr = 0x04,
164 .data = 0x08,
165 .control = 0x0c,
166 .status = 0x10,
167 .clock = 0x14,
168 .soft_reset = 0x18,
169 };
170
171 static void
172 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
173 struct i2c_msg *msg)
174 {
175 u32 dir = 0;
176
177 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
178 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
179
180 if (msg->flags & I2C_M_RD)
181 dir = 1;
182
183 if (msg->flags & I2C_M_TEN) {
184 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
185 drv_data->addr2 = (u32)msg->addr & 0xff;
186 } else {
187 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
188 drv_data->addr2 = 0;
189 }
190 }
191
192 /*
193 *****************************************************************************
194 *
195 * Finite State Machine & Interrupt Routines
196 *
197 *****************************************************************************
198 */
199
200 /* Reset hardware and initialize FSM */
201 static void
202 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
203 {
204 if (drv_data->offload_enabled) {
205 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
206 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
207 writel(0, drv_data->reg_base +
208 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
209 writel(0, drv_data->reg_base +
210 MV64XXX_I2C_REG_BRIDGE_INTR_MASK);
211 }
212
213 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
214 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
215 drv_data->reg_base + drv_data->reg_offsets.clock);
216 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
217 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
218 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
219 drv_data->reg_base + drv_data->reg_offsets.control);
220 drv_data->state = MV64XXX_I2C_STATE_IDLE;
221 }
222
223 static void
224 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
225 {
226 /*
227 * If state is idle, then this is likely the remnants of an old
228 * operation that driver has given up on or the user has killed.
229 * If so, issue the stop condition and go to idle.
230 */
231 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
232 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
233 return;
234 }
235
236 /* The status from the ctlr [mostly] tells us what to do next */
237 switch (status) {
238 /* Start condition interrupt */
239 case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
240 case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
241 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
242 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
243 break;
244
245 /* Performing a write */
246 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
247 if (drv_data->msg->flags & I2C_M_TEN) {
248 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
249 drv_data->state =
250 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
251 break;
252 }
253 /* FALLTHRU */
254 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
255 case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
256 if ((drv_data->bytes_left == 0)
257 || (drv_data->aborting
258 && (drv_data->byte_posn != 0))) {
259 if (drv_data->send_stop || drv_data->aborting) {
260 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
261 drv_data->state = MV64XXX_I2C_STATE_IDLE;
262 } else {
263 drv_data->action =
264 MV64XXX_I2C_ACTION_SEND_RESTART;
265 drv_data->state =
266 MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
267 }
268 } else {
269 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
270 drv_data->state =
271 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
272 drv_data->bytes_left--;
273 }
274 break;
275
276 /* Performing a read */
277 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
278 if (drv_data->msg->flags & I2C_M_TEN) {
279 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
280 drv_data->state =
281 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
282 break;
283 }
284 /* FALLTHRU */
285 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
286 if (drv_data->bytes_left == 0) {
287 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
288 drv_data->state = MV64XXX_I2C_STATE_IDLE;
289 break;
290 }
291 /* FALLTHRU */
292 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
293 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
294 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
295 else {
296 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
297 drv_data->bytes_left--;
298 }
299 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
300
301 if ((drv_data->bytes_left == 1) || drv_data->aborting)
302 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
303 break;
304
305 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
306 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
307 drv_data->state = MV64XXX_I2C_STATE_IDLE;
308 break;
309
310 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
311 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
312 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
313 /* Doesn't seem to be a device at other end */
314 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
315 drv_data->state = MV64XXX_I2C_STATE_IDLE;
316 drv_data->rc = -ENXIO;
317 break;
318
319 default:
320 dev_err(&drv_data->adapter.dev,
321 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
322 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
323 drv_data->state, status, drv_data->msg->addr,
324 drv_data->msg->flags);
325 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
326 mv64xxx_i2c_hw_init(drv_data);
327 drv_data->rc = -EIO;
328 }
329 }
330
331 static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data)
332 {
333 drv_data->msg = drv_data->msgs;
334 drv_data->byte_posn = 0;
335 drv_data->bytes_left = drv_data->msg->len;
336 drv_data->aborting = 0;
337 drv_data->rc = 0;
338
339 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
340 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
341 drv_data->reg_base + drv_data->reg_offsets.control);
342 }
343
344 static void
345 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
346 {
347 switch(drv_data->action) {
348 case MV64XXX_I2C_ACTION_SEND_RESTART:
349 /* We should only get here if we have further messages */
350 BUG_ON(drv_data->num_msgs == 0);
351
352 drv_data->msgs++;
353 drv_data->num_msgs--;
354 mv64xxx_i2c_send_start(drv_data);
355
356 if (drv_data->errata_delay)
357 udelay(5);
358
359 /*
360 * We're never at the start of the message here, and by this
361 * time it's already too late to do any protocol mangling.
362 * Thankfully, do not advertise support for that feature.
363 */
364 drv_data->send_stop = drv_data->num_msgs == 1;
365 break;
366
367 case MV64XXX_I2C_ACTION_CONTINUE:
368 writel(drv_data->cntl_bits,
369 drv_data->reg_base + drv_data->reg_offsets.control);
370 break;
371
372 case MV64XXX_I2C_ACTION_SEND_ADDR_1:
373 writel(drv_data->addr1,
374 drv_data->reg_base + drv_data->reg_offsets.data);
375 writel(drv_data->cntl_bits,
376 drv_data->reg_base + drv_data->reg_offsets.control);
377 break;
378
379 case MV64XXX_I2C_ACTION_SEND_ADDR_2:
380 writel(drv_data->addr2,
381 drv_data->reg_base + drv_data->reg_offsets.data);
382 writel(drv_data->cntl_bits,
383 drv_data->reg_base + drv_data->reg_offsets.control);
384 break;
385
386 case MV64XXX_I2C_ACTION_SEND_DATA:
387 writel(drv_data->msg->buf[drv_data->byte_posn++],
388 drv_data->reg_base + drv_data->reg_offsets.data);
389 writel(drv_data->cntl_bits,
390 drv_data->reg_base + drv_data->reg_offsets.control);
391 break;
392
393 case MV64XXX_I2C_ACTION_RCV_DATA:
394 drv_data->msg->buf[drv_data->byte_posn++] =
395 readl(drv_data->reg_base + drv_data->reg_offsets.data);
396 writel(drv_data->cntl_bits,
397 drv_data->reg_base + drv_data->reg_offsets.control);
398 break;
399
400 case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
401 drv_data->msg->buf[drv_data->byte_posn++] =
402 readl(drv_data->reg_base + drv_data->reg_offsets.data);
403 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
404 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
405 drv_data->reg_base + drv_data->reg_offsets.control);
406 drv_data->block = 0;
407 if (drv_data->errata_delay)
408 udelay(5);
409
410 wake_up(&drv_data->waitq);
411 break;
412
413 case MV64XXX_I2C_ACTION_INVALID:
414 default:
415 dev_err(&drv_data->adapter.dev,
416 "mv64xxx_i2c_do_action: Invalid action: %d\n",
417 drv_data->action);
418 drv_data->rc = -EIO;
419
420 /* FALLTHRU */
421 case MV64XXX_I2C_ACTION_SEND_STOP:
422 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
423 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
424 drv_data->reg_base + drv_data->reg_offsets.control);
425 drv_data->block = 0;
426 wake_up(&drv_data->waitq);
427 break;
428 }
429 }
430
431 static void
432 mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data,
433 struct i2c_msg *msg)
434 {
435 u32 buf[2];
436
437 buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO);
438 buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI);
439
440 memcpy(msg->buf, buf, msg->len);
441 }
442
443 static int
444 mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data)
445 {
446 u32 cause, status;
447
448 cause = readl(drv_data->reg_base +
449 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
450 if (!cause)
451 return IRQ_NONE;
452
453 status = readl(drv_data->reg_base +
454 MV64XXX_I2C_REG_BRIDGE_STATUS);
455
456 if (status & MV64XXX_I2C_BRIDGE_STATUS_ERROR) {
457 drv_data->rc = -EIO;
458 goto out;
459 }
460
461 drv_data->rc = 0;
462
463 /*
464 * Transaction is a one message read transaction, read data
465 * for this message.
466 */
467 if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) {
468 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs);
469 drv_data->msgs++;
470 drv_data->num_msgs--;
471 }
472 /*
473 * Transaction is a two messages write/read transaction, read
474 * data for the second (read) message.
475 */
476 else if (drv_data->num_msgs == 2 &&
477 !(drv_data->msgs[0].flags & I2C_M_RD) &&
478 drv_data->msgs[1].flags & I2C_M_RD) {
479 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1);
480 drv_data->msgs += 2;
481 drv_data->num_msgs -= 2;
482 }
483
484 out:
485 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
486 writel(0, drv_data->reg_base +
487 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
488 drv_data->block = 0;
489
490 wake_up(&drv_data->waitq);
491
492 return IRQ_HANDLED;
493 }
494
495 static irqreturn_t
496 mv64xxx_i2c_intr(int irq, void *dev_id)
497 {
498 struct mv64xxx_i2c_data *drv_data = dev_id;
499 unsigned long flags;
500 u32 status;
501 irqreturn_t rc = IRQ_NONE;
502
503 spin_lock_irqsave(&drv_data->lock, flags);
504
505 if (drv_data->offload_enabled)
506 rc = mv64xxx_i2c_intr_offload(drv_data);
507
508 while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
509 MV64XXX_I2C_REG_CONTROL_IFLG) {
510 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
511 mv64xxx_i2c_fsm(drv_data, status);
512 mv64xxx_i2c_do_action(drv_data);
513
514 if (drv_data->irq_clear_inverted)
515 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG,
516 drv_data->reg_base + drv_data->reg_offsets.control);
517
518 rc = IRQ_HANDLED;
519 }
520 spin_unlock_irqrestore(&drv_data->lock, flags);
521
522 return rc;
523 }
524
525 /*
526 *****************************************************************************
527 *
528 * I2C Msg Execution Routines
529 *
530 *****************************************************************************
531 */
532 static void
533 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
534 {
535 long time_left;
536 unsigned long flags;
537 char abort = 0;
538
539 time_left = wait_event_timeout(drv_data->waitq,
540 !drv_data->block, drv_data->adapter.timeout);
541
542 spin_lock_irqsave(&drv_data->lock, flags);
543 if (!time_left) { /* Timed out */
544 drv_data->rc = -ETIMEDOUT;
545 abort = 1;
546 } else if (time_left < 0) { /* Interrupted/Error */
547 drv_data->rc = time_left; /* errno value */
548 abort = 1;
549 }
550
551 if (abort && drv_data->block) {
552 drv_data->aborting = 1;
553 spin_unlock_irqrestore(&drv_data->lock, flags);
554
555 time_left = wait_event_timeout(drv_data->waitq,
556 !drv_data->block, drv_data->adapter.timeout);
557
558 if ((time_left <= 0) && drv_data->block) {
559 drv_data->state = MV64XXX_I2C_STATE_IDLE;
560 dev_err(&drv_data->adapter.dev,
561 "mv64xxx: I2C bus locked, block: %d, "
562 "time_left: %d\n", drv_data->block,
563 (int)time_left);
564 mv64xxx_i2c_hw_init(drv_data);
565 }
566 } else
567 spin_unlock_irqrestore(&drv_data->lock, flags);
568 }
569
570 static int
571 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
572 int is_last)
573 {
574 unsigned long flags;
575
576 spin_lock_irqsave(&drv_data->lock, flags);
577
578 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
579
580 drv_data->send_stop = is_last;
581 drv_data->block = 1;
582 mv64xxx_i2c_send_start(drv_data);
583 spin_unlock_irqrestore(&drv_data->lock, flags);
584
585 mv64xxx_i2c_wait_for_completion(drv_data);
586 return drv_data->rc;
587 }
588
589 static void
590 mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data)
591 {
592 struct i2c_msg *msg = drv_data->msgs;
593 u32 buf[2];
594
595 memcpy(buf, msg->buf, msg->len);
596
597 writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
598 writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
599 }
600
601 static int
602 mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data)
603 {
604 struct i2c_msg *msgs = drv_data->msgs;
605 int num = drv_data->num_msgs;
606 unsigned long ctrl_reg;
607 unsigned long flags;
608
609 spin_lock_irqsave(&drv_data->lock, flags);
610
611 /* Build transaction */
612 ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
613 (msgs[0].addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
614
615 if (msgs[0].flags & I2C_M_TEN)
616 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
617
618 /* Single write message transaction */
619 if (num == 1 && !(msgs[0].flags & I2C_M_RD)) {
620 size_t len = msgs[0].len - 1;
621
622 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
623 (len << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT);
624 mv64xxx_i2c_prepare_tx(drv_data);
625 }
626 /* Single read message transaction */
627 else if (num == 1 && msgs[0].flags & I2C_M_RD) {
628 size_t len = msgs[0].len - 1;
629
630 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
631 (len << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT);
632 }
633 /*
634 * Transaction with one write and one read message. This is
635 * guaranteed by the mv64xx_i2c_can_offload() checks.
636 */
637 else if (num == 2) {
638 size_t lentx = msgs[0].len - 1;
639 size_t lenrx = msgs[1].len - 1;
640
641 ctrl_reg |=
642 MV64XXX_I2C_BRIDGE_CONTROL_RD |
643 MV64XXX_I2C_BRIDGE_CONTROL_WR |
644 (lentx << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT) |
645 (lenrx << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT) |
646 MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START;
647 mv64xxx_i2c_prepare_tx(drv_data);
648 }
649
650 /* Execute transaction */
651 drv_data->block = 1;
652 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
653 spin_unlock_irqrestore(&drv_data->lock, flags);
654
655 mv64xxx_i2c_wait_for_completion(drv_data);
656
657 return drv_data->rc;
658 }
659
660 static bool
661 mv64xxx_i2c_valid_offload_sz(struct i2c_msg *msg)
662 {
663 return msg->len <= 8 && msg->len >= 1;
664 }
665
666 static bool
667 mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data)
668 {
669 struct i2c_msg *msgs = drv_data->msgs;
670 int num = drv_data->num_msgs;
671
672 if (!drv_data->offload_enabled)
673 return false;
674
675 /*
676 * We can offload a transaction consisting of a single
677 * message, as long as the message has a length between 1 and
678 * 8 bytes.
679 */
680 if (num == 1 && mv64xxx_i2c_valid_offload_sz(msgs))
681 return true;
682
683 /*
684 * We can offload a transaction consisting of two messages, if
685 * the first is a write and a second is a read, and both have
686 * a length between 1 and 8 bytes.
687 */
688 if (num == 2 &&
689 mv64xxx_i2c_valid_offload_sz(msgs) &&
690 mv64xxx_i2c_valid_offload_sz(msgs + 1) &&
691 !(msgs[0].flags & I2C_M_RD) &&
692 msgs[1].flags & I2C_M_RD)
693 return true;
694
695 return false;
696 }
697
698 /*
699 *****************************************************************************
700 *
701 * I2C Core Support Routines (Interface to higher level I2C code)
702 *
703 *****************************************************************************
704 */
705 static u32
706 mv64xxx_i2c_functionality(struct i2c_adapter *adap)
707 {
708 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
709 }
710
711 static int
712 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
713 {
714 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
715 int rc, ret = num;
716
717 BUG_ON(drv_data->msgs != NULL);
718 drv_data->msgs = msgs;
719 drv_data->num_msgs = num;
720
721 if (mv64xxx_i2c_can_offload(drv_data))
722 rc = mv64xxx_i2c_offload_xfer(drv_data);
723 else
724 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
725
726 if (rc < 0)
727 ret = rc;
728
729 drv_data->num_msgs = 0;
730 drv_data->msgs = NULL;
731
732 return ret;
733 }
734
735 static const struct i2c_algorithm mv64xxx_i2c_algo = {
736 .master_xfer = mv64xxx_i2c_xfer,
737 .functionality = mv64xxx_i2c_functionality,
738 };
739
740 /*
741 *****************************************************************************
742 *
743 * Driver Interface & Early Init Routines
744 *
745 *****************************************************************************
746 */
747 static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
748 { .compatible = "allwinner,sun4i-a10-i2c", .data = &mv64xxx_i2c_regs_sun4i},
749 { .compatible = "allwinner,sun6i-a31-i2c", .data = &mv64xxx_i2c_regs_sun4i},
750 { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
751 { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
752 { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
753 {}
754 };
755 MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
756
757 #ifdef CONFIG_OF
758 static int
759 mv64xxx_calc_freq(struct mv64xxx_i2c_data *drv_data,
760 const int tclk, const int n, const int m)
761 {
762 if (drv_data->clk_n_base_0)
763 return tclk / (10 * (m + 1) * (1 << n));
764 else
765 return tclk / (10 * (m + 1) * (2 << n));
766 }
767
768 static bool
769 mv64xxx_find_baud_factors(struct mv64xxx_i2c_data *drv_data,
770 const u32 req_freq, const u32 tclk)
771 {
772 int freq, delta, best_delta = INT_MAX;
773 int m, n;
774
775 for (n = 0; n <= 7; n++)
776 for (m = 0; m <= 15; m++) {
777 freq = mv64xxx_calc_freq(drv_data, tclk, n, m);
778 delta = req_freq - freq;
779 if (delta >= 0 && delta < best_delta) {
780 drv_data->freq_m = m;
781 drv_data->freq_n = n;
782 best_delta = delta;
783 }
784 if (best_delta == 0)
785 return true;
786 }
787 if (best_delta == INT_MAX)
788 return false;
789 return true;
790 }
791
792 static int
793 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
794 struct device *dev)
795 {
796 const struct of_device_id *device;
797 struct device_node *np = dev->of_node;
798 u32 bus_freq, tclk;
799 int rc = 0;
800
801 /* CLK is mandatory when using DT to describe the i2c bus. We
802 * need to know tclk in order to calculate bus clock
803 * factors.
804 */
805 if (IS_ERR(drv_data->clk)) {
806 rc = -ENODEV;
807 goto out;
808 }
809 tclk = clk_get_rate(drv_data->clk);
810
811 if (of_property_read_u32(np, "clock-frequency", &bus_freq))
812 bus_freq = 100000; /* 100kHz by default */
813
814 if (of_device_is_compatible(np, "allwinner,sun4i-a10-i2c") ||
815 of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
816 drv_data->clk_n_base_0 = true;
817
818 if (!mv64xxx_find_baud_factors(drv_data, bus_freq, tclk)) {
819 rc = -EINVAL;
820 goto out;
821 }
822 drv_data->irq = irq_of_parse_and_map(np, 0);
823
824 drv_data->rstc = devm_reset_control_get_optional(dev, NULL);
825 if (IS_ERR(drv_data->rstc)) {
826 if (PTR_ERR(drv_data->rstc) == -EPROBE_DEFER) {
827 rc = -EPROBE_DEFER;
828 goto out;
829 }
830 } else {
831 reset_control_deassert(drv_data->rstc);
832 }
833
834 /* Its not yet defined how timeouts will be specified in device tree.
835 * So hard code the value to 1 second.
836 */
837 drv_data->adapter.timeout = HZ;
838
839 device = of_match_device(mv64xxx_i2c_of_match_table, dev);
840 if (!device)
841 return -ENODEV;
842
843 memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets));
844
845 /*
846 * For controllers embedded in new SoCs activate the
847 * Transaction Generator support and the errata fix.
848 */
849 if (of_device_is_compatible(np, "marvell,mv78230-i2c")) {
850 drv_data->offload_enabled = true;
851 drv_data->errata_delay = true;
852 }
853
854 if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) {
855 drv_data->offload_enabled = false;
856 drv_data->errata_delay = true;
857 }
858
859 if (of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
860 drv_data->irq_clear_inverted = true;
861
862 out:
863 return rc;
864 }
865 #else /* CONFIG_OF */
866 static int
867 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
868 struct device *dev)
869 {
870 return -ENODEV;
871 }
872 #endif /* CONFIG_OF */
873
874 static int
875 mv64xxx_i2c_probe(struct platform_device *pd)
876 {
877 struct mv64xxx_i2c_data *drv_data;
878 struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev);
879 struct resource *r;
880 int rc;
881
882 if ((!pdata && !pd->dev.of_node))
883 return -ENODEV;
884
885 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
886 GFP_KERNEL);
887 if (!drv_data)
888 return -ENOMEM;
889
890 r = platform_get_resource(pd, IORESOURCE_MEM, 0);
891 drv_data->reg_base = devm_ioremap_resource(&pd->dev, r);
892 if (IS_ERR(drv_data->reg_base))
893 return PTR_ERR(drv_data->reg_base);
894
895 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
896 sizeof(drv_data->adapter.name));
897
898 init_waitqueue_head(&drv_data->waitq);
899 spin_lock_init(&drv_data->lock);
900
901 /* Not all platforms have a clk */
902 drv_data->clk = devm_clk_get(&pd->dev, NULL);
903 if (IS_ERR(drv_data->clk) && PTR_ERR(drv_data->clk) == -EPROBE_DEFER)
904 return -EPROBE_DEFER;
905 if (!IS_ERR(drv_data->clk))
906 clk_prepare_enable(drv_data->clk);
907
908 if (pdata) {
909 drv_data->freq_m = pdata->freq_m;
910 drv_data->freq_n = pdata->freq_n;
911 drv_data->irq = platform_get_irq(pd, 0);
912 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
913 drv_data->offload_enabled = false;
914 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
915 } else if (pd->dev.of_node) {
916 rc = mv64xxx_of_config(drv_data, &pd->dev);
917 if (rc)
918 goto exit_clk;
919 }
920 if (drv_data->irq < 0) {
921 rc = -ENXIO;
922 goto exit_reset;
923 }
924
925 drv_data->adapter.dev.parent = &pd->dev;
926 drv_data->adapter.algo = &mv64xxx_i2c_algo;
927 drv_data->adapter.owner = THIS_MODULE;
928 drv_data->adapter.class = I2C_CLASS_DEPRECATED;
929 drv_data->adapter.nr = pd->id;
930 drv_data->adapter.dev.of_node = pd->dev.of_node;
931 platform_set_drvdata(pd, drv_data);
932 i2c_set_adapdata(&drv_data->adapter, drv_data);
933
934 mv64xxx_i2c_hw_init(drv_data);
935
936 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
937 MV64XXX_I2C_CTLR_NAME, drv_data);
938 if (rc) {
939 dev_err(&drv_data->adapter.dev,
940 "mv64xxx: Can't register intr handler irq%d: %d\n",
941 drv_data->irq, rc);
942 goto exit_reset;
943 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
944 dev_err(&drv_data->adapter.dev,
945 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
946 goto exit_free_irq;
947 }
948
949 return 0;
950
951 exit_free_irq:
952 free_irq(drv_data->irq, drv_data);
953 exit_reset:
954 if (!IS_ERR_OR_NULL(drv_data->rstc))
955 reset_control_assert(drv_data->rstc);
956 exit_clk:
957 /* Not all platforms have a clk */
958 if (!IS_ERR(drv_data->clk))
959 clk_disable_unprepare(drv_data->clk);
960
961 return rc;
962 }
963
964 static int
965 mv64xxx_i2c_remove(struct platform_device *dev)
966 {
967 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev);
968
969 i2c_del_adapter(&drv_data->adapter);
970 free_irq(drv_data->irq, drv_data);
971 if (!IS_ERR_OR_NULL(drv_data->rstc))
972 reset_control_assert(drv_data->rstc);
973 /* Not all platforms have a clk */
974 if (!IS_ERR(drv_data->clk))
975 clk_disable_unprepare(drv_data->clk);
976
977 return 0;
978 }
979
980 static struct platform_driver mv64xxx_i2c_driver = {
981 .probe = mv64xxx_i2c_probe,
982 .remove = mv64xxx_i2c_remove,
983 .driver = {
984 .name = MV64XXX_I2C_CTLR_NAME,
985 .of_match_table = mv64xxx_i2c_of_match_table,
986 },
987 };
988
989 module_platform_driver(mv64xxx_i2c_driver);
990
991 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
992 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
993 MODULE_LICENSE("GPL");
Linux with added FPC-III support