2 * P2WI (Push-Pull Two Wire Interface) bus driver.
4 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
10 * The P2WI controller looks like an SMBus controller which only supports byte
11 * data transfers. But, it differs from standard SMBus protocol on several
13 * - it supports only one slave device, and thus drop the address field
14 * - it adds a parity bit every 8bits of data
15 * - only one read access is required to read a byte (instead of a write
16 * followed by a read access in standard SMBus protocol)
17 * - there's no Ack bit after each byte transfer
19 * This means this bus cannot be used to interface with standard SMBus
20 * devices (the only known device to support this interface is the AXP221
24 #include <linux/clk.h>
25 #include <linux/i2c.h>
27 #include <linux/interrupt.h>
28 #include <linux/module.h>
30 #include <linux/platform_device.h>
31 #include <linux/reset.h>
39 #define P2WI_DADDR0 0x10
40 #define P2WI_DADDR1 0x14
41 #define P2WI_DLEN 0x18
42 #define P2WI_DATA0 0x1c
43 #define P2WI_DATA1 0x20
45 #define P2WI_PMCR 0x28
48 #define P2WI_CTRL_START_TRANS BIT(7)
49 #define P2WI_CTRL_ABORT_TRANS BIT(6)
50 #define P2WI_CTRL_GLOBAL_INT_ENB BIT(1)
51 #define P2WI_CTRL_SOFT_RST BIT(0)
54 #define P2WI_CCR_SDA_OUT_DELAY(v) (((v) & 0x7) << 8)
55 #define P2WI_CCR_MAX_CLK_DIV 0xff
56 #define P2WI_CCR_CLK_DIV(v) ((v) & P2WI_CCR_MAX_CLK_DIV)
59 #define P2WI_INTS_TRANS_ERR_ID(v) (((v) >> 8) & 0xff)
60 #define P2WI_INTS_LOAD_BSY BIT(2)
61 #define P2WI_INTS_TRANS_ERR BIT(1)
62 #define P2WI_INTS_TRANS_OVER BIT(0)
64 /* DATA LENGTH fields*/
65 #define P2WI_DLEN_READ BIT(4)
66 #define P2WI_DLEN_DATA_LENGTH(v) ((v - 1) & 0x7)
69 #define P2WI_LCR_SCL_STATE BIT(5)
70 #define P2WI_LCR_SDA_STATE BIT(4)
71 #define P2WI_LCR_SCL_CTL BIT(3)
72 #define P2WI_LCR_SCL_CTL_EN BIT(2)
73 #define P2WI_LCR_SDA_CTL BIT(1)
74 #define P2WI_LCR_SDA_CTL_EN BIT(0)
76 /* PMU MODE CTRL fields */
77 #define P2WI_PMCR_PMU_INIT_SEND BIT(31)
78 #define P2WI_PMCR_PMU_INIT_DATA(v) (((v) & 0xff) << 16)
79 #define P2WI_PMCR_PMU_MODE_REG(v) (((v) & 0xff) << 8)
80 #define P2WI_PMCR_PMU_DEV_ADDR(v) ((v) & 0xff)
82 #define P2WI_MAX_FREQ 6000000
85 struct i2c_adapter adapter
;
86 struct completion complete
;
90 struct reset_control
*rstc
;
94 static irqreturn_t
p2wi_interrupt(int irq
, void *dev_id
)
96 struct p2wi
*p2wi
= dev_id
;
99 status
= readl(p2wi
->regs
+ P2WI_INTS
);
100 p2wi
->status
= status
;
102 /* Clear interrupts */
103 status
&= (P2WI_INTS_LOAD_BSY
| P2WI_INTS_TRANS_ERR
|
104 P2WI_INTS_TRANS_OVER
);
105 writel(status
, p2wi
->regs
+ P2WI_INTS
);
107 complete(&p2wi
->complete
);
112 static u32
p2wi_functionality(struct i2c_adapter
*adap
)
114 return I2C_FUNC_SMBUS_BYTE_DATA
;
117 static int p2wi_smbus_xfer(struct i2c_adapter
*adap
, u16 addr
,
118 unsigned short flags
, char read_write
,
119 u8 command
, int size
, union i2c_smbus_data
*data
)
121 struct p2wi
*p2wi
= i2c_get_adapdata(adap
);
122 unsigned long dlen
= P2WI_DLEN_DATA_LENGTH(1);
124 if (p2wi
->slave_addr
>= 0 && addr
!= p2wi
->slave_addr
) {
125 dev_err(&adap
->dev
, "invalid P2WI address\n");
132 writel(command
, p2wi
->regs
+ P2WI_DADDR0
);
134 if (read_write
== I2C_SMBUS_READ
)
135 dlen
|= P2WI_DLEN_READ
;
137 writel(data
->byte
, p2wi
->regs
+ P2WI_DATA0
);
139 writel(dlen
, p2wi
->regs
+ P2WI_DLEN
);
141 if (readl(p2wi
->regs
+ P2WI_CTRL
) & P2WI_CTRL_START_TRANS
) {
142 dev_err(&adap
->dev
, "P2WI bus busy\n");
146 reinit_completion(&p2wi
->complete
);
148 writel(P2WI_INTS_LOAD_BSY
| P2WI_INTS_TRANS_ERR
| P2WI_INTS_TRANS_OVER
,
149 p2wi
->regs
+ P2WI_INTE
);
151 writel(P2WI_CTRL_START_TRANS
| P2WI_CTRL_GLOBAL_INT_ENB
,
152 p2wi
->regs
+ P2WI_CTRL
);
154 wait_for_completion(&p2wi
->complete
);
156 if (p2wi
->status
& P2WI_INTS_LOAD_BSY
) {
157 dev_err(&adap
->dev
, "P2WI bus busy\n");
161 if (p2wi
->status
& P2WI_INTS_TRANS_ERR
) {
162 dev_err(&adap
->dev
, "P2WI bus xfer error\n");
166 if (read_write
== I2C_SMBUS_READ
)
167 data
->byte
= readl(p2wi
->regs
+ P2WI_DATA0
);
172 static const struct i2c_algorithm p2wi_algo
= {
173 .smbus_xfer
= p2wi_smbus_xfer
,
174 .functionality
= p2wi_functionality
,
177 static const struct of_device_id p2wi_of_match_table
[] = {
178 { .compatible
= "allwinner,sun6i-a31-p2wi" },
181 MODULE_DEVICE_TABLE(of
, p2wi_of_match_table
);
183 static int p2wi_probe(struct platform_device
*pdev
)
185 struct device
*dev
= &pdev
->dev
;
186 struct device_node
*np
= dev
->of_node
;
187 struct device_node
*childnp
;
188 unsigned long parent_clk_freq
;
189 u32 clk_freq
= 100000;
197 of_property_read_u32(np
, "clock-frequency", &clk_freq
);
198 if (clk_freq
> P2WI_MAX_FREQ
) {
200 "required clock-frequency (%u Hz) is too high (max = 6MHz)",
205 if (of_get_child_count(np
) > 1) {
206 dev_err(dev
, "P2WI only supports one slave device\n");
210 p2wi
= devm_kzalloc(dev
, sizeof(struct p2wi
), GFP_KERNEL
);
214 p2wi
->slave_addr
= -1;
217 * Authorize a p2wi node without any children to be able to use an
218 * i2c-dev from userpace.
219 * In this case the slave_addr is set to -1 and won't be checked when
220 * launching a P2WI transfer.
222 childnp
= of_get_next_available_child(np
, NULL
);
224 ret
= of_property_read_u32(childnp
, "reg", &slave_addr
);
226 dev_err(dev
, "invalid slave address on node %s\n",
231 p2wi
->slave_addr
= slave_addr
;
234 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
235 p2wi
->regs
= devm_ioremap_resource(dev
, r
);
236 if (IS_ERR(p2wi
->regs
))
237 return PTR_ERR(p2wi
->regs
);
239 strlcpy(p2wi
->adapter
.name
, pdev
->name
, sizeof(p2wi
->adapter
.name
));
240 irq
= platform_get_irq(pdev
, 0);
242 dev_err(dev
, "failed to retrieve irq: %d\n", irq
);
246 p2wi
->clk
= devm_clk_get(dev
, NULL
);
247 if (IS_ERR(p2wi
->clk
)) {
248 ret
= PTR_ERR(p2wi
->clk
);
249 dev_err(dev
, "failed to retrieve clk: %d\n", ret
);
253 ret
= clk_prepare_enable(p2wi
->clk
);
255 dev_err(dev
, "failed to enable clk: %d\n", ret
);
259 parent_clk_freq
= clk_get_rate(p2wi
->clk
);
261 p2wi
->rstc
= devm_reset_control_get(dev
, NULL
);
262 if (IS_ERR(p2wi
->rstc
)) {
263 ret
= PTR_ERR(p2wi
->rstc
);
264 dev_err(dev
, "failed to retrieve reset controller: %d\n", ret
);
265 goto err_clk_disable
;
268 ret
= reset_control_deassert(p2wi
->rstc
);
270 dev_err(dev
, "failed to deassert reset line: %d\n", ret
);
271 goto err_clk_disable
;
274 init_completion(&p2wi
->complete
);
275 p2wi
->adapter
.dev
.parent
= dev
;
276 p2wi
->adapter
.algo
= &p2wi_algo
;
277 p2wi
->adapter
.owner
= THIS_MODULE
;
278 p2wi
->adapter
.dev
.of_node
= pdev
->dev
.of_node
;
279 platform_set_drvdata(pdev
, p2wi
);
280 i2c_set_adapdata(&p2wi
->adapter
, p2wi
);
282 ret
= devm_request_irq(dev
, irq
, p2wi_interrupt
, 0, pdev
->name
, p2wi
);
284 dev_err(dev
, "can't register interrupt handler irq%d: %d\n",
286 goto err_reset_assert
;
289 writel(P2WI_CTRL_SOFT_RST
, p2wi
->regs
+ P2WI_CTRL
);
291 clk_div
= parent_clk_freq
/ clk_freq
;
294 "clock-frequency is too high, setting it to %lu Hz\n",
297 } else if (clk_div
> P2WI_CCR_MAX_CLK_DIV
) {
299 "clock-frequency is too low, setting it to %lu Hz\n",
300 parent_clk_freq
/ P2WI_CCR_MAX_CLK_DIV
);
301 clk_div
= P2WI_CCR_MAX_CLK_DIV
;
304 writel(P2WI_CCR_SDA_OUT_DELAY(1) | P2WI_CCR_CLK_DIV(clk_div
),
305 p2wi
->regs
+ P2WI_CCR
);
307 ret
= i2c_add_adapter(&p2wi
->adapter
);
312 reset_control_assert(p2wi
->rstc
);
315 clk_disable_unprepare(p2wi
->clk
);
320 static int p2wi_remove(struct platform_device
*dev
)
322 struct p2wi
*p2wi
= platform_get_drvdata(dev
);
324 reset_control_assert(p2wi
->rstc
);
325 clk_disable_unprepare(p2wi
->clk
);
326 i2c_del_adapter(&p2wi
->adapter
);
331 static struct platform_driver p2wi_driver
= {
333 .remove
= p2wi_remove
,
335 .name
= "i2c-sunxi-p2wi",
336 .of_match_table
= p2wi_of_match_table
,
339 module_platform_driver(p2wi_driver
);
341 MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
342 MODULE_DESCRIPTION("Allwinner P2WI driver");
343 MODULE_LICENSE("GPL v2");