Merge tag 'locks-v3.16-2' of git://git.samba.org/jlayton/linux
[linux/fpc-iii.git] / arch / arc / mm / cache_arc700.c
blob1f676c4794e01c90573937ee804882a27ac95ae4
1 /*
2 * ARC700 VIPT Cache Management
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs
11 * -flush_cache_dup_mm (fork)
12 * -likewise for flush_cache_mm (exit/execve)
13 * -likewise for flush_cache_range,flush_cache_page (munmap, exit, COW-break)
15 * vineetg: Apr 2011
16 * -Now that MMU can support larger pg sz (16K), the determiniation of
17 * aliasing shd not be based on assumption of 8k pg
19 * vineetg: Mar 2011
20 * -optimised version of flush_icache_range( ) for making I/D coherent
21 * when vaddr is available (agnostic of num of aliases)
23 * vineetg: Mar 2011
24 * -Added documentation about I-cache aliasing on ARC700 and the way it
25 * was handled up until MMU V2.
26 * -Spotted a three year old bug when killing the 4 aliases, which needs
27 * bottom 2 bits, so we need to do paddr | {0x00, 0x01, 0x02, 0x03}
28 * instead of paddr | {0x00, 0x01, 0x10, 0x11}
29 * (Rajesh you owe me one now)
31 * vineetg: Dec 2010
32 * -Off-by-one error when computing num_of_lines to flush
33 * This broke signal handling with bionic which uses synthetic sigret stub
35 * vineetg: Mar 2010
36 * -GCC can't generate ZOL for core cache flush loops.
37 * Conv them into iterations based as opposed to while (start < end) types
39 * Vineetg: July 2009
40 * -In I-cache flush routine we used to chk for aliasing for every line INV.
41 * Instead now we setup routines per cache geometry and invoke them
42 * via function pointers.
44 * Vineetg: Jan 2009
45 * -Cache Line flush routines used to flush an extra line beyond end addr
46 * because check was while (end >= start) instead of (end > start)
47 * =Some call sites had to work around by doing -1, -4 etc to end param
48 * =Some callers didnt care. This was spec bad in case of INV routines
49 * which would discard valid data (cause of the horrible ext2 bug
50 * in ARC IDE driver)
52 * vineetg: June 11th 2008: Fixed flush_icache_range( )
53 * -Since ARC700 caches are not coherent (I$ doesnt snoop D$) both need
54 * to be flushed, which it was not doing.
55 * -load_module( ) passes vmalloc addr (Kernel Virtual Addr) to the API,
56 * however ARC cache maintenance OPs require PHY addr. Thus need to do
57 * vmalloc_to_phy.
58 * -Also added optimisation there, that for range > PAGE SIZE we flush the
59 * entire cache in one shot rather than line by line. For e.g. a module
60 * with Code sz 600k, old code flushed 600k worth of cache (line-by-line),
61 * while cache is only 16 or 32k.
64 #include <linux/module.h>
65 #include <linux/mm.h>
66 #include <linux/sched.h>
67 #include <linux/cache.h>
68 #include <linux/mmu_context.h>
69 #include <linux/syscalls.h>
70 #include <linux/uaccess.h>
71 #include <linux/pagemap.h>
72 #include <asm/cacheflush.h>
73 #include <asm/cachectl.h>
74 #include <asm/setup.h>
76 char *arc_cache_mumbojumbo(int c, char *buf, int len)
78 int n = 0;
80 #define PR_CACHE(p, enb, str) \
81 { \
82 if (!(p)->ver) \
83 n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \
84 else \
85 n += scnprintf(buf + n, len - n, \
86 str"\t\t: (%uK) VIPT, %dway set-asc, %ub Line %s\n", \
87 TO_KB((p)->sz), (p)->assoc, (p)->line_len, \
88 enb ? "" : "DISABLED (kernel-build)"); \
91 PR_CACHE(&cpuinfo_arc700[c].icache, IS_ENABLED(CONFIG_ARC_HAS_ICACHE),
92 "I-Cache");
93 PR_CACHE(&cpuinfo_arc700[c].dcache, IS_ENABLED(CONFIG_ARC_HAS_DCACHE),
94 "D-Cache");
96 return buf;
100 * Read the Cache Build Confuration Registers, Decode them and save into
101 * the cpuinfo structure for later use.
102 * No Validation done here, simply read/convert the BCRs
104 void read_decode_cache_bcr(void)
106 struct cpuinfo_arc_cache *p_ic, *p_dc;
107 unsigned int cpu = smp_processor_id();
108 struct bcr_cache {
109 #ifdef CONFIG_CPU_BIG_ENDIAN
110 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
111 #else
112 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
113 #endif
114 } ibcr, dbcr;
116 p_ic = &cpuinfo_arc700[cpu].icache;
117 READ_BCR(ARC_REG_IC_BCR, ibcr);
119 BUG_ON(ibcr.config != 3);
120 p_ic->assoc = 2; /* Fixed to 2w set assoc */
121 p_ic->line_len = 8 << ibcr.line_len;
122 p_ic->sz = 0x200 << ibcr.sz;
123 p_ic->ver = ibcr.ver;
125 p_dc = &cpuinfo_arc700[cpu].dcache;
126 READ_BCR(ARC_REG_DC_BCR, dbcr);
128 BUG_ON(dbcr.config != 2);
129 p_dc->assoc = 4; /* Fixed to 4w set assoc */
130 p_dc->line_len = 16 << dbcr.line_len;
131 p_dc->sz = 0x200 << dbcr.sz;
132 p_dc->ver = dbcr.ver;
136 * 1. Validate the Cache Geomtery (compile time config matches hardware)
137 * 2. If I-cache suffers from aliasing, setup work arounds (difft flush rtn)
138 * (aliasing D-cache configurations are not supported YET)
139 * 3. Enable the Caches, setup default flush mode for D-Cache
140 * 3. Calculate the SHMLBA used by user space
142 void arc_cache_init(void)
144 unsigned int __maybe_unused cpu = smp_processor_id();
145 struct cpuinfo_arc_cache __maybe_unused *ic, __maybe_unused *dc;
146 char str[256];
148 printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
150 #ifdef CONFIG_ARC_HAS_ICACHE
151 ic = &cpuinfo_arc700[cpu].icache;
152 if (ic->ver) {
153 if (ic->line_len != L1_CACHE_BYTES)
154 panic("ICache line [%d] != kernel Config [%d]",
155 ic->line_len, L1_CACHE_BYTES);
157 if (ic->ver != CONFIG_ARC_MMU_VER)
158 panic("Cache ver [%d] doesn't match MMU ver [%d]\n",
159 ic->ver, CONFIG_ARC_MMU_VER);
161 #endif
163 #ifdef CONFIG_ARC_HAS_DCACHE
164 dc = &cpuinfo_arc700[cpu].dcache;
165 if (dc->ver) {
166 unsigned int dcache_does_alias;
168 if (dc->line_len != L1_CACHE_BYTES)
169 panic("DCache line [%d] != kernel Config [%d]",
170 dc->line_len, L1_CACHE_BYTES);
172 /* check for D-Cache aliasing */
173 dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE;
175 if (dcache_does_alias && !cache_is_vipt_aliasing())
176 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
177 else if (!dcache_does_alias && cache_is_vipt_aliasing())
178 panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n");
180 #endif
183 #define OP_INV 0x1
184 #define OP_FLUSH 0x2
185 #define OP_FLUSH_N_INV 0x3
186 #define OP_INV_IC 0x4
189 * Common Helper for Line Operations on {I,D}-Cache
191 static inline void __cache_line_loop(unsigned long paddr, unsigned long vaddr,
192 unsigned long sz, const int cacheop)
194 unsigned int aux_cmd, aux_tag;
195 int num_lines;
196 const int full_page_op = __builtin_constant_p(sz) && sz == PAGE_SIZE;
198 if (cacheop == OP_INV_IC) {
199 aux_cmd = ARC_REG_IC_IVIL;
200 #if (CONFIG_ARC_MMU_VER > 2)
201 aux_tag = ARC_REG_IC_PTAG;
202 #endif
204 else {
205 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
206 aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
207 #if (CONFIG_ARC_MMU_VER > 2)
208 aux_tag = ARC_REG_DC_PTAG;
209 #endif
212 /* Ensure we properly floor/ceil the non-line aligned/sized requests
213 * and have @paddr - aligned to cache line and integral @num_lines.
214 * This however can be avoided for page sized since:
215 * -@paddr will be cache-line aligned already (being page aligned)
216 * -@sz will be integral multiple of line size (being page sized).
218 if (!full_page_op) {
219 sz += paddr & ~CACHE_LINE_MASK;
220 paddr &= CACHE_LINE_MASK;
221 vaddr &= CACHE_LINE_MASK;
224 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
226 #if (CONFIG_ARC_MMU_VER <= 2)
227 /* MMUv2 and before: paddr contains stuffed vaddrs bits */
228 paddr |= (vaddr >> PAGE_SHIFT) & 0x1F;
229 #else
230 /* if V-P const for loop, PTAG can be written once outside loop */
231 if (full_page_op)
232 write_aux_reg(aux_tag, paddr);
233 #endif
235 while (num_lines-- > 0) {
236 #if (CONFIG_ARC_MMU_VER > 2)
237 /* MMUv3, cache ops require paddr seperately */
238 if (!full_page_op) {
239 write_aux_reg(aux_tag, paddr);
240 paddr += L1_CACHE_BYTES;
243 write_aux_reg(aux_cmd, vaddr);
244 vaddr += L1_CACHE_BYTES;
245 #else
246 write_aux_reg(aux_cmd, paddr);
247 paddr += L1_CACHE_BYTES;
248 #endif
252 #ifdef CONFIG_ARC_HAS_DCACHE
254 /***************************************************************
255 * Machine specific helpers for Entire D-Cache or Per Line ops
258 static inline void wait_for_flush(void)
260 while (read_aux_reg(ARC_REG_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
265 * Operation on Entire D-Cache
266 * @cacheop = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV}
267 * Note that constant propagation ensures all the checks are gone
268 * in generated code
270 static inline void __dc_entire_op(const int cacheop)
272 unsigned int tmp = tmp;
273 int aux;
275 if (cacheop == OP_FLUSH_N_INV) {
276 /* Dcache provides 2 cmd: FLUSH or INV
277 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
278 * flush-n-inv is achieved by INV cmd but with IM=1
279 * Default INV sub-mode is DISCARD, which needs to be toggled
281 tmp = read_aux_reg(ARC_REG_DC_CTRL);
282 write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH);
285 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
286 aux = ARC_REG_DC_IVDC;
287 else
288 aux = ARC_REG_DC_FLSH;
290 write_aux_reg(aux, 0x1);
292 if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */
293 wait_for_flush();
295 /* Switch back the DISCARD ONLY Invalidate mode */
296 if (cacheop == OP_FLUSH_N_INV)
297 write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH);
300 /* For kernel mappings cache operation: index is same as paddr */
301 #define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op)
304 * D-Cache : Per Line INV (discard or wback+discard) or FLUSH (wback)
306 static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr,
307 unsigned long sz, const int cacheop)
309 unsigned long flags, tmp = tmp;
311 local_irq_save(flags);
313 if (cacheop == OP_FLUSH_N_INV) {
315 * Dcache provides 2 cmd: FLUSH or INV
316 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
317 * flush-n-inv is achieved by INV cmd but with IM=1
318 * Default INV sub-mode is DISCARD, which needs to be toggled
320 tmp = read_aux_reg(ARC_REG_DC_CTRL);
321 write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH);
324 __cache_line_loop(paddr, vaddr, sz, cacheop);
326 if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */
327 wait_for_flush();
329 /* Switch back the DISCARD ONLY Invalidate mode */
330 if (cacheop == OP_FLUSH_N_INV)
331 write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH);
333 local_irq_restore(flags);
336 #else
338 #define __dc_entire_op(cacheop)
339 #define __dc_line_op(paddr, vaddr, sz, cacheop)
340 #define __dc_line_op_k(paddr, sz, cacheop)
342 #endif /* CONFIG_ARC_HAS_DCACHE */
345 #ifdef CONFIG_ARC_HAS_ICACHE
348 * I-Cache Aliasing in ARC700 VIPT caches
350 * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag.
351 * The orig Cache Management Module "CDU" only required paddr to invalidate a
352 * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry.
353 * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching
354 * the exact same line.
356 * However for larger Caches (way-size > page-size) - i.e. in Aliasing config,
357 * paddr alone could not be used to correctly index the cache.
359 * ------------------
360 * MMU v1/v2 (Fixed Page Size 8k)
361 * ------------------
362 * The solution was to provide CDU with these additonal vaddr bits. These
363 * would be bits [x:13], x would depend on cache-geometry, 13 comes from
364 * standard page size of 8k.
365 * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits
366 * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the
367 * orig 5 bits of paddr were anyways ignored by CDU line ops, as they
368 * represent the offset within cache-line. The adv of using this "clumsy"
369 * interface for additional info was no new reg was needed in CDU programming
370 * model.
372 * 17:13 represented the max num of bits passable, actual bits needed were
373 * fewer, based on the num-of-aliases possible.
374 * -for 2 alias possibility, only bit 13 needed (32K cache)
375 * -for 4 alias possibility, bits 14:13 needed (64K cache)
377 * ------------------
378 * MMU v3
379 * ------------------
380 * This ver of MMU supports variable page sizes (1k-16k): although Linux will
381 * only support 8k (default), 16k and 4k.
382 * However from hardware perspective, smaller page sizes aggrevate aliasing
383 * meaning more vaddr bits needed to disambiguate the cache-line-op ;
384 * the existing scheme of piggybacking won't work for certain configurations.
385 * Two new registers IC_PTAG and DC_PTAG inttoduced.
386 * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs
389 /***********************************************************
390 * Machine specific helper for per line I-Cache invalidate.
392 static void __ic_line_inv_vaddr(unsigned long paddr, unsigned long vaddr,
393 unsigned long sz)
395 unsigned long flags;
397 local_irq_save(flags);
398 __cache_line_loop(paddr, vaddr, sz, OP_INV_IC);
399 local_irq_restore(flags);
402 static inline void __ic_entire_inv(void)
404 write_aux_reg(ARC_REG_IC_IVIC, 1);
405 read_aux_reg(ARC_REG_IC_CTRL); /* blocks */
408 #else
410 #define __ic_entire_inv()
411 #define __ic_line_inv_vaddr(pstart, vstart, sz)
413 #endif /* CONFIG_ARC_HAS_ICACHE */
416 /***********************************************************
417 * Exported APIs
421 * Handle cache congruency of kernel and userspace mappings of page when kernel
422 * writes-to/reads-from
424 * The idea is to defer flushing of kernel mapping after a WRITE, possible if:
425 * -dcache is NOT aliasing, hence any U/K-mappings of page are congruent
426 * -U-mapping doesn't exist yet for page (finalised in update_mmu_cache)
427 * -In SMP, if hardware caches are coherent
429 * There's a corollary case, where kernel READs from a userspace mapped page.
430 * If the U-mapping is not congruent to to K-mapping, former needs flushing.
432 void flush_dcache_page(struct page *page)
434 struct address_space *mapping;
436 if (!cache_is_vipt_aliasing()) {
437 clear_bit(PG_dc_clean, &page->flags);
438 return;
441 /* don't handle anon pages here */
442 mapping = page_mapping(page);
443 if (!mapping)
444 return;
447 * pagecache page, file not yet mapped to userspace
448 * Make a note that K-mapping is dirty
450 if (!mapping_mapped(mapping)) {
451 clear_bit(PG_dc_clean, &page->flags);
452 } else if (page_mapped(page)) {
454 /* kernel reading from page with U-mapping */
455 void *paddr = page_address(page);
456 unsigned long vaddr = page->index << PAGE_CACHE_SHIFT;
458 if (addr_not_cache_congruent(paddr, vaddr))
459 __flush_dcache_page(paddr, vaddr);
462 EXPORT_SYMBOL(flush_dcache_page);
465 void dma_cache_wback_inv(unsigned long start, unsigned long sz)
467 __dc_line_op_k(start, sz, OP_FLUSH_N_INV);
469 EXPORT_SYMBOL(dma_cache_wback_inv);
471 void dma_cache_inv(unsigned long start, unsigned long sz)
473 __dc_line_op_k(start, sz, OP_INV);
475 EXPORT_SYMBOL(dma_cache_inv);
477 void dma_cache_wback(unsigned long start, unsigned long sz)
479 __dc_line_op_k(start, sz, OP_FLUSH);
481 EXPORT_SYMBOL(dma_cache_wback);
484 * This is API for making I/D Caches consistent when modifying
485 * kernel code (loadable modules, kprobes, kgdb...)
486 * This is called on insmod, with kernel virtual address for CODE of
487 * the module. ARC cache maintenance ops require PHY address thus we
488 * need to convert vmalloc addr to PHY addr
490 void flush_icache_range(unsigned long kstart, unsigned long kend)
492 unsigned int tot_sz, off, sz;
493 unsigned long phy, pfn;
495 /* printk("Kernel Cache Cohenercy: %lx to %lx\n",kstart, kend); */
497 /* This is not the right API for user virtual address */
498 if (kstart < TASK_SIZE) {
499 BUG_ON("Flush icache range for user virtual addr space");
500 return;
503 /* Shortcut for bigger flush ranges.
504 * Here we don't care if this was kernel virtual or phy addr
506 tot_sz = kend - kstart;
507 if (tot_sz > PAGE_SIZE) {
508 flush_cache_all();
509 return;
512 /* Case: Kernel Phy addr (0x8000_0000 onwards) */
513 if (likely(kstart > PAGE_OFFSET)) {
515 * The 2nd arg despite being paddr will be used to index icache
516 * This is OK since no alternate virtual mappings will exist
517 * given the callers for this case: kprobe/kgdb in built-in
518 * kernel code only.
520 __sync_icache_dcache(kstart, kstart, kend - kstart);
521 return;
525 * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff)
526 * (1) ARC Cache Maintenance ops only take Phy addr, hence special
527 * handling of kernel vaddr.
529 * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already),
530 * it still needs to handle a 2 page scenario, where the range
531 * straddles across 2 virtual pages and hence need for loop
533 while (tot_sz > 0) {
534 off = kstart % PAGE_SIZE;
535 pfn = vmalloc_to_pfn((void *)kstart);
536 phy = (pfn << PAGE_SHIFT) + off;
537 sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off);
538 __sync_icache_dcache(phy, kstart, sz);
539 kstart += sz;
540 tot_sz -= sz;
545 * General purpose helper to make I and D cache lines consistent.
546 * @paddr is phy addr of region
547 * @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc)
548 * However in one instance, when called by kprobe (for a breakpt in
549 * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will
550 * use a paddr to index the cache (despite VIPT). This is fine since since a
551 * builtin kernel page will not have any virtual mappings.
552 * kprobe on loadable module will be kernel vaddr.
554 void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len)
556 unsigned long flags;
558 local_irq_save(flags);
559 __ic_line_inv_vaddr(paddr, vaddr, len);
560 __dc_line_op(paddr, vaddr, len, OP_FLUSH_N_INV);
561 local_irq_restore(flags);
564 /* wrapper to compile time eliminate alignment checks in flush loop */
565 void __inv_icache_page(unsigned long paddr, unsigned long vaddr)
567 __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
571 * wrapper to clearout kernel or userspace mappings of a page
572 * For kernel mappings @vaddr == @paddr
574 void ___flush_dcache_page(unsigned long paddr, unsigned long vaddr)
576 __dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV);
579 noinline void flush_cache_all(void)
581 unsigned long flags;
583 local_irq_save(flags);
585 __ic_entire_inv();
586 __dc_entire_op(OP_FLUSH_N_INV);
588 local_irq_restore(flags);
592 #ifdef CONFIG_ARC_CACHE_VIPT_ALIASING
594 void flush_cache_mm(struct mm_struct *mm)
596 flush_cache_all();
599 void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr,
600 unsigned long pfn)
602 unsigned int paddr = pfn << PAGE_SHIFT;
604 u_vaddr &= PAGE_MASK;
606 ___flush_dcache_page(paddr, u_vaddr);
608 if (vma->vm_flags & VM_EXEC)
609 __inv_icache_page(paddr, u_vaddr);
612 void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
613 unsigned long end)
615 flush_cache_all();
618 void flush_anon_page(struct vm_area_struct *vma, struct page *page,
619 unsigned long u_vaddr)
621 /* TBD: do we really need to clear the kernel mapping */
622 __flush_dcache_page(page_address(page), u_vaddr);
623 __flush_dcache_page(page_address(page), page_address(page));
627 #endif
629 void copy_user_highpage(struct page *to, struct page *from,
630 unsigned long u_vaddr, struct vm_area_struct *vma)
632 void *kfrom = page_address(from);
633 void *kto = page_address(to);
634 int clean_src_k_mappings = 0;
637 * If SRC page was already mapped in userspace AND it's U-mapping is
638 * not congruent with K-mapping, sync former to physical page so that
639 * K-mapping in memcpy below, sees the right data
641 * Note that while @u_vaddr refers to DST page's userspace vaddr, it is
642 * equally valid for SRC page as well
644 if (page_mapped(from) && addr_not_cache_congruent(kfrom, u_vaddr)) {
645 __flush_dcache_page(kfrom, u_vaddr);
646 clean_src_k_mappings = 1;
649 copy_page(kto, kfrom);
652 * Mark DST page K-mapping as dirty for a later finalization by
653 * update_mmu_cache(). Although the finalization could have been done
654 * here as well (given that both vaddr/paddr are available).
655 * But update_mmu_cache() already has code to do that for other
656 * non copied user pages (e.g. read faults which wire in pagecache page
657 * directly).
659 clear_bit(PG_dc_clean, &to->flags);
662 * if SRC was already usermapped and non-congruent to kernel mapping
663 * sync the kernel mapping back to physical page
665 if (clean_src_k_mappings) {
666 __flush_dcache_page(kfrom, kfrom);
667 set_bit(PG_dc_clean, &from->flags);
668 } else {
669 clear_bit(PG_dc_clean, &from->flags);
673 void clear_user_page(void *to, unsigned long u_vaddr, struct page *page)
675 clear_page(to);
676 clear_bit(PG_dc_clean, &page->flags);
680 /**********************************************************************
681 * Explicit Cache flush request from user space via syscall
682 * Needed for JITs which generate code on the fly
684 SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags)
686 /* TBD: optimize this */
687 flush_cache_all();
688 return 0;