| blob | 245058b3b0ef7d5d27b7c113d6199127d8cd5a8c |
1 config ARM
2 bool
3 default y
4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
28 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
29 select HAVE_ARCH_KGDB
30 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_TRACEHOOK
32 select HAVE_BPF_JIT
33 select HAVE_CC_STACKPROTECTOR
34 select HAVE_CONTEXT_TRACKING
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_DEBUG_KMEMLEAK
37 select HAVE_DMA_API_DEBUG
38 select HAVE_DMA_ATTRS
39 select HAVE_DMA_CONTIGUOUS if MMU
40 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
41 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
42 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
43 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
44 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
45 select HAVE_GENERIC_DMA_COHERENT
46 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
47 select HAVE_IDE if PCI || ISA || PCMCIA
48 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_KERNEL_GZIP
50 select HAVE_KERNEL_LZ4
51 select HAVE_KERNEL_LZMA
52 select HAVE_KERNEL_LZO
53 select HAVE_KERNEL_XZ
54 select HAVE_KPROBES if !XIP_KERNEL
55 select HAVE_KRETPROBES if (HAVE_KPROBES)
56 select HAVE_MEMBLOCK
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
59 select HAVE_PERF_EVENTS
60 select HAVE_PERF_REGS
61 select HAVE_PERF_USER_STACK_DUMP
62 select HAVE_REGS_AND_STACK_ACCESS_API
63 select HAVE_SYSCALL_TRACEPOINTS
64 select HAVE_UID16
65 select HAVE_VIRT_CPU_ACCOUNTING_GEN
66 select IRQ_FORCED_THREADING
67 select KTIME_SCALAR
68 select MODULES_USE_ELF_REL
69 select NO_BOOTMEM
70 select OLD_SIGACTION
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
73 select RTC_LIB
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
77 help
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
86 bool
88 config NEED_SG_DMA_LENGTH
89 bool
91 config ARM_DMA_USE_IOMMU
92 bool
93 select ARM_HAS_SG_CHAIN
94 select NEED_SG_DMA_LENGTH
96 if ARM_DMA_USE_IOMMU
98 config ARM_DMA_IOMMU_ALIGNMENT
99 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
100 range 4 9
101 default 8
102 help
103 DMA mapping framework by default aligns all buffers to the smallest
104 PAGE_SIZE order which is greater than or equal to the requested buffer
105 size. This works well for buffers up to a few hundreds kilobytes, but
106 for larger buffers it just a waste of address space. Drivers which has
107 relatively small addressing window (like 64Mib) might run out of
108 virtual space with just a few allocations.
110 With this parameter you can specify the maximum PAGE_SIZE order for
111 DMA IOMMU buffers. Larger buffers will be aligned only to this
112 specified order. The order is expressed as a power of two multiplied
113 by the PAGE_SIZE.
115 endif
117 config MIGHT_HAVE_PCI
118 bool
120 config SYS_SUPPORTS_APM_EMULATION
121 bool
123 config HAVE_TCM
124 bool
125 select GENERIC_ALLOCATOR
127 config HAVE_PROC_CPU
128 bool
130 config NO_IOPORT_MAP
131 bool
133 config EISA
134 bool
135 ---help---
136 The Extended Industry Standard Architecture (EISA) bus was
137 developed as an open alternative to the IBM MicroChannel bus.
139 The EISA bus provided some of the features of the IBM MicroChannel
140 bus while maintaining backward compatibility with cards made for
141 the older ISA bus. The EISA bus saw limited use between 1988 and
142 1995 when it was made obsolete by the PCI bus.
144 Say Y here if you are building a kernel for an EISA-based machine.
146 Otherwise, say N.
148 config SBUS
149 bool
151 config STACKTRACE_SUPPORT
152 bool
153 default y
155 config HAVE_LATENCYTOP_SUPPORT
156 bool
157 depends on !SMP
158 default y
160 config LOCKDEP_SUPPORT
161 bool
162 default y
164 config TRACE_IRQFLAGS_SUPPORT
165 bool
166 default y
168 config RWSEM_XCHGADD_ALGORITHM
169 bool
170 default y
172 config ARCH_HAS_ILOG2_U32
173 bool
175 config ARCH_HAS_ILOG2_U64
176 bool
178 config ARCH_HAS_BANDGAP
179 bool
181 config GENERIC_HWEIGHT
182 bool
183 default y
185 config GENERIC_CALIBRATE_DELAY
186 bool
187 default y
189 config ARCH_MAY_HAVE_PC_FDC
190 bool
192 config ZONE_DMA
193 bool
195 config NEED_DMA_MAP_STATE
196 def_bool y
198 config ARCH_SUPPORTS_UPROBES
199 def_bool y
201 config ARCH_HAS_DMA_SET_COHERENT_MASK
202 bool
204 config GENERIC_ISA_DMA
205 bool
207 config FIQ
208 bool
210 config NEED_RET_TO_USER
211 bool
213 config ARCH_MTD_XIP
214 bool
216 config VECTORS_BASE
217 hex
218 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
219 default DRAM_BASE if REMAP_VECTORS_TO_RAM
220 default 0x00000000
221 help
222 The base address of exception vectors. This must be two pages
223 in size.
225 config ARM_PATCH_PHYS_VIRT
226 bool "Patch physical to virtual translations at runtime" if EMBEDDED
227 default y
228 depends on !XIP_KERNEL && MMU
229 depends on !ARCH_REALVIEW || !SPARSEMEM
230 help
231 Patch phys-to-virt and virt-to-phys translation functions at
232 boot and module load time according to the position of the
233 kernel in system memory.
235 This can only be used with non-XIP MMU kernels where the base
236 of physical memory is at a 16MB boundary.
238 Only disable this option if you know that you do not require
239 this feature (eg, building a kernel for a single machine) and
240 you need to shrink the kernel to the minimal size.
242 config NEED_MACH_GPIO_H
243 bool
244 help
245 Select this when mach/gpio.h is required to provide special
246 definitions for this platform. The need for mach/gpio.h should
247 be avoided when possible.
249 config NEED_MACH_IO_H
250 bool
251 help
252 Select this when mach/io.h is required to provide special
253 definitions for this platform. The need for mach/io.h should
254 be avoided when possible.
256 config NEED_MACH_MEMORY_H
257 bool
258 help
259 Select this when mach/memory.h is required to provide special
260 definitions for this platform. The need for mach/memory.h should
261 be avoided when possible.
263 config PHYS_OFFSET
264 hex "Physical address of main memory" if MMU
265 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
266 default DRAM_BASE if !MMU
267 help
268 Please provide the physical address corresponding to the
269 location of main memory in your system.
271 config GENERIC_BUG
272 def_bool y
273 depends on BUG
275 source "init/Kconfig"
277 source "kernel/Kconfig.freezer"
279 menu "System Type"
281 config MMU
282 bool "MMU-based Paged Memory Management Support"
283 default y
284 help
285 Select if you want MMU-based virtualised addressing space
286 support by paged memory management. If unsure, say 'Y'.
288 #
289 # The "ARM system type" choice list is ordered alphabetically by option
290 # text. Please add new entries in the option alphabetic order.
291 #
292 choice
293 prompt "ARM system type"
294 default ARCH_VERSATILE if !MMU
295 default ARCH_MULTIPLATFORM if MMU
297 config ARCH_MULTIPLATFORM
298 bool "Allow multiple platforms to be selected"
299 depends on MMU
300 select ARCH_WANT_OPTIONAL_GPIOLIB
301 select ARM_HAS_SG_CHAIN
302 select ARM_PATCH_PHYS_VIRT
303 select AUTO_ZRELADDR
304 select CLKSRC_OF
305 select COMMON_CLK
306 select GENERIC_CLOCKEVENTS
307 select MIGHT_HAVE_PCI
308 select MULTI_IRQ_HANDLER
309 select SPARSE_IRQ
310 select USE_OF
312 config ARCH_INTEGRATOR
313 bool "ARM Ltd. Integrator family"
314 select ARM_AMBA
315 select ARM_PATCH_PHYS_VIRT
316 select AUTO_ZRELADDR
317 select COMMON_CLK
318 select COMMON_CLK_VERSATILE
319 select GENERIC_CLOCKEVENTS
320 select HAVE_TCM
321 select ICST
322 select MULTI_IRQ_HANDLER
323 select NEED_MACH_MEMORY_H
324 select PLAT_VERSATILE
325 select SPARSE_IRQ
326 select USE_OF
327 select VERSATILE_FPGA_IRQ
328 help
329 Support for ARM's Integrator platform.
331 config ARCH_REALVIEW
332 bool "ARM Ltd. RealView family"
333 select ARCH_WANT_OPTIONAL_GPIOLIB
334 select ARM_AMBA
335 select ARM_TIMER_SP804
336 select COMMON_CLK
337 select COMMON_CLK_VERSATILE
338 select GENERIC_CLOCKEVENTS
339 select GPIO_PL061 if GPIOLIB
340 select ICST
341 select NEED_MACH_MEMORY_H
342 select PLAT_VERSATILE
343 select PLAT_VERSATILE_CLCD
344 help
345 This enables support for ARM Ltd RealView boards.
347 config ARCH_VERSATILE
348 bool "ARM Ltd. Versatile family"
349 select ARCH_WANT_OPTIONAL_GPIOLIB
350 select ARM_AMBA
351 select ARM_TIMER_SP804
352 select ARM_VIC
353 select CLKDEV_LOOKUP
354 select GENERIC_CLOCKEVENTS
355 select HAVE_MACH_CLKDEV
356 select ICST
357 select PLAT_VERSATILE
358 select PLAT_VERSATILE_CLCD
359 select PLAT_VERSATILE_CLOCK
360 select VERSATILE_FPGA_IRQ
361 help
362 This enables support for ARM Ltd Versatile board.
364 config ARCH_AT91
365 bool "Atmel AT91"
366 select ARCH_REQUIRE_GPIOLIB
367 select CLKDEV_LOOKUP
368 select IRQ_DOMAIN
369 select NEED_MACH_IO_H if PCCARD
370 select PINCTRL
371 select PINCTRL_AT91 if USE_OF
372 help
373 This enables support for systems based on Atmel
374 AT91RM9200 and AT91SAM9* processors.
376 config ARCH_CLPS711X
377 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
378 select ARCH_REQUIRE_GPIOLIB
379 select AUTO_ZRELADDR
380 select CLKSRC_MMIO
381 select COMMON_CLK
382 select CPU_ARM720T
383 select GENERIC_CLOCKEVENTS
384 select MFD_SYSCON
385 help
386 Support for Cirrus Logic 711x/721x/731x based boards.
388 config ARCH_GEMINI
389 bool "Cortina Systems Gemini"
390 select ARCH_REQUIRE_GPIOLIB
391 select CLKSRC_MMIO
392 select CPU_FA526
393 select GENERIC_CLOCKEVENTS
394 help
395 Support for the Cortina Systems Gemini family SoCs
397 config ARCH_EBSA110
398 bool "EBSA-110"
399 select ARCH_USES_GETTIMEOFFSET
400 select CPU_SA110
401 select ISA
402 select NEED_MACH_IO_H
403 select NEED_MACH_MEMORY_H
404 select NO_IOPORT_MAP
405 help
406 This is an evaluation board for the StrongARM processor available
407 from Digital. It has limited hardware on-board, including an
408 Ethernet interface, two PCMCIA sockets, two serial ports and a
409 parallel port.
411 config ARCH_EFM32
412 bool "Energy Micro efm32"
413 depends on !MMU
414 select ARCH_REQUIRE_GPIOLIB
415 select ARM_NVIC
416 select AUTO_ZRELADDR
417 select CLKSRC_OF
418 select COMMON_CLK
419 select CPU_V7M
420 select GENERIC_CLOCKEVENTS
421 select NO_DMA
422 select NO_IOPORT_MAP
423 select SPARSE_IRQ
424 select USE_OF
425 help
426 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
427 processors.
429 config ARCH_EP93XX
430 bool "EP93xx-based"
431 select ARCH_HAS_HOLES_MEMORYMODEL
432 select ARCH_REQUIRE_GPIOLIB
433 select ARCH_USES_GETTIMEOFFSET
434 select ARM_AMBA
435 select ARM_VIC
436 select CLKDEV_LOOKUP
437 select CPU_ARM920T
438 select NEED_MACH_MEMORY_H
439 help
440 This enables support for the Cirrus EP93xx series of CPUs.
442 config ARCH_FOOTBRIDGE
443 bool "FootBridge"
444 select CPU_SA110
445 select FOOTBRIDGE
446 select GENERIC_CLOCKEVENTS
447 select HAVE_IDE
448 select NEED_MACH_IO_H if !MMU
449 select NEED_MACH_MEMORY_H
450 help
451 Support for systems based on the DC21285 companion chip
452 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
454 config ARCH_NETX
455 bool "Hilscher NetX based"
456 select ARM_VIC
457 select CLKSRC_MMIO
458 select CPU_ARM926T
459 select GENERIC_CLOCKEVENTS
460 help
461 This enables support for systems based on the Hilscher NetX Soc
463 config ARCH_IOP13XX
464 bool "IOP13xx-based"
465 depends on MMU
466 select CPU_XSC3
467 select NEED_MACH_MEMORY_H
468 select NEED_RET_TO_USER
469 select PCI
470 select PLAT_IOP
471 select VMSPLIT_1G
472 select SPARSE_IRQ
473 help
474 Support for Intel's IOP13XX (XScale) family of processors.
476 config ARCH_IOP32X
477 bool "IOP32x-based"
478 depends on MMU
479 select ARCH_REQUIRE_GPIOLIB
480 select CPU_XSCALE
481 select GPIO_IOP
482 select NEED_RET_TO_USER
483 select PCI
484 select PLAT_IOP
485 help
486 Support for Intel's 80219 and IOP32X (XScale) family of
487 processors.
489 config ARCH_IOP33X
490 bool "IOP33x-based"
491 depends on MMU
492 select ARCH_REQUIRE_GPIOLIB
493 select CPU_XSCALE
494 select GPIO_IOP
495 select NEED_RET_TO_USER
496 select PCI
497 select PLAT_IOP
498 help
499 Support for Intel's IOP33X (XScale) family of processors.
501 config ARCH_IXP4XX
502 bool "IXP4xx-based"
503 depends on MMU
504 select ARCH_HAS_DMA_SET_COHERENT_MASK
505 select ARCH_REQUIRE_GPIOLIB
506 select ARCH_SUPPORTS_BIG_ENDIAN
507 select CLKSRC_MMIO
508 select CPU_XSCALE
509 select DMABOUNCE if PCI
510 select GENERIC_CLOCKEVENTS
511 select MIGHT_HAVE_PCI
512 select NEED_MACH_IO_H
513 select USB_EHCI_BIG_ENDIAN_DESC
514 select USB_EHCI_BIG_ENDIAN_MMIO
515 help
516 Support for Intel's IXP4XX (XScale) family of processors.
518 config ARCH_DOVE
519 bool "Marvell Dove"
520 select ARCH_REQUIRE_GPIOLIB
521 select CPU_PJ4
522 select GENERIC_CLOCKEVENTS
523 select MIGHT_HAVE_PCI
524 select MVEBU_MBUS
525 select PINCTRL
526 select PINCTRL_DOVE
527 select PLAT_ORION_LEGACY
528 help
529 Support for the Marvell Dove SoC 88AP510
531 config ARCH_KIRKWOOD
532 bool "Marvell Kirkwood"
533 select ARCH_REQUIRE_GPIOLIB
534 select CPU_FEROCEON
535 select GENERIC_CLOCKEVENTS
536 select MVEBU_MBUS
537 select PCI
538 select PCI_QUIRKS
539 select PINCTRL
540 select PINCTRL_KIRKWOOD
541 select PLAT_ORION_LEGACY
542 help
543 Support for the following Marvell Kirkwood series SoCs:
544 88F6180, 88F6192 and 88F6281.
546 config ARCH_MV78XX0
547 bool "Marvell MV78xx0"
548 select ARCH_REQUIRE_GPIOLIB
549 select CPU_FEROCEON
550 select GENERIC_CLOCKEVENTS
551 select MVEBU_MBUS
552 select PCI
553 select PLAT_ORION_LEGACY
554 help
555 Support for the following Marvell MV78xx0 series SoCs:
556 MV781x0, MV782x0.
558 config ARCH_ORION5X
559 bool "Marvell Orion"
560 depends on MMU
561 select ARCH_REQUIRE_GPIOLIB
562 select CPU_FEROCEON
563 select GENERIC_CLOCKEVENTS
564 select MVEBU_MBUS
565 select PCI
566 select PLAT_ORION_LEGACY
567 help
568 Support for the following Marvell Orion 5x series SoCs:
569 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
570 Orion-2 (5281), Orion-1-90 (6183).
572 config ARCH_MMP
573 bool "Marvell PXA168/910/MMP2"
574 depends on MMU
575 select ARCH_REQUIRE_GPIOLIB
576 select CLKDEV_LOOKUP
577 select GENERIC_ALLOCATOR
578 select GENERIC_CLOCKEVENTS
579 select GPIO_PXA
580 select IRQ_DOMAIN
581 select MULTI_IRQ_HANDLER
582 select PINCTRL
583 select PLAT_PXA
584 select SPARSE_IRQ
585 help
586 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
588 config ARCH_KS8695
589 bool "Micrel/Kendin KS8695"
590 select ARCH_REQUIRE_GPIOLIB
591 select CLKSRC_MMIO
592 select CPU_ARM922T
593 select GENERIC_CLOCKEVENTS
594 select NEED_MACH_MEMORY_H
595 help
596 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
597 System-on-Chip devices.
599 config ARCH_W90X900
600 bool "Nuvoton W90X900 CPU"
601 select ARCH_REQUIRE_GPIOLIB
602 select CLKDEV_LOOKUP
603 select CLKSRC_MMIO
604 select CPU_ARM926T
605 select GENERIC_CLOCKEVENTS
606 help
607 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
608 At present, the w90x900 has been renamed nuc900, regarding
609 the ARM series product line, you can login the following
610 link address to know more.
612 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
613 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
615 config ARCH_LPC32XX
616 bool "NXP LPC32XX"
617 select ARCH_REQUIRE_GPIOLIB
618 select ARM_AMBA
619 select CLKDEV_LOOKUP
620 select CLKSRC_MMIO
621 select CPU_ARM926T
622 select GENERIC_CLOCKEVENTS
623 select HAVE_IDE
624 select USE_OF
625 help
626 Support for the NXP LPC32XX family of processors
628 config ARCH_PXA
629 bool "PXA2xx/PXA3xx-based"
630 depends on MMU
631 select ARCH_MTD_XIP
632 select ARCH_REQUIRE_GPIOLIB
633 select ARM_CPU_SUSPEND if PM
634 select AUTO_ZRELADDR
635 select CLKDEV_LOOKUP
636 select CLKSRC_MMIO
637 select GENERIC_CLOCKEVENTS
638 select GPIO_PXA
639 select HAVE_IDE
640 select MULTI_IRQ_HANDLER
641 select PLAT_PXA
642 select SPARSE_IRQ
643 help
644 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
646 config ARCH_MSM
647 bool "Qualcomm MSM (non-multiplatform)"
648 select ARCH_REQUIRE_GPIOLIB
649 select COMMON_CLK
650 select GENERIC_CLOCKEVENTS
651 help
652 Support for Qualcomm MSM/QSD based systems. This runs on the
653 apps processor of the MSM/QSD and depends on a shared memory
654 interface to the modem processor which runs the baseband
655 stack and controls some vital subsystems
656 (clock and power control, etc).
658 config ARCH_SHMOBILE_LEGACY
659 bool "Renesas ARM SoCs (non-multiplatform)"
660 select ARCH_SHMOBILE
661 select ARM_PATCH_PHYS_VIRT
662 select CLKDEV_LOOKUP
663 select GENERIC_CLOCKEVENTS
664 select HAVE_ARM_SCU if SMP
665 select HAVE_ARM_TWD if SMP
666 select HAVE_MACH_CLKDEV
667 select HAVE_SMP
668 select MIGHT_HAVE_CACHE_L2X0
669 select MULTI_IRQ_HANDLER
670 select NO_IOPORT_MAP
671 select PINCTRL
672 select PM_GENERIC_DOMAINS if PM
673 select SPARSE_IRQ
674 help
675 Support for Renesas ARM SoC platforms using a non-multiplatform
676 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
677 and RZ families.
679 config ARCH_RPC
680 bool "RiscPC"
681 select ARCH_ACORN
682 select ARCH_MAY_HAVE_PC_FDC
683 select ARCH_SPARSEMEM_ENABLE
684 select ARCH_USES_GETTIMEOFFSET
685 select CPU_SA110
686 select FIQ
687 select HAVE_IDE
688 select HAVE_PATA_PLATFORM
689 select ISA_DMA_API
690 select NEED_MACH_IO_H
691 select NEED_MACH_MEMORY_H
692 select NO_IOPORT_MAP
693 select VIRT_TO_BUS
694 help
695 On the Acorn Risc-PC, Linux can support the internal IDE disk and
696 CD-ROM interface, serial and parallel port, and the floppy drive.
698 config ARCH_SA1100
699 bool "SA1100-based"
700 select ARCH_MTD_XIP
701 select ARCH_REQUIRE_GPIOLIB
702 select ARCH_SPARSEMEM_ENABLE
703 select CLKDEV_LOOKUP
704 select CLKSRC_MMIO
705 select CPU_FREQ
706 select CPU_SA1100
707 select GENERIC_CLOCKEVENTS
708 select HAVE_IDE
709 select ISA
710 select NEED_MACH_MEMORY_H
711 select SPARSE_IRQ
712 help
713 Support for StrongARM 11x0 based boards.
715 config ARCH_S3C24XX
716 bool "Samsung S3C24XX SoCs"
717 select ARCH_REQUIRE_GPIOLIB
718 select ATAGS
719 select CLKDEV_LOOKUP
720 select CLKSRC_SAMSUNG_PWM
721 select GENERIC_CLOCKEVENTS
722 select GPIO_SAMSUNG
723 select HAVE_S3C2410_I2C if I2C
724 select HAVE_S3C2410_WATCHDOG if WATCHDOG
725 select HAVE_S3C_RTC if RTC_CLASS
726 select MULTI_IRQ_HANDLER
727 select NEED_MACH_IO_H
728 select SAMSUNG_ATAGS
729 help
730 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
731 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
732 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
733 Samsung SMDK2410 development board (and derivatives).
735 config ARCH_S3C64XX
736 bool "Samsung S3C64XX"
737 select ARCH_REQUIRE_GPIOLIB
738 select ARM_AMBA
739 select ARM_VIC
740 select ATAGS
741 select CLKDEV_LOOKUP
742 select CLKSRC_SAMSUNG_PWM
743 select COMMON_CLK_SAMSUNG
744 select CPU_V6K
745 select GENERIC_CLOCKEVENTS
746 select GPIO_SAMSUNG
747 select HAVE_S3C2410_I2C if I2C
748 select HAVE_S3C2410_WATCHDOG if WATCHDOG
749 select HAVE_TCM
750 select NO_IOPORT_MAP
751 select PLAT_SAMSUNG
752 select PM_GENERIC_DOMAINS if PM
753 select S3C_DEV_NAND
754 select S3C_GPIO_TRACK
755 select SAMSUNG_ATAGS
756 select SAMSUNG_WAKEMASK
757 select SAMSUNG_WDT_RESET
758 help
759 Samsung S3C64XX series based systems
761 config ARCH_S5P64X0
762 bool "Samsung S5P6440 S5P6450"
763 select ATAGS
764 select CLKDEV_LOOKUP
765 select CLKSRC_SAMSUNG_PWM
766 select CPU_V6
767 select GENERIC_CLOCKEVENTS
768 select GPIO_SAMSUNG
769 select HAVE_S3C2410_I2C if I2C
770 select HAVE_S3C2410_WATCHDOG if WATCHDOG
771 select HAVE_S3C_RTC if RTC_CLASS
772 select NEED_MACH_GPIO_H
773 select SAMSUNG_ATAGS
774 select SAMSUNG_WDT_RESET
775 help
776 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
777 SMDK6450.
779 config ARCH_S5PC100
780 bool "Samsung S5PC100"
781 select ARCH_REQUIRE_GPIOLIB
782 select ATAGS
783 select CLKDEV_LOOKUP
784 select CLKSRC_SAMSUNG_PWM
785 select CPU_V7
786 select GENERIC_CLOCKEVENTS
787 select GPIO_SAMSUNG
788 select HAVE_S3C2410_I2C if I2C
789 select HAVE_S3C2410_WATCHDOG if WATCHDOG
790 select HAVE_S3C_RTC if RTC_CLASS
791 select NEED_MACH_GPIO_H
792 select SAMSUNG_ATAGS
793 select SAMSUNG_WDT_RESET
794 help
795 Samsung S5PC100 series based systems
797 config ARCH_S5PV210
798 bool "Samsung S5PV210/S5PC110"
799 select ARCH_HAS_HOLES_MEMORYMODEL
800 select ARCH_SPARSEMEM_ENABLE
801 select ATAGS
802 select CLKDEV_LOOKUP
803 select CLKSRC_SAMSUNG_PWM
804 select CPU_V7
805 select GENERIC_CLOCKEVENTS
806 select GPIO_SAMSUNG
807 select HAVE_S3C2410_I2C if I2C
808 select HAVE_S3C2410_WATCHDOG if WATCHDOG
809 select HAVE_S3C_RTC if RTC_CLASS
810 select NEED_MACH_GPIO_H
811 select NEED_MACH_MEMORY_H
812 select SAMSUNG_ATAGS
813 help
814 Samsung S5PV210/S5PC110 series based systems
816 config ARCH_DAVINCI
817 bool "TI DaVinci"
818 select ARCH_HAS_HOLES_MEMORYMODEL
819 select ARCH_REQUIRE_GPIOLIB
820 select CLKDEV_LOOKUP
821 select GENERIC_ALLOCATOR
822 select GENERIC_CLOCKEVENTS
823 select GENERIC_IRQ_CHIP
824 select HAVE_IDE
825 select TI_PRIV_EDMA
826 select USE_OF
827 select ZONE_DMA
828 help
829 Support for TI's DaVinci platform.
831 config ARCH_OMAP1
832 bool "TI OMAP1"
833 depends on MMU
834 select ARCH_HAS_HOLES_MEMORYMODEL
835 select ARCH_OMAP
836 select ARCH_REQUIRE_GPIOLIB
837 select CLKDEV_LOOKUP
838 select CLKSRC_MMIO
839 select GENERIC_CLOCKEVENTS
840 select GENERIC_IRQ_CHIP
841 select HAVE_IDE
842 select IRQ_DOMAIN
843 select NEED_MACH_IO_H if PCCARD
844 select NEED_MACH_MEMORY_H
845 help
846 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
848 endchoice
850 menu "Multiple platform selection"
851 depends on ARCH_MULTIPLATFORM
853 comment "CPU Core family selection"
855 config ARCH_MULTI_V4
856 bool "ARMv4 based platforms (FA526)"
857 depends on !ARCH_MULTI_V6_V7
858 select ARCH_MULTI_V4_V5
859 select CPU_FA526
861 config ARCH_MULTI_V4T
862 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
863 depends on !ARCH_MULTI_V6_V7
864 select ARCH_MULTI_V4_V5
865 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
866 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
867 CPU_ARM925T || CPU_ARM940T)
869 config ARCH_MULTI_V5
870 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
871 depends on !ARCH_MULTI_V6_V7
872 select ARCH_MULTI_V4_V5
873 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
874 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
875 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
877 config ARCH_MULTI_V4_V5
878 bool
880 config ARCH_MULTI_V6
881 bool "ARMv6 based platforms (ARM11)"
882 select ARCH_MULTI_V6_V7
883 select CPU_V6K
885 config ARCH_MULTI_V7
886 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
887 default y
888 select ARCH_MULTI_V6_V7
889 select CPU_V7
890 select HAVE_SMP
892 config ARCH_MULTI_V6_V7
893 bool
894 select MIGHT_HAVE_CACHE_L2X0
896 config ARCH_MULTI_CPU_AUTO
897 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
898 select ARCH_MULTI_V5
900 endmenu
902 config ARCH_VIRT
903 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
904 select ARM_AMBA
905 select ARM_GIC
906 select ARM_PSCI
907 select HAVE_ARM_ARCH_TIMER
909 #
910 # This is sorted alphabetically by mach-* pathname. However, plat-*
911 # Kconfigs may be included either alphabetically (according to the
912 # plat- suffix) or along side the corresponding mach-* source.
913 #
914 source "arch/arm/mach-mvebu/Kconfig"
916 source "arch/arm/mach-at91/Kconfig"
918 source "arch/arm/mach-axxia/Kconfig"
920 source "arch/arm/mach-bcm/Kconfig"
922 source "arch/arm/mach-berlin/Kconfig"
924 source "arch/arm/mach-clps711x/Kconfig"
926 source "arch/arm/mach-cns3xxx/Kconfig"
928 source "arch/arm/mach-davinci/Kconfig"
930 source "arch/arm/mach-dove/Kconfig"
932 source "arch/arm/mach-ep93xx/Kconfig"
934 source "arch/arm/mach-footbridge/Kconfig"
936 source "arch/arm/mach-gemini/Kconfig"
938 source "arch/arm/mach-highbank/Kconfig"
940 source "arch/arm/mach-hisi/Kconfig"
942 source "arch/arm/mach-integrator/Kconfig"
944 source "arch/arm/mach-iop32x/Kconfig"
946 source "arch/arm/mach-iop33x/Kconfig"
948 source "arch/arm/mach-iop13xx/Kconfig"
950 source "arch/arm/mach-ixp4xx/Kconfig"
952 source "arch/arm/mach-keystone/Kconfig"
954 source "arch/arm/mach-kirkwood/Kconfig"
956 source "arch/arm/mach-ks8695/Kconfig"
958 source "arch/arm/mach-msm/Kconfig"
960 source "arch/arm/mach-moxart/Kconfig"
962 source "arch/arm/mach-mv78xx0/Kconfig"
964 source "arch/arm/mach-imx/Kconfig"
966 source "arch/arm/mach-mxs/Kconfig"
968 source "arch/arm/mach-netx/Kconfig"
970 source "arch/arm/mach-nomadik/Kconfig"
972 source "arch/arm/mach-nspire/Kconfig"
974 source "arch/arm/plat-omap/Kconfig"
976 source "arch/arm/mach-omap1/Kconfig"
978 source "arch/arm/mach-omap2/Kconfig"
980 source "arch/arm/mach-orion5x/Kconfig"
982 source "arch/arm/mach-picoxcell/Kconfig"
984 source "arch/arm/mach-pxa/Kconfig"
985 source "arch/arm/plat-pxa/Kconfig"
987 source "arch/arm/mach-mmp/Kconfig"
989 source "arch/arm/mach-qcom/Kconfig"
991 source "arch/arm/mach-realview/Kconfig"
993 source "arch/arm/mach-rockchip/Kconfig"
995 source "arch/arm/mach-sa1100/Kconfig"
997 source "arch/arm/mach-socfpga/Kconfig"
999 source "arch/arm/mach-spear/Kconfig"
1001 source "arch/arm/mach-sti/Kconfig"
1003 source "arch/arm/mach-s3c24xx/Kconfig"
1005 source "arch/arm/mach-s3c64xx/Kconfig"
1007 source "arch/arm/mach-s5p64x0/Kconfig"
1009 source "arch/arm/mach-s5pc100/Kconfig"
1011 source "arch/arm/mach-s5pv210/Kconfig"
1013 source "arch/arm/mach-exynos/Kconfig"
1014 source "arch/arm/plat-samsung/Kconfig"
1016 source "arch/arm/mach-shmobile/Kconfig"
1018 source "arch/arm/mach-sunxi/Kconfig"
1020 source "arch/arm/mach-prima2/Kconfig"
1022 source "arch/arm/mach-tegra/Kconfig"
1024 source "arch/arm/mach-u300/Kconfig"
1026 source "arch/arm/mach-ux500/Kconfig"
1028 source "arch/arm/mach-versatile/Kconfig"
1030 source "arch/arm/mach-vexpress/Kconfig"
1031 source "arch/arm/plat-versatile/Kconfig"
1033 source "arch/arm/mach-vt8500/Kconfig"
1035 source "arch/arm/mach-w90x900/Kconfig"
1037 source "arch/arm/mach-zynq/Kconfig"
1039 # Definitions to make life easier
1040 config ARCH_ACORN
1041 bool
1043 config PLAT_IOP
1044 bool
1045 select GENERIC_CLOCKEVENTS
1047 config PLAT_ORION
1048 bool
1049 select CLKSRC_MMIO
1050 select COMMON_CLK
1051 select GENERIC_IRQ_CHIP
1052 select IRQ_DOMAIN
1054 config PLAT_ORION_LEGACY
1055 bool
1056 select PLAT_ORION
1058 config PLAT_PXA
1059 bool
1061 config PLAT_VERSATILE
1062 bool
1064 config ARM_TIMER_SP804
1065 bool
1066 select CLKSRC_MMIO
1067 select CLKSRC_OF if OF
1069 source "arch/arm/firmware/Kconfig"
1071 source arch/arm/mm/Kconfig
1073 config IWMMXT
1074 bool "Enable iWMMXt support"
1075 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1076 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1077 help
1078 Enable support for iWMMXt context switching at run time if
1079 running on a CPU that supports it.
1081 config MULTI_IRQ_HANDLER
1082 bool
1083 help
1084 Allow each machine to specify it's own IRQ handler at run time.
1086 if !MMU
1087 source "arch/arm/Kconfig-nommu"
1088 endif
1090 config PJ4B_ERRATA_4742
1091 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1092 depends on CPU_PJ4B && MACH_ARMADA_370
1093 default y
1094 help
1095 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1096 Event (WFE) IDLE states, a specific timing sensitivity exists between
1097 the retiring WFI/WFE instructions and the newly issued subsequent
1098 instructions. This sensitivity can result in a CPU hang scenario.
1099 Workaround:
1100 The software must insert either a Data Synchronization Barrier (DSB)
1101 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1102 instruction
1104 config ARM_ERRATA_326103
1105 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1106 depends on CPU_V6
1107 help
1108 Executing a SWP instruction to read-only memory does not set bit 11
1109 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1110 treat the access as a read, preventing a COW from occurring and
1111 causing the faulting task to livelock.
1113 config ARM_ERRATA_411920
1114 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1115 depends on CPU_V6 || CPU_V6K
1116 help
1117 Invalidation of the Instruction Cache operation can
1118 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1119 It does not affect the MPCore. This option enables the ARM Ltd.
1120 recommended workaround.
1122 config ARM_ERRATA_430973
1123 bool "ARM errata: Stale prediction on replaced interworking branch"
1124 depends on CPU_V7
1125 help
1126 This option enables the workaround for the 430973 Cortex-A8
1127 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1128 interworking branch is replaced with another code sequence at the
1129 same virtual address, whether due to self-modifying code or virtual
1130 to physical address re-mapping, Cortex-A8 does not recover from the
1131 stale interworking branch prediction. This results in Cortex-A8
1132 executing the new code sequence in the incorrect ARM or Thumb state.
1133 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1134 and also flushes the branch target cache at every context switch.
1135 Note that setting specific bits in the ACTLR register may not be
1136 available in non-secure mode.
1138 config ARM_ERRATA_458693
1139 bool "ARM errata: Processor deadlock when a false hazard is created"
1140 depends on CPU_V7
1141 depends on !ARCH_MULTIPLATFORM
1142 help
1143 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1144 erratum. For very specific sequences of memory operations, it is
1145 possible for a hazard condition intended for a cache line to instead
1146 be incorrectly associated with a different cache line. This false
1147 hazard might then cause a processor deadlock. The workaround enables
1148 the L1 caching of the NEON accesses and disables the PLD instruction
1149 in the ACTLR register. Note that setting specific bits in the ACTLR
1150 register may not be available in non-secure mode.
1152 config ARM_ERRATA_460075
1153 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1154 depends on CPU_V7
1155 depends on !ARCH_MULTIPLATFORM
1156 help
1157 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1158 erratum. Any asynchronous access to the L2 cache may encounter a
1159 situation in which recent store transactions to the L2 cache are lost
1160 and overwritten with stale memory contents from external memory. The
1161 workaround disables the write-allocate mode for the L2 cache via the
1162 ACTLR register. Note that setting specific bits in the ACTLR register
1163 may not be available in non-secure mode.
1165 config ARM_ERRATA_742230
1166 bool "ARM errata: DMB operation may be faulty"
1167 depends on CPU_V7 && SMP
1168 depends on !ARCH_MULTIPLATFORM
1169 help
1170 This option enables the workaround for the 742230 Cortex-A9
1171 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1172 between two write operations may not ensure the correct visibility
1173 ordering of the two writes. This workaround sets a specific bit in
1174 the diagnostic register of the Cortex-A9 which causes the DMB
1175 instruction to behave as a DSB, ensuring the correct behaviour of
1176 the two writes.
1178 config ARM_ERRATA_742231
1179 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1180 depends on CPU_V7 && SMP
1181 depends on !ARCH_MULTIPLATFORM
1182 help
1183 This option enables the workaround for the 742231 Cortex-A9
1184 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1185 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1186 accessing some data located in the same cache line, may get corrupted
1187 data due to bad handling of the address hazard when the line gets
1188 replaced from one of the CPUs at the same time as another CPU is
1189 accessing it. This workaround sets specific bits in the diagnostic
1190 register of the Cortex-A9 which reduces the linefill issuing
1191 capabilities of the processor.
1193 config ARM_ERRATA_643719
1194 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1195 depends on CPU_V7 && SMP
1196 help
1197 This option enables the workaround for the 643719 Cortex-A9 (prior to
1198 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1199 register returns zero when it should return one. The workaround
1200 corrects this value, ensuring cache maintenance operations which use
1201 it behave as intended and avoiding data corruption.
1203 config ARM_ERRATA_720789
1204 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1205 depends on CPU_V7
1206 help
1207 This option enables the workaround for the 720789 Cortex-A9 (prior to
1208 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1209 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1210 As a consequence of this erratum, some TLB entries which should be
1211 invalidated are not, resulting in an incoherency in the system page
1212 tables. The workaround changes the TLB flushing routines to invalidate
1213 entries regardless of the ASID.
1215 config ARM_ERRATA_743622
1216 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1217 depends on CPU_V7
1218 depends on !ARCH_MULTIPLATFORM
1219 help
1220 This option enables the workaround for the 743622 Cortex-A9
1221 (r2p*) erratum. Under very rare conditions, a faulty
1222 optimisation in the Cortex-A9 Store Buffer may lead to data
1223 corruption. This workaround sets a specific bit in the diagnostic
1224 register of the Cortex-A9 which disables the Store Buffer
1225 optimisation, preventing the defect from occurring. This has no
1226 visible impact on the overall performance or power consumption of the
1227 processor.
1229 config ARM_ERRATA_751472
1230 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1231 depends on CPU_V7
1232 depends on !ARCH_MULTIPLATFORM
1233 help
1234 This option enables the workaround for the 751472 Cortex-A9 (prior
1235 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1236 completion of a following broadcasted operation if the second
1237 operation is received by a CPU before the ICIALLUIS has completed,
1238 potentially leading to corrupted entries in the cache or TLB.
1240 config ARM_ERRATA_754322
1241 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1242 depends on CPU_V7
1243 help
1244 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1245 r3p*) erratum. A speculative memory access may cause a page table walk
1246 which starts prior to an ASID switch but completes afterwards. This
1247 can populate the micro-TLB with a stale entry which may be hit with
1248 the new ASID. This workaround places two dsb instructions in the mm
1249 switching code so that no page table walks can cross the ASID switch.
1251 config ARM_ERRATA_754327
1252 bool "ARM errata: no automatic Store Buffer drain"
1253 depends on CPU_V7 && SMP
1254 help
1255 This option enables the workaround for the 754327 Cortex-A9 (prior to
1256 r2p0) erratum. The Store Buffer does not have any automatic draining
1257 mechanism and therefore a livelock may occur if an external agent
1258 continuously polls a memory location waiting to observe an update.
1259 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1260 written polling loops from denying visibility of updates to memory.
1262 config ARM_ERRATA_364296
1263 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1264 depends on CPU_V6
1265 help
1266 This options enables the workaround for the 364296 ARM1136
1267 r0p2 erratum (possible cache data corruption with
1268 hit-under-miss enabled). It sets the undocumented bit 31 in
1269 the auxiliary control register and the FI bit in the control
1270 register, thus disabling hit-under-miss without putting the
1271 processor into full low interrupt latency mode. ARM11MPCore
1272 is not affected.
1274 config ARM_ERRATA_764369
1275 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1276 depends on CPU_V7 && SMP
1277 help
1278 This option enables the workaround for erratum 764369
1279 affecting Cortex-A9 MPCore with two or more processors (all
1280 current revisions). Under certain timing circumstances, a data
1281 cache line maintenance operation by MVA targeting an Inner
1282 Shareable memory region may fail to proceed up to either the
1283 Point of Coherency or to the Point of Unification of the
1284 system. This workaround adds a DSB instruction before the
1285 relevant cache maintenance functions and sets a specific bit
1286 in the diagnostic control register of the SCU.
1288 config ARM_ERRATA_775420
1289 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1290 depends on CPU_V7
1291 help
1292 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1293 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1294 operation aborts with MMU exception, it might cause the processor
1295 to deadlock. This workaround puts DSB before executing ISB if
1296 an abort may occur on cache maintenance.
1298 config ARM_ERRATA_798181
1299 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1300 depends on CPU_V7 && SMP
1301 help
1302 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1303 adequately shooting down all use of the old entries. This
1304 option enables the Linux kernel workaround for this erratum
1305 which sends an IPI to the CPUs that are running the same ASID
1306 as the one being invalidated.
1308 config ARM_ERRATA_773022
1309 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1310 depends on CPU_V7
1311 help
1312 This option enables the workaround for the 773022 Cortex-A15
1313 (up to r0p4) erratum. In certain rare sequences of code, the
1314 loop buffer may deliver incorrect instructions. This
1315 workaround disables the loop buffer to avoid the erratum.
1317 endmenu
1319 source "arch/arm/common/Kconfig"
1321 menu "Bus support"
1323 config ARM_AMBA
1324 bool
1326 config ISA
1327 bool
1328 help
1329 Find out whether you have ISA slots on your motherboard. ISA is the
1330 name of a bus system, i.e. the way the CPU talks to the other stuff
1331 inside your box. Other bus systems are PCI, EISA, MicroChannel
1332 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1333 newer boards don't support it. If you have ISA, say Y, otherwise N.
1335 # Select ISA DMA controller support
1336 config ISA_DMA
1337 bool
1338 select ISA_DMA_API
1340 # Select ISA DMA interface
1341 config ISA_DMA_API
1342 bool
1344 config PCI
1345 bool "PCI support" if MIGHT_HAVE_PCI
1346 help
1347 Find out whether you have a PCI motherboard. PCI is the name of a
1348 bus system, i.e. the way the CPU talks to the other stuff inside
1349 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1350 VESA. If you have PCI, say Y, otherwise N.
1352 config PCI_DOMAINS
1353 bool
1354 depends on PCI
1356 config PCI_NANOENGINE
1357 bool "BSE nanoEngine PCI support"
1358 depends on SA1100_NANOENGINE
1359 help
1360 Enable PCI on the BSE nanoEngine board.
1362 config PCI_SYSCALL
1363 def_bool PCI
1365 config PCI_HOST_ITE8152
1366 bool
1367 depends on PCI && MACH_ARMCORE
1368 default y
1369 select DMABOUNCE
1371 source "drivers/pci/Kconfig"
1372 source "drivers/pci/pcie/Kconfig"
1374 source "drivers/pcmcia/Kconfig"
1376 endmenu
1378 menu "Kernel Features"
1380 config HAVE_SMP
1381 bool
1382 help
1383 This option should be selected by machines which have an SMP-
1384 capable CPU.
1386 The only effect of this option is to make the SMP-related
1387 options available to the user for configuration.
1389 config SMP
1390 bool "Symmetric Multi-Processing"
1391 depends on CPU_V6K || CPU_V7
1392 depends on GENERIC_CLOCKEVENTS
1393 depends on HAVE_SMP
1394 depends on MMU || ARM_MPU
1395 help
1396 This enables support for systems with more than one CPU. If you have
1397 a system with only one CPU, say N. If you have a system with more
1398 than one CPU, say Y.
1400 If you say N here, the kernel will run on uni- and multiprocessor
1401 machines, but will use only one CPU of a multiprocessor machine. If
1402 you say Y here, the kernel will run on many, but not all,
1403 uniprocessor machines. On a uniprocessor machine, the kernel
1404 will run faster if you say N here.
1406 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1407 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1408 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1410 If you don't know what to do here, say N.
1412 config SMP_ON_UP
1413 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1414 depends on SMP && !XIP_KERNEL && MMU
1415 default y
1416 help
1417 SMP kernels contain instructions which fail on non-SMP processors.
1418 Enabling this option allows the kernel to modify itself to make
1419 these instructions safe. Disabling it allows about 1K of space
1420 savings.
1422 If you don't know what to do here, say Y.
1424 config ARM_CPU_TOPOLOGY
1425 bool "Support cpu topology definition"
1426 depends on SMP && CPU_V7
1427 default y
1428 help
1429 Support ARM cpu topology definition. The MPIDR register defines
1430 affinity between processors which is then used to describe the cpu
1431 topology of an ARM System.
1433 config SCHED_MC
1434 bool "Multi-core scheduler support"
1435 depends on ARM_CPU_TOPOLOGY
1436 help
1437 Multi-core scheduler support improves the CPU scheduler's decision
1438 making when dealing with multi-core CPU chips at a cost of slightly
1439 increased overhead in some places. If unsure say N here.
1441 config SCHED_SMT
1442 bool "SMT scheduler support"
1443 depends on ARM_CPU_TOPOLOGY
1444 help
1445 Improves the CPU scheduler's decision making when dealing with
1446 MultiThreading at a cost of slightly increased overhead in some
1447 places. If unsure say N here.
1449 config HAVE_ARM_SCU
1450 bool
1451 help
1452 This option enables support for the ARM system coherency unit
1454 config HAVE_ARM_ARCH_TIMER
1455 bool "Architected timer support"
1456 depends on CPU_V7
1457 select ARM_ARCH_TIMER
1458 select GENERIC_CLOCKEVENTS
1459 help
1460 This option enables support for the ARM architected timer
1462 config HAVE_ARM_TWD
1463 bool
1464 depends on SMP
1465 select CLKSRC_OF if OF
1466 help
1467 This options enables support for the ARM timer and watchdog unit
1469 config MCPM
1470 bool "Multi-Cluster Power Management"
1471 depends on CPU_V7 && SMP
1472 help
1473 This option provides the common power management infrastructure
1474 for (multi-)cluster based systems, such as big.LITTLE based
1475 systems.
1477 config BIG_LITTLE
1478 bool "big.LITTLE support (Experimental)"
1479 depends on CPU_V7 && SMP
1480 select MCPM
1481 help
1482 This option enables support selections for the big.LITTLE
1483 system architecture.
1485 config BL_SWITCHER
1486 bool "big.LITTLE switcher support"
1487 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1488 select ARM_CPU_SUSPEND
1489 select CPU_PM
1490 help
1491 The big.LITTLE "switcher" provides the core functionality to
1492 transparently handle transition between a cluster of A15's
1493 and a cluster of A7's in a big.LITTLE system.
1495 config BL_SWITCHER_DUMMY_IF
1496 tristate "Simple big.LITTLE switcher user interface"
1497 depends on BL_SWITCHER && DEBUG_KERNEL
1498 help
1499 This is a simple and dummy char dev interface to control
1500 the big.LITTLE switcher core code. It is meant for
1501 debugging purposes only.
1503 choice
1504 prompt "Memory split"
1505 depends on MMU
1506 default VMSPLIT_3G
1507 help
1508 Select the desired split between kernel and user memory.
1510 If you are not absolutely sure what you are doing, leave this
1511 option alone!
1513 config VMSPLIT_3G
1514 bool "3G/1G user/kernel split"
1515 config VMSPLIT_2G
1516 bool "2G/2G user/kernel split"
1517 config VMSPLIT_1G
1518 bool "1G/3G user/kernel split"
1519 endchoice
1521 config PAGE_OFFSET
1522 hex
1523 default PHYS_OFFSET if !MMU
1524 default 0x40000000 if VMSPLIT_1G
1525 default 0x80000000 if VMSPLIT_2G
1526 default 0xC0000000
1528 config NR_CPUS
1529 int "Maximum number of CPUs (2-32)"
1530 range 2 32
1531 depends on SMP
1532 default "4"
1534 config HOTPLUG_CPU
1535 bool "Support for hot-pluggable CPUs"
1536 depends on SMP
1537 help
1538 Say Y here to experiment with turning CPUs off and on. CPUs
1539 can be controlled through /sys/devices/system/cpu.
1541 config ARM_PSCI
1542 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1543 depends on CPU_V7
1544 help
1545 Say Y here if you want Linux to communicate with system firmware
1546 implementing the PSCI specification for CPU-centric power
1547 management operations described in ARM document number ARM DEN
1548 0022A ("Power State Coordination Interface System Software on
1549 ARM processors").
1551 # The GPIO number here must be sorted by descending number. In case of
1552 # a multiplatform kernel, we just want the highest value required by the
1553 # selected platforms.
1554 config ARCH_NR_GPIO
1555 int
1556 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1557 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1558 default 416 if ARCH_SUNXI
1559 default 392 if ARCH_U8500
1560 default 352 if ARCH_VT8500
1561 default 264 if MACH_H4700
1562 default 0
1563 help
1564 Maximum number of GPIOs in the system.
1566 If unsure, leave the default value.
1568 source kernel/Kconfig.preempt
1570 config HZ_FIXED
1571 int
1572 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1573 ARCH_S5PV210 || ARCH_EXYNOS4
1574 default AT91_TIMER_HZ if ARCH_AT91
1575 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1576 default 0
1578 choice
1579 depends on HZ_FIXED = 0
1580 prompt "Timer frequency"
1582 config HZ_100
1583 bool "100 Hz"
1585 config HZ_200
1586 bool "200 Hz"
1588 config HZ_250
1589 bool "250 Hz"
1591 config HZ_300
1592 bool "300 Hz"
1594 config HZ_500
1595 bool "500 Hz"
1597 config HZ_1000
1598 bool "1000 Hz"
1600 endchoice
1602 config HZ
1603 int
1604 default HZ_FIXED if HZ_FIXED != 0
1605 default 100 if HZ_100
1606 default 200 if HZ_200
1607 default 250 if HZ_250
1608 default 300 if HZ_300
1609 default 500 if HZ_500
1610 default 1000
1612 config SCHED_HRTICK
1613 def_bool HIGH_RES_TIMERS
1615 config THUMB2_KERNEL
1616 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1617 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1618 default y if CPU_THUMBONLY
1619 select AEABI
1620 select ARM_ASM_UNIFIED
1621 select ARM_UNWIND
1622 help
1623 By enabling this option, the kernel will be compiled in
1624 Thumb-2 mode. A compiler/assembler that understand the unified
1625 ARM-Thumb syntax is needed.
1627 If unsure, say N.
1629 config THUMB2_AVOID_R_ARM_THM_JUMP11
1630 bool "Work around buggy Thumb-2 short branch relocations in gas"
1631 depends on THUMB2_KERNEL && MODULES
1632 default y
1633 help
1634 Various binutils versions can resolve Thumb-2 branches to
1635 locally-defined, preemptible global symbols as short-range "b.n"
1636 branch instructions.
1638 This is a problem, because there's no guarantee the final
1639 destination of the symbol, or any candidate locations for a
1640 trampoline, are within range of the branch. For this reason, the
1641 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1642 relocation in modules at all, and it makes little sense to add
1643 support.
1645 The symptom is that the kernel fails with an "unsupported
1646 relocation" error when loading some modules.
1648 Until fixed tools are available, passing
1649 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1650 code which hits this problem, at the cost of a bit of extra runtime
1651 stack usage in some cases.
1653 The problem is described in more detail at:
1654 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1656 Only Thumb-2 kernels are affected.
1658 Unless you are sure your tools don't have this problem, say Y.
1660 config ARM_ASM_UNIFIED
1661 bool
1663 config AEABI
1664 bool "Use the ARM EABI to compile the kernel"
1665 help
1666 This option allows for the kernel to be compiled using the latest
1667 ARM ABI (aka EABI). This is only useful if you are using a user
1668 space environment that is also compiled with EABI.
1670 Since there are major incompatibilities between the legacy ABI and
1671 EABI, especially with regard to structure member alignment, this
1672 option also changes the kernel syscall calling convention to
1673 disambiguate both ABIs and allow for backward compatibility support
1674 (selected with CONFIG_OABI_COMPAT).
1676 To use this you need GCC version 4.0.0 or later.
1678 config OABI_COMPAT
1679 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1680 depends on AEABI && !THUMB2_KERNEL
1681 help
1682 This option preserves the old syscall interface along with the
1683 new (ARM EABI) one. It also provides a compatibility layer to
1684 intercept syscalls that have structure arguments which layout
1685 in memory differs between the legacy ABI and the new ARM EABI
1686 (only for non "thumb" binaries). This option adds a tiny
1687 overhead to all syscalls and produces a slightly larger kernel.
1689 The seccomp filter system will not be available when this is
1690 selected, since there is no way yet to sensibly distinguish
1691 between calling conventions during filtering.
1693 If you know you'll be using only pure EABI user space then you
1694 can say N here. If this option is not selected and you attempt
1695 to execute a legacy ABI binary then the result will be
1696 UNPREDICTABLE (in fact it can be predicted that it won't work
1697 at all). If in doubt say N.
1699 config ARCH_HAS_HOLES_MEMORYMODEL
1700 bool
1702 config ARCH_SPARSEMEM_ENABLE
1703 bool
1705 config ARCH_SPARSEMEM_DEFAULT
1706 def_bool ARCH_SPARSEMEM_ENABLE
1708 config ARCH_SELECT_MEMORY_MODEL
1709 def_bool ARCH_SPARSEMEM_ENABLE
1711 config HAVE_ARCH_PFN_VALID
1712 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1714 config HIGHMEM
1715 bool "High Memory Support"
1716 depends on MMU
1717 help
1718 The address space of ARM processors is only 4 Gigabytes large
1719 and it has to accommodate user address space, kernel address
1720 space as well as some memory mapped IO. That means that, if you
1721 have a large amount of physical memory and/or IO, not all of the
1722 memory can be "permanently mapped" by the kernel. The physical
1723 memory that is not permanently mapped is called "high memory".
1725 Depending on the selected kernel/user memory split, minimum
1726 vmalloc space and actual amount of RAM, you may not need this
1727 option which should result in a slightly faster kernel.
1729 If unsure, say n.
1731 config HIGHPTE
1732 bool "Allocate 2nd-level pagetables from highmem"
1733 depends on HIGHMEM
1735 config HW_PERF_EVENTS
1736 bool "Enable hardware performance counter support for perf events"
1737 depends on PERF_EVENTS
1738 default y
1739 help
1740 Enable hardware performance counter support for perf events. If
1741 disabled, perf events will use software events only.
1743 config SYS_SUPPORTS_HUGETLBFS
1744 def_bool y
1745 depends on ARM_LPAE
1747 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1748 def_bool y
1749 depends on ARM_LPAE
1751 config ARCH_WANT_GENERAL_HUGETLB
1752 def_bool y
1754 source "mm/Kconfig"
1756 config FORCE_MAX_ZONEORDER
1757 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1758 range 11 64 if ARCH_SHMOBILE_LEGACY
1759 default "12" if SOC_AM33XX
1760 default "9" if SA1111 || ARCH_EFM32
1761 default "11"
1762 help
1763 The kernel memory allocator divides physically contiguous memory
1764 blocks into "zones", where each zone is a power of two number of
1765 pages. This option selects the largest power of two that the kernel
1766 keeps in the memory allocator. If you need to allocate very large
1767 blocks of physically contiguous memory, then you may need to
1768 increase this value.
1770 This config option is actually maximum order plus one. For example,
1771 a value of 11 means that the largest free memory block is 2^10 pages.
1773 config ALIGNMENT_TRAP
1774 bool
1775 depends on CPU_CP15_MMU
1776 default y if !ARCH_EBSA110
1777 select HAVE_PROC_CPU if PROC_FS
1778 help
1779 ARM processors cannot fetch/store information which is not
1780 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1781 address divisible by 4. On 32-bit ARM processors, these non-aligned
1782 fetch/store instructions will be emulated in software if you say
1783 here, which has a severe performance impact. This is necessary for
1784 correct operation of some network protocols. With an IP-only
1785 configuration it is safe to say N, otherwise say Y.
1787 config UACCESS_WITH_MEMCPY
1788 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1789 depends on MMU
1790 default y if CPU_FEROCEON
1791 help
1792 Implement faster copy_to_user and clear_user methods for CPU
1793 cores where a 8-word STM instruction give significantly higher
1794 memory write throughput than a sequence of individual 32bit stores.
1796 A possible side effect is a slight increase in scheduling latency
1797 between threads sharing the same address space if they invoke
1798 such copy operations with large buffers.
1800 However, if the CPU data cache is using a write-allocate mode,
1801 this option is unlikely to provide any performance gain.
1803 config SECCOMP
1804 bool
1805 prompt "Enable seccomp to safely compute untrusted bytecode"
1806 ---help---
1807 This kernel feature is useful for number crunching applications
1808 that may need to compute untrusted bytecode during their
1809 execution. By using pipes or other transports made available to
1810 the process as file descriptors supporting the read/write
1811 syscalls, it's possible to isolate those applications in
1812 their own address space using seccomp. Once seccomp is
1813 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1814 and the task is only allowed to execute a few safe syscalls
1815 defined by each seccomp mode.
1817 config SWIOTLB
1818 def_bool y
1820 config IOMMU_HELPER
1821 def_bool SWIOTLB
1823 config XEN_DOM0
1824 def_bool y
1825 depends on XEN
1827 config XEN
1828 bool "Xen guest support on ARM (EXPERIMENTAL)"
1829 depends on ARM && AEABI && OF
1830 depends on CPU_V7 && !CPU_V6
1831 depends on !GENERIC_ATOMIC64
1832 depends on MMU
1833 select ARCH_DMA_ADDR_T_64BIT
1834 select ARM_PSCI
1835 select SWIOTLB_XEN
1836 help
1837 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1839 endmenu
1841 menu "Boot options"
1843 config USE_OF
1844 bool "Flattened Device Tree support"
1845 select IRQ_DOMAIN
1846 select OF
1847 select OF_EARLY_FLATTREE
1848 select OF_RESERVED_MEM
1849 help
1850 Include support for flattened device tree machine descriptions.
1852 config ATAGS
1853 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1854 default y
1855 help
1856 This is the traditional way of passing data to the kernel at boot
1857 time. If you are solely relying on the flattened device tree (or
1858 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1859 to remove ATAGS support from your kernel binary. If unsure,
1860 leave this to y.
1862 config DEPRECATED_PARAM_STRUCT
1863 bool "Provide old way to pass kernel parameters"
1864 depends on ATAGS
1865 help
1866 This was deprecated in 2001 and announced to live on for 5 years.
1867 Some old boot loaders still use this way.
1869 # Compressed boot loader in ROM. Yes, we really want to ask about
1870 # TEXT and BSS so we preserve their values in the config files.
1871 config ZBOOT_ROM_TEXT
1872 hex "Compressed ROM boot loader base address"
1873 default "0"
1874 help
1875 The physical address at which the ROM-able zImage is to be
1876 placed in the target. Platforms which normally make use of
1877 ROM-able zImage formats normally set this to a suitable
1878 value in their defconfig file.
1880 If ZBOOT_ROM is not enabled, this has no effect.
1882 config ZBOOT_ROM_BSS
1883 hex "Compressed ROM boot loader BSS address"
1884 default "0"
1885 help
1886 The base address of an area of read/write memory in the target
1887 for the ROM-able zImage which must be available while the
1888 decompressor is running. It must be large enough to hold the
1889 entire decompressed kernel plus an additional 128 KiB.
1890 Platforms which normally make use of ROM-able zImage formats
1891 normally set this to a suitable value in their defconfig file.
1893 If ZBOOT_ROM is not enabled, this has no effect.
1895 config ZBOOT_ROM
1896 bool "Compressed boot loader in ROM/flash"
1897 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1898 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1899 help
1900 Say Y here if you intend to execute your compressed kernel image
1901 (zImage) directly from ROM or flash. If unsure, say N.
1903 choice
1904 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1905 depends on ZBOOT_ROM && ARCH_SH7372
1906 default ZBOOT_ROM_NONE
1907 help
1908 Include experimental SD/MMC loading code in the ROM-able zImage.
1909 With this enabled it is possible to write the ROM-able zImage
1910 kernel image to an MMC or SD card and boot the kernel straight
1911 from the reset vector. At reset the processor Mask ROM will load
1912 the first part of the ROM-able zImage which in turn loads the
1913 rest the kernel image to RAM.
1915 config ZBOOT_ROM_NONE
1916 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1917 help
1918 Do not load image from SD or MMC
1920 config ZBOOT_ROM_MMCIF
1921 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1922 help
1923 Load image from MMCIF hardware block.
1925 config ZBOOT_ROM_SH_MOBILE_SDHI
1926 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1927 help
1928 Load image from SDHI hardware block
1930 endchoice
1932 config ARM_APPENDED_DTB
1933 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1934 depends on OF
1935 help
1936 With this option, the boot code will look for a device tree binary
1937 (DTB) appended to zImage
1938 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1940 This is meant as a backward compatibility convenience for those
1941 systems with a bootloader that can't be upgraded to accommodate
1942 the documented boot protocol using a device tree.
1944 Beware that there is very little in terms of protection against
1945 this option being confused by leftover garbage in memory that might
1946 look like a DTB header after a reboot if no actual DTB is appended
1947 to zImage. Do not leave this option active in a production kernel
1948 if you don't intend to always append a DTB. Proper passing of the
1949 location into r2 of a bootloader provided DTB is always preferable
1950 to this option.
1952 config ARM_ATAG_DTB_COMPAT
1953 bool "Supplement the appended DTB with traditional ATAG information"
1954 depends on ARM_APPENDED_DTB
1955 help
1956 Some old bootloaders can't be updated to a DTB capable one, yet
1957 they provide ATAGs with memory configuration, the ramdisk address,
1958 the kernel cmdline string, etc. Such information is dynamically
1959 provided by the bootloader and can't always be stored in a static
1960 DTB. To allow a device tree enabled kernel to be used with such
1961 bootloaders, this option allows zImage to extract the information
1962 from the ATAG list and store it at run time into the appended DTB.
1964 choice
1965 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1966 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1968 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1969 bool "Use bootloader kernel arguments if available"
1970 help
1971 Uses the command-line options passed by the boot loader instead of
1972 the device tree bootargs property. If the boot loader doesn't provide
1973 any, the device tree bootargs property will be used.
1975 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1976 bool "Extend with bootloader kernel arguments"
1977 help
1978 The command-line arguments provided by the boot loader will be
1979 appended to the the device tree bootargs property.
1981 endchoice
1983 config CMDLINE
1984 string "Default kernel command string"
1985 default ""
1986 help
1987 On some architectures (EBSA110 and CATS), there is currently no way
1988 for the boot loader to pass arguments to the kernel. For these
1989 architectures, you should supply some command-line options at build
1990 time by entering them here. As a minimum, you should specify the
1991 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1993 choice
1994 prompt "Kernel command line type" if CMDLINE != ""
1995 default CMDLINE_FROM_BOOTLOADER
1996 depends on ATAGS
1998 config CMDLINE_FROM_BOOTLOADER
1999 bool "Use bootloader kernel arguments if available"
2000 help
2001 Uses the command-line options passed by the boot loader. If
2002 the boot loader doesn't provide any, the default kernel command
2003 string provided in CMDLINE will be used.
2005 config CMDLINE_EXTEND
2006 bool "Extend bootloader kernel arguments"
2007 help
2008 The command-line arguments provided by the boot loader will be
2009 appended to the default kernel command string.
2011 config CMDLINE_FORCE
2012 bool "Always use the default kernel command string"
2013 help
2014 Always use the default kernel command string, even if the boot
2015 loader passes other arguments to the kernel.
2016 This is useful if you cannot or don't want to change the
2017 command-line options your boot loader passes to the kernel.
2018 endchoice
2020 config XIP_KERNEL
2021 bool "Kernel Execute-In-Place from ROM"
2022 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2023 help
2024 Execute-In-Place allows the kernel to run from non-volatile storage
2025 directly addressable by the CPU, such as NOR flash. This saves RAM
2026 space since the text section of the kernel is not loaded from flash
2027 to RAM. Read-write sections, such as the data section and stack,
2028 are still copied to RAM. The XIP kernel is not compressed since
2029 it has to run directly from flash, so it will take more space to
2030 store it. The flash address used to link the kernel object files,
2031 and for storing it, is configuration dependent. Therefore, if you
2032 say Y here, you must know the proper physical address where to
2033 store the kernel image depending on your own flash memory usage.
2035 Also note that the make target becomes "make xipImage" rather than
2036 "make zImage" or "make Image". The final kernel binary to put in
2037 ROM memory will be arch/arm/boot/xipImage.
2039 If unsure, say N.
2041 config XIP_PHYS_ADDR
2042 hex "XIP Kernel Physical Location"
2043 depends on XIP_KERNEL
2044 default "0x00080000"
2045 help
2046 This is the physical address in your flash memory the kernel will
2047 be linked for and stored to. This address is dependent on your
2048 own flash usage.
2050 config KEXEC
2051 bool "Kexec system call (EXPERIMENTAL)"
2052 depends on (!SMP || PM_SLEEP_SMP)
2053 help
2054 kexec is a system call that implements the ability to shutdown your
2055 current kernel, and to start another kernel. It is like a reboot
2056 but it is independent of the system firmware. And like a reboot
2057 you can start any kernel with it, not just Linux.
2059 It is an ongoing process to be certain the hardware in a machine
2060 is properly shutdown, so do not be surprised if this code does not
2061 initially work for you.
2063 config ATAGS_PROC
2064 bool "Export atags in procfs"
2065 depends on ATAGS && KEXEC
2066 default y
2067 help
2068 Should the atags used to boot the kernel be exported in an "atags"
2069 file in procfs. Useful with kexec.
2071 config CRASH_DUMP
2072 bool "Build kdump crash kernel (EXPERIMENTAL)"
2073 help
2074 Generate crash dump after being started by kexec. This should
2075 be normally only set in special crash dump kernels which are
2076 loaded in the main kernel with kexec-tools into a specially
2077 reserved region and then later executed after a crash by
2078 kdump/kexec. The crash dump kernel must be compiled to a
2079 memory address not used by the main kernel
2081 For more details see Documentation/kdump/kdump.txt
2083 config AUTO_ZRELADDR
2084 bool "Auto calculation of the decompressed kernel image address"
2085 help
2086 ZRELADDR is the physical address where the decompressed kernel
2087 image will be placed. If AUTO_ZRELADDR is selected, the address
2088 will be determined at run-time by masking the current IP with
2089 0xf8000000. This assumes the zImage being placed in the first 128MB
2090 from start of memory.
2092 endmenu
2094 menu "CPU Power Management"
2096 source "drivers/cpufreq/Kconfig"
2098 source "drivers/cpuidle/Kconfig"
2100 endmenu
2102 menu "Floating point emulation"
2104 comment "At least one emulation must be selected"
2106 config FPE_NWFPE
2107 bool "NWFPE math emulation"
2108 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2109 ---help---
2110 Say Y to include the NWFPE floating point emulator in the kernel.
2111 This is necessary to run most binaries. Linux does not currently
2112 support floating point hardware so you need to say Y here even if
2113 your machine has an FPA or floating point co-processor podule.
2115 You may say N here if you are going to load the Acorn FPEmulator
2116 early in the bootup.
2118 config FPE_NWFPE_XP
2119 bool "Support extended precision"
2120 depends on FPE_NWFPE
2121 help
2122 Say Y to include 80-bit support in the kernel floating-point
2123 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2124 Note that gcc does not generate 80-bit operations by default,
2125 so in most cases this option only enlarges the size of the
2126 floating point emulator without any good reason.
2128 You almost surely want to say N here.
2130 config FPE_FASTFPE
2131 bool "FastFPE math emulation (EXPERIMENTAL)"
2132 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2133 ---help---
2134 Say Y here to include the FAST floating point emulator in the kernel.
2135 This is an experimental much faster emulator which now also has full
2136 precision for the mantissa. It does not support any exceptions.
2137 It is very simple, and approximately 3-6 times faster than NWFPE.
2139 It should be sufficient for most programs. It may be not suitable
2140 for scientific calculations, but you have to check this for yourself.
2141 If you do not feel you need a faster FP emulation you should better
2142 choose NWFPE.
2144 config VFP
2145 bool "VFP-format floating point maths"
2146 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2147 help
2148 Say Y to include VFP support code in the kernel. This is needed
2149 if your hardware includes a VFP unit.
2151 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2152 release notes and additional status information.
2154 Say N if your target does not have VFP hardware.
2156 config VFPv3
2157 bool
2158 depends on VFP
2159 default y if CPU_V7
2161 config NEON
2162 bool "Advanced SIMD (NEON) Extension support"
2163 depends on VFPv3 && CPU_V7
2164 help
2165 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2166 Extension.
2168 config KERNEL_MODE_NEON
2169 bool "Support for NEON in kernel mode"
2170 depends on NEON && AEABI
2171 help
2172 Say Y to include support for NEON in kernel mode.
2174 endmenu
2176 menu "Userspace binary formats"
2178 source "fs/Kconfig.binfmt"
2180 config ARTHUR
2181 tristate "RISC OS personality"
2182 depends on !AEABI
2183 help
2184 Say Y here to include the kernel code necessary if you want to run
2185 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2186 experimental; if this sounds frightening, say N and sleep in peace.
2187 You can also say M here to compile this support as a module (which
2188 will be called arthur).
2190 endmenu
2192 menu "Power management options"
2194 source "kernel/power/Kconfig"
2196 config ARCH_SUSPEND_POSSIBLE
2197 depends on !ARCH_S5PC100
2198 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2199 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2200 def_bool y
2202 config ARM_CPU_SUSPEND
2203 def_bool PM_SLEEP
2205 config ARCH_HIBERNATION_POSSIBLE
2206 bool
2207 depends on MMU
2208 default y if ARCH_SUSPEND_POSSIBLE
2210 endmenu
2212 source "net/Kconfig"
2214 source "drivers/Kconfig"
2216 source "fs/Kconfig"
2218 source "arch/arm/Kconfig.debug"
2220 source "security/Kconfig"
2222 source "crypto/Kconfig"
2224 source "lib/Kconfig"
2226 source "arch/arm/kvm/Kconfig"