| blob | 834fb5a5306f297ffde587ef58248d61c9d60f08 |
1 /*
2 * SAMSUNG EXYNOS5250 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
20 #include <dt-bindings/clock/exynos5250.h>
21 #include "exynos5.dtsi"
22 #include "exynos5250-pinctrl.dtsi"
24 #include <dt-bindings/clock/exynos-audss-clk.h>
26 / {
27 compatible = "samsung,exynos5250", "samsung,exynos5";
29 aliases {
30 spi0 = &spi_0;
31 spi1 = &spi_1;
32 spi2 = &spi_2;
33 gsc0 = &gsc_0;
34 gsc1 = &gsc_1;
35 gsc2 = &gsc_2;
36 gsc3 = &gsc_3;
37 mshc0 = &mmc_0;
38 mshc1 = &mmc_1;
39 mshc2 = &mmc_2;
40 mshc3 = &mmc_3;
41 i2c0 = &i2c_0;
42 i2c1 = &i2c_1;
43 i2c2 = &i2c_2;
44 i2c3 = &i2c_3;
45 i2c4 = &i2c_4;
46 i2c5 = &i2c_5;
47 i2c6 = &i2c_6;
48 i2c7 = &i2c_7;
49 i2c8 = &i2c_8;
50 i2c9 = &i2c_9;
51 pinctrl0 = &pinctrl_0;
52 pinctrl1 = &pinctrl_1;
53 pinctrl2 = &pinctrl_2;
54 pinctrl3 = &pinctrl_3;
55 };
57 cpus {
58 #address-cells = <1>;
59 #size-cells = <0>;
61 cpu@0 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a15";
64 reg = <0>;
65 clock-frequency = <1700000000>;
66 };
67 cpu@1 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a15";
70 reg = <1>;
71 clock-frequency = <1700000000>;
72 };
73 };
75 sysram@02020000 {
76 compatible = "mmio-sram";
77 reg = <0x02020000 0x30000>;
78 #address-cells = <1>;
79 #size-cells = <1>;
80 ranges = <0 0x02020000 0x30000>;
82 smp-sysram@0 {
83 compatible = "samsung,exynos4210-sysram";
84 reg = <0x0 0x1000>;
85 };
87 smp-sysram@2f000 {
88 compatible = "samsung,exynos4210-sysram-ns";
89 reg = <0x2f000 0x1000>;
90 };
91 };
93 pd_gsc: gsc-power-domain@10044000 {
94 compatible = "samsung,exynos4210-pd";
95 reg = <0x10044000 0x20>;
96 };
98 pd_mfc: mfc-power-domain@10044040 {
99 compatible = "samsung,exynos4210-pd";
100 reg = <0x10044040 0x20>;
101 };
103 clock: clock-controller@10010000 {
104 compatible = "samsung,exynos5250-clock";
105 reg = <0x10010000 0x30000>;
106 #clock-cells = <1>;
107 };
109 clock_audss: audss-clock-controller@3810000 {
110 compatible = "samsung,exynos5250-audss-clock";
111 reg = <0x03810000 0x0C>;
112 #clock-cells = <1>;
113 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
114 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
115 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
116 };
118 timer {
119 compatible = "arm,armv7-timer";
120 interrupts = <1 13 0xf08>,
121 <1 14 0xf08>,
122 <1 11 0xf08>,
123 <1 10 0xf08>;
124 /* Unfortunately we need this since some versions of U-Boot
125 * on Exynos don't set the CNTFRQ register, so we need the
126 * value from DT.
127 */
128 clock-frequency = <24000000>;
129 };
131 mct@101C0000 {
132 compatible = "samsung,exynos4210-mct";
133 reg = <0x101C0000 0x800>;
134 interrupt-controller;
135 #interrups-cells = <2>;
136 interrupt-parent = <&mct_map>;
137 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
138 <4 0>, <5 0>;
139 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
140 clock-names = "fin_pll", "mct";
142 mct_map: mct-map {
143 #interrupt-cells = <2>;
144 #address-cells = <0>;
145 #size-cells = <0>;
146 interrupt-map = <0x0 0 &combiner 23 3>,
147 <0x1 0 &combiner 23 4>,
148 <0x2 0 &combiner 25 2>,
149 <0x3 0 &combiner 25 3>,
150 <0x4 0 &gic 0 120 0>,
151 <0x5 0 &gic 0 121 0>;
152 };
153 };
155 pmu {
156 compatible = "arm,cortex-a15-pmu";
157 interrupt-parent = <&combiner>;
158 interrupts = <1 2>, <22 4>;
159 };
161 pinctrl_0: pinctrl@11400000 {
162 compatible = "samsung,exynos5250-pinctrl";
163 reg = <0x11400000 0x1000>;
164 interrupts = <0 46 0>;
166 wakup_eint: wakeup-interrupt-controller {
167 compatible = "samsung,exynos4210-wakeup-eint";
168 interrupt-parent = <&gic>;
169 interrupts = <0 32 0>;
170 };
171 };
173 pinctrl_1: pinctrl@13400000 {
174 compatible = "samsung,exynos5250-pinctrl";
175 reg = <0x13400000 0x1000>;
176 interrupts = <0 45 0>;
177 };
179 pinctrl_2: pinctrl@10d10000 {
180 compatible = "samsung,exynos5250-pinctrl";
181 reg = <0x10d10000 0x1000>;
182 interrupts = <0 50 0>;
183 };
185 pinctrl_3: pinctrl@03860000 {
186 compatible = "samsung,exynos5250-pinctrl";
187 reg = <0x03860000 0x1000>;
188 interrupts = <0 47 0>;
189 };
191 pmu_system_controller: system-controller@10040000 {
192 compatible = "samsung,exynos5250-pmu", "syscon";
193 reg = <0x10040000 0x5000>;
194 };
196 sysreg_system_controller: syscon@10050000 {
197 compatible = "samsung,exynos5-sysreg", "syscon";
198 reg = <0x10050000 0x5000>;
199 };
201 watchdog@101D0000 {
202 compatible = "samsung,exynos5250-wdt";
203 reg = <0x101D0000 0x100>;
204 interrupts = <0 42 0>;
205 clocks = <&clock CLK_WDT>;
206 clock-names = "watchdog";
207 samsung,syscon-phandle = <&pmu_system_controller>;
208 };
210 g2d@10850000 {
211 compatible = "samsung,exynos5250-g2d";
212 reg = <0x10850000 0x1000>;
213 interrupts = <0 91 0>;
214 clocks = <&clock CLK_G2D>;
215 clock-names = "fimg2d";
216 };
218 codec@11000000 {
219 compatible = "samsung,mfc-v6";
220 reg = <0x11000000 0x10000>;
221 interrupts = <0 96 0>;
222 samsung,power-domain = <&pd_mfc>;
223 clocks = <&clock CLK_MFC>;
224 clock-names = "mfc";
225 };
227 rtc@101E0000 {
228 clocks = <&clock CLK_RTC>;
229 clock-names = "rtc";
230 status = "disabled";
231 };
233 tmu@10060000 {
234 compatible = "samsung,exynos5250-tmu";
235 reg = <0x10060000 0x100>;
236 interrupts = <0 65 0>;
237 clocks = <&clock CLK_TMU>;
238 clock-names = "tmu_apbif";
239 };
241 serial@12C00000 {
242 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
243 clock-names = "uart", "clk_uart_baud0";
244 };
246 serial@12C10000 {
247 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
248 clock-names = "uart", "clk_uart_baud0";
249 };
251 serial@12C20000 {
252 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
253 clock-names = "uart", "clk_uart_baud0";
254 };
256 serial@12C30000 {
257 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
258 clock-names = "uart", "clk_uart_baud0";
259 };
261 sata@122F0000 {
262 compatible = "snps,dwc-ahci";
263 samsung,sata-freq = <66>;
264 reg = <0x122F0000 0x1ff>;
265 interrupts = <0 115 0>;
266 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
267 clock-names = "sata", "sclk_sata";
268 phys = <&sata_phy>;
269 phy-names = "sata-phy";
270 status = "disabled";
271 };
273 sata_phy: sata-phy@12170000 {
274 compatible = "samsung,exynos5250-sata-phy";
275 reg = <0x12170000 0x1ff>;
276 clocks = <&clock CLK_SATA_PHYCTRL>;
277 clock-names = "sata_phyctrl";
278 #phy-cells = <0>;
279 samsung,syscon-phandle = <&pmu_system_controller>;
280 status = "disabled";
281 };
283 i2c_0: i2c@12C60000 {
284 compatible = "samsung,s3c2440-i2c";
285 reg = <0x12C60000 0x100>;
286 interrupts = <0 56 0>;
287 #address-cells = <1>;
288 #size-cells = <0>;
289 clocks = <&clock CLK_I2C0>;
290 clock-names = "i2c";
291 pinctrl-names = "default";
292 pinctrl-0 = <&i2c0_bus>;
293 status = "disabled";
294 };
296 i2c_1: i2c@12C70000 {
297 compatible = "samsung,s3c2440-i2c";
298 reg = <0x12C70000 0x100>;
299 interrupts = <0 57 0>;
300 #address-cells = <1>;
301 #size-cells = <0>;
302 clocks = <&clock CLK_I2C1>;
303 clock-names = "i2c";
304 pinctrl-names = "default";
305 pinctrl-0 = <&i2c1_bus>;
306 status = "disabled";
307 };
309 i2c_2: i2c@12C80000 {
310 compatible = "samsung,s3c2440-i2c";
311 reg = <0x12C80000 0x100>;
312 interrupts = <0 58 0>;
313 #address-cells = <1>;
314 #size-cells = <0>;
315 clocks = <&clock CLK_I2C2>;
316 clock-names = "i2c";
317 pinctrl-names = "default";
318 pinctrl-0 = <&i2c2_bus>;
319 status = "disabled";
320 };
322 i2c_3: i2c@12C90000 {
323 compatible = "samsung,s3c2440-i2c";
324 reg = <0x12C90000 0x100>;
325 interrupts = <0 59 0>;
326 #address-cells = <1>;
327 #size-cells = <0>;
328 clocks = <&clock CLK_I2C3>;
329 clock-names = "i2c";
330 pinctrl-names = "default";
331 pinctrl-0 = <&i2c3_bus>;
332 status = "disabled";
333 };
335 i2c_4: i2c@12CA0000 {
336 compatible = "samsung,s3c2440-i2c";
337 reg = <0x12CA0000 0x100>;
338 interrupts = <0 60 0>;
339 #address-cells = <1>;
340 #size-cells = <0>;
341 clocks = <&clock CLK_I2C4>;
342 clock-names = "i2c";
343 pinctrl-names = "default";
344 pinctrl-0 = <&i2c4_bus>;
345 status = "disabled";
346 };
348 i2c_5: i2c@12CB0000 {
349 compatible = "samsung,s3c2440-i2c";
350 reg = <0x12CB0000 0x100>;
351 interrupts = <0 61 0>;
352 #address-cells = <1>;
353 #size-cells = <0>;
354 clocks = <&clock CLK_I2C5>;
355 clock-names = "i2c";
356 pinctrl-names = "default";
357 pinctrl-0 = <&i2c5_bus>;
358 status = "disabled";
359 };
361 i2c_6: i2c@12CC0000 {
362 compatible = "samsung,s3c2440-i2c";
363 reg = <0x12CC0000 0x100>;
364 interrupts = <0 62 0>;
365 #address-cells = <1>;
366 #size-cells = <0>;
367 clocks = <&clock CLK_I2C6>;
368 clock-names = "i2c";
369 pinctrl-names = "default";
370 pinctrl-0 = <&i2c6_bus>;
371 status = "disabled";
372 };
374 i2c_7: i2c@12CD0000 {
375 compatible = "samsung,s3c2440-i2c";
376 reg = <0x12CD0000 0x100>;
377 interrupts = <0 63 0>;
378 #address-cells = <1>;
379 #size-cells = <0>;
380 clocks = <&clock CLK_I2C7>;
381 clock-names = "i2c";
382 pinctrl-names = "default";
383 pinctrl-0 = <&i2c7_bus>;
384 status = "disabled";
385 };
387 i2c_8: i2c@12CE0000 {
388 compatible = "samsung,s3c2440-hdmiphy-i2c";
389 reg = <0x12CE0000 0x1000>;
390 interrupts = <0 64 0>;
391 #address-cells = <1>;
392 #size-cells = <0>;
393 clocks = <&clock CLK_I2C_HDMI>;
394 clock-names = "i2c";
395 status = "disabled";
396 };
398 i2c_9: i2c@121D0000 {
399 compatible = "samsung,exynos5-sata-phy-i2c";
400 reg = <0x121D0000 0x100>;
401 #address-cells = <1>;
402 #size-cells = <0>;
403 clocks = <&clock CLK_SATA_PHYI2C>;
404 clock-names = "i2c";
405 status = "disabled";
406 };
408 spi_0: spi@12d20000 {
409 compatible = "samsung,exynos4210-spi";
410 status = "disabled";
411 reg = <0x12d20000 0x100>;
412 interrupts = <0 66 0>;
413 dmas = <&pdma0 5
414 &pdma0 4>;
415 dma-names = "tx", "rx";
416 #address-cells = <1>;
417 #size-cells = <0>;
418 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
419 clock-names = "spi", "spi_busclk0";
420 pinctrl-names = "default";
421 pinctrl-0 = <&spi0_bus>;
422 };
424 spi_1: spi@12d30000 {
425 compatible = "samsung,exynos4210-spi";
426 status = "disabled";
427 reg = <0x12d30000 0x100>;
428 interrupts = <0 67 0>;
429 dmas = <&pdma1 5
430 &pdma1 4>;
431 dma-names = "tx", "rx";
432 #address-cells = <1>;
433 #size-cells = <0>;
434 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
435 clock-names = "spi", "spi_busclk0";
436 pinctrl-names = "default";
437 pinctrl-0 = <&spi1_bus>;
438 };
440 spi_2: spi@12d40000 {
441 compatible = "samsung,exynos4210-spi";
442 status = "disabled";
443 reg = <0x12d40000 0x100>;
444 interrupts = <0 68 0>;
445 dmas = <&pdma0 7
446 &pdma0 6>;
447 dma-names = "tx", "rx";
448 #address-cells = <1>;
449 #size-cells = <0>;
450 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
451 clock-names = "spi", "spi_busclk0";
452 pinctrl-names = "default";
453 pinctrl-0 = <&spi2_bus>;
454 };
456 mmc_0: mmc@12200000 {
457 compatible = "samsung,exynos5250-dw-mshc";
458 interrupts = <0 75 0>;
459 #address-cells = <1>;
460 #size-cells = <0>;
461 reg = <0x12200000 0x1000>;
462 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
463 clock-names = "biu", "ciu";
464 fifo-depth = <0x80>;
465 status = "disabled";
466 };
468 mmc_1: mmc@12210000 {
469 compatible = "samsung,exynos5250-dw-mshc";
470 interrupts = <0 76 0>;
471 #address-cells = <1>;
472 #size-cells = <0>;
473 reg = <0x12210000 0x1000>;
474 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
475 clock-names = "biu", "ciu";
476 fifo-depth = <0x80>;
477 status = "disabled";
478 };
480 mmc_2: mmc@12220000 {
481 compatible = "samsung,exynos5250-dw-mshc";
482 interrupts = <0 77 0>;
483 #address-cells = <1>;
484 #size-cells = <0>;
485 reg = <0x12220000 0x1000>;
486 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
487 clock-names = "biu", "ciu";
488 fifo-depth = <0x80>;
489 status = "disabled";
490 };
492 mmc_3: mmc@12230000 {
493 compatible = "samsung,exynos5250-dw-mshc";
494 reg = <0x12230000 0x1000>;
495 interrupts = <0 78 0>;
496 #address-cells = <1>;
497 #size-cells = <0>;
498 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
499 clock-names = "biu", "ciu";
500 fifo-depth = <0x80>;
501 status = "disabled";
502 };
504 i2s0: i2s@03830000 {
505 compatible = "samsung,s5pv210-i2s";
506 status = "disabled";
507 reg = <0x03830000 0x100>;
508 dmas = <&pdma0 10
509 &pdma0 9
510 &pdma0 8>;
511 dma-names = "tx", "rx", "tx-sec";
512 clocks = <&clock_audss EXYNOS_I2S_BUS>,
513 <&clock_audss EXYNOS_I2S_BUS>,
514 <&clock_audss EXYNOS_SCLK_I2S>;
515 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
516 samsung,idma-addr = <0x03000000>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&i2s0_bus>;
519 };
521 i2s1: i2s@12D60000 {
522 compatible = "samsung,s3c6410-i2s";
523 status = "disabled";
524 reg = <0x12D60000 0x100>;
525 dmas = <&pdma1 12
526 &pdma1 11>;
527 dma-names = "tx", "rx";
528 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
529 clock-names = "iis", "i2s_opclk0";
530 pinctrl-names = "default";
531 pinctrl-0 = <&i2s1_bus>;
532 };
534 i2s2: i2s@12D70000 {
535 compatible = "samsung,s3c6410-i2s";
536 status = "disabled";
537 reg = <0x12D70000 0x100>;
538 dmas = <&pdma0 12
539 &pdma0 11>;
540 dma-names = "tx", "rx";
541 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
542 clock-names = "iis", "i2s_opclk0";
543 pinctrl-names = "default";
544 pinctrl-0 = <&i2s2_bus>;
545 };
547 usb@12000000 {
548 compatible = "samsung,exynos5250-dwusb3";
549 clocks = <&clock CLK_USB3>;
550 clock-names = "usbdrd30";
551 #address-cells = <1>;
552 #size-cells = <1>;
553 ranges;
555 dwc3 {
556 compatible = "synopsys,dwc3";
557 reg = <0x12000000 0x10000>;
558 interrupts = <0 72 0>;
559 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
560 phy-names = "usb2-phy", "usb3-phy";
561 };
562 };
564 usbdrd_phy: phy@12100000 {
565 compatible = "samsung,exynos5250-usbdrd-phy";
566 reg = <0x12100000 0x100>;
567 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
568 clock-names = "phy", "ref";
569 samsung,pmu-syscon = <&pmu_system_controller>;
570 #phy-cells = <1>;
571 };
573 usb@12110000 {
574 compatible = "samsung,exynos4210-ehci";
575 reg = <0x12110000 0x100>;
576 interrupts = <0 71 0>;
578 clocks = <&clock CLK_USB2>;
579 clock-names = "usbhost";
580 #address-cells = <1>;
581 #size-cells = <0>;
582 port@0 {
583 reg = <0>;
584 phys = <&usb2_phy_gen 1>;
585 };
586 };
588 usb@12120000 {
589 compatible = "samsung,exynos4210-ohci";
590 reg = <0x12120000 0x100>;
591 interrupts = <0 71 0>;
593 clocks = <&clock CLK_USB2>;
594 clock-names = "usbhost";
595 #address-cells = <1>;
596 #size-cells = <0>;
597 port@0 {
598 reg = <0>;
599 phys = <&usb2_phy_gen 1>;
600 };
601 };
603 usb2_phy: usbphy@12130000 {
604 compatible = "samsung,exynos5250-usb2phy";
605 reg = <0x12130000 0x100>;
606 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>;
607 clock-names = "ext_xtal", "usbhost";
608 #address-cells = <1>;
609 #size-cells = <1>;
610 ranges;
612 usbphy-sys {
613 reg = <0x10040704 0x8>,
614 <0x10050230 0x4>;
615 };
616 };
618 usb2_phy_gen: phy@12130000 {
619 compatible = "samsung,exynos5250-usb2-phy";
620 reg = <0x12130000 0x100>;
621 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
622 clock-names = "phy", "ref";
623 #phy-cells = <1>;
624 samsung,sysreg-phandle = <&sysreg_system_controller>;
625 samsung,pmureg-phandle = <&pmu_system_controller>;
626 };
628 pwm: pwm@12dd0000 {
629 compatible = "samsung,exynos4210-pwm";
630 reg = <0x12dd0000 0x100>;
631 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
632 #pwm-cells = <3>;
633 clocks = <&clock CLK_PWM>;
634 clock-names = "timers";
635 };
637 amba {
638 #address-cells = <1>;
639 #size-cells = <1>;
640 compatible = "arm,amba-bus";
641 interrupt-parent = <&gic>;
642 ranges;
644 pdma0: pdma@121A0000 {
645 compatible = "arm,pl330", "arm,primecell";
646 reg = <0x121A0000 0x1000>;
647 interrupts = <0 34 0>;
648 clocks = <&clock CLK_PDMA0>;
649 clock-names = "apb_pclk";
650 #dma-cells = <1>;
651 #dma-channels = <8>;
652 #dma-requests = <32>;
653 };
655 pdma1: pdma@121B0000 {
656 compatible = "arm,pl330", "arm,primecell";
657 reg = <0x121B0000 0x1000>;
658 interrupts = <0 35 0>;
659 clocks = <&clock CLK_PDMA1>;
660 clock-names = "apb_pclk";
661 #dma-cells = <1>;
662 #dma-channels = <8>;
663 #dma-requests = <32>;
664 };
666 mdma0: mdma@10800000 {
667 compatible = "arm,pl330", "arm,primecell";
668 reg = <0x10800000 0x1000>;
669 interrupts = <0 33 0>;
670 clocks = <&clock CLK_MDMA0>;
671 clock-names = "apb_pclk";
672 #dma-cells = <1>;
673 #dma-channels = <8>;
674 #dma-requests = <1>;
675 };
677 mdma1: mdma@11C10000 {
678 compatible = "arm,pl330", "arm,primecell";
679 reg = <0x11C10000 0x1000>;
680 interrupts = <0 124 0>;
681 clocks = <&clock CLK_MDMA1>;
682 clock-names = "apb_pclk";
683 #dma-cells = <1>;
684 #dma-channels = <8>;
685 #dma-requests = <1>;
686 };
687 };
689 gsc_0: gsc@13e00000 {
690 compatible = "samsung,exynos5-gsc";
691 reg = <0x13e00000 0x1000>;
692 interrupts = <0 85 0>;
693 samsung,power-domain = <&pd_gsc>;
694 clocks = <&clock CLK_GSCL0>;
695 clock-names = "gscl";
696 };
698 gsc_1: gsc@13e10000 {
699 compatible = "samsung,exynos5-gsc";
700 reg = <0x13e10000 0x1000>;
701 interrupts = <0 86 0>;
702 samsung,power-domain = <&pd_gsc>;
703 clocks = <&clock CLK_GSCL1>;
704 clock-names = "gscl";
705 };
707 gsc_2: gsc@13e20000 {
708 compatible = "samsung,exynos5-gsc";
709 reg = <0x13e20000 0x1000>;
710 interrupts = <0 87 0>;
711 samsung,power-domain = <&pd_gsc>;
712 clocks = <&clock CLK_GSCL2>;
713 clock-names = "gscl";
714 };
716 gsc_3: gsc@13e30000 {
717 compatible = "samsung,exynos5-gsc";
718 reg = <0x13e30000 0x1000>;
719 interrupts = <0 88 0>;
720 samsung,power-domain = <&pd_gsc>;
721 clocks = <&clock CLK_GSCL3>;
722 clock-names = "gscl";
723 };
725 hdmi {
726 compatible = "samsung,exynos4212-hdmi";
727 reg = <0x14530000 0x70000>;
728 interrupts = <0 95 0>;
729 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
730 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
731 <&clock CLK_MOUT_HDMI>;
732 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
733 "sclk_hdmiphy", "mout_hdmi";
734 samsung,syscon-phandle = <&pmu_system_controller>;
735 };
737 mixer {
738 compatible = "samsung,exynos5250-mixer";
739 reg = <0x14450000 0x10000>;
740 interrupts = <0 94 0>;
741 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
742 clock-names = "mixer", "sclk_hdmi";
743 };
745 dp_phy: video-phy@10040720 {
746 compatible = "samsung,exynos5250-dp-video-phy";
747 reg = <0x10040720 4>;
748 #phy-cells = <0>;
749 };
751 dp-controller@145B0000 {
752 clocks = <&clock CLK_DP>;
753 clock-names = "dp";
754 phys = <&dp_phy>;
755 phy-names = "dp";
756 };
758 fimd@14400000 {
759 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
760 clock-names = "sclk_fimd", "fimd";
761 };
763 adc: adc@12D10000 {
764 compatible = "samsung,exynos-adc-v1";
765 reg = <0x12D10000 0x100>, <0x10040718 0x4>;
766 interrupts = <0 106 0>;
767 clocks = <&clock CLK_ADC>;
768 clock-names = "adc";
769 #io-channel-cells = <1>;
770 io-channel-ranges;
771 status = "disabled";
772 };
774 sss@10830000 {
775 compatible = "samsung,exynos4210-secss";
776 reg = <0x10830000 0x10000>;
777 interrupts = <0 112 0>;
778 clocks = <&clock CLK_SSS>;
779 clock-names = "secss";
780 };
781 };