arch/arm/boot/dts/prima2.dtsi

   1 /*
   2  * DTS file for CSR SiRFprimaII SoC
   3  *
   4  * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10 / {
  11         compatible = "sirf,prima2";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         interrupt-parent = <&intc>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         compatible = "arm,cortex-a9";
  22                         device_type = "cpu";
  23                         reg = <0x0>;
  24                         d-cache-line-size = <32>;
  25                         i-cache-line-size = <32>;
  26                         d-cache-size = <32768>;
  27                         i-cache-size = <32768>;
  28                         /* from bootloader */
  29                         timebase-frequency = <0>;
  30                         bus-frequency = <0>;
  31                         clock-frequency = <0>;
  32                         clocks = <&clks 12>;
  33                         operating-points = <
  34                                 /* kHz    uV */
  35                                 200000  1025000
  36                                 400000  1025000
  37                                 664000  1050000
  38                                 800000  1100000
  39                         >;
  40                         clock-latency = <150000>;
  41                 };
  42         };
  43
  44         axi {
  45                 compatible = "simple-bus";
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 ranges = <0x40000000 0x40000000 0x80000000>;
  49
  50                 l2-cache-controller@80040000 {
  51                         compatible = "arm,pl310-cache";
  52                         reg = <0x80040000 0x1000>;
  53                         interrupts = <59>;
  54                         arm,tag-latency = <1 1 1>;
  55                         arm,data-latency = <1 1 1>;
  56                         arm,filter-ranges = <0 0x40000000>;
  57                 };
  58
  59                 intc: interrupt-controller@80020000 {
  60                         #interrupt-cells = <1>;
  61                         interrupt-controller;
  62                         compatible = "sirf,prima2-intc";
  63                         reg = <0x80020000 0x1000>;
  64                 };
  65
  66                 sys-iobg {
  67                         compatible = "simple-bus";
  68                         #address-cells = <1>;
  69                         #size-cells = <1>;
  70                         ranges = <0x88000000 0x88000000 0x40000>;
  71
  72                         clks: clock-controller@88000000 {
  73                                 compatible = "sirf,prima2-clkc";
  74                                 reg = <0x88000000 0x1000>;
  75                                 interrupts = <3>;
  76                                 #clock-cells = <1>;
  77                         };
  78
  79                         rstc: reset-controller@88010000 {
  80                                 compatible = "sirf,prima2-rstc";
  81                                 reg = <0x88010000 0x1000>;
  82                                 #reset-cells = <1>;
  83                         };
  84
  85                         rsc-controller@88020000 {
  86                                 compatible = "sirf,prima2-rsc";
  87                                 reg = <0x88020000 0x1000>;
  88                         };
  89
  90                         cphifbg@88030000 {
  91                                 compatible = "sirf,prima2-cphifbg";
  92                                 reg = <0x88030000 0x1000>;
  93                                 clocks = <&clks 42>;
  94                         };
  95                 };
  96
  97                 mem-iobg {
  98                         compatible = "simple-bus";
  99                         #address-cells = <1>;
 100                         #size-cells = <1>;
 101                         ranges = <0x90000000 0x90000000 0x10000>;
 102
 103                         memory-controller@90000000 {
 104                                 compatible = "sirf,prima2-memc";
 105                                 reg = <0x90000000 0x2000>;
 106                                 interrupts = <27>;
 107                                 clocks = <&clks 5>;
 108                         };
 109
 110                         memc-monitor {
 111                                 compatible = "sirf,prima2-memcmon";
 112                                 reg = <0x90002000 0x200>;
 113                                 interrupts = <4>;
 114                                 clocks = <&clks 32>;
 115                         };
 116                 };
 117
 118                 disp-iobg {
 119                         compatible = "simple-bus";
 120                         #address-cells = <1>;
 121                         #size-cells = <1>;
 122                         ranges = <0x90010000 0x90010000 0x30000>;
 123
 124                         display@90010000 {
 125                                 compatible = "sirf,prima2-lcd";
 126                                 reg = <0x90010000 0x20000>;
 127                                 interrupts = <30>;
 128                         };
 129
 130                         vpp@90020000 {
 131                                 compatible = "sirf,prima2-vpp";
 132                                 reg = <0x90020000 0x10000>;
 133                                 interrupts = <31>;
 134                                 clocks = <&clks 35>;
 135                         };
 136                 };
 137
 138                 graphics-iobg {
 139                         compatible = "simple-bus";
 140                         #address-cells = <1>;
 141                         #size-cells = <1>;
 142                         ranges = <0x98000000 0x98000000 0x8000000>;
 143
 144                         graphics@98000000 {
 145                                 compatible = "powervr,sgx531";
 146                                 reg = <0x98000000 0x8000000>;
 147                                 interrupts = <6>;
 148                                 clocks = <&clks 32>;
 149                         };
 150                 };
 151
 152                 multimedia-iobg {
 153                         compatible = "simple-bus";
 154                         #address-cells = <1>;
 155                         #size-cells = <1>;
 156                         ranges = <0xa0000000 0xa0000000 0x8000000>;
 157
 158                         multimedia@a0000000 {
 159                                 compatible = "sirf,prima2-video-codec";
 160                                 reg = <0xa0000000 0x8000000>;
 161                                 interrupts = <5>;
 162                                 clocks = <&clks 33>;
 163                         };
 164                 };
 165
 166                 dsp-iobg {
 167                         compatible = "simple-bus";
 168                         #address-cells = <1>;
 169                         #size-cells = <1>;
 170                         ranges = <0xa8000000 0xa8000000 0x2000000>;
 171
 172                         dspif@a8000000 {
 173                                 compatible = "sirf,prima2-dspif";
 174                                 reg = <0xa8000000 0x10000>;
 175                                 interrupts = <9>;
 176                         };
 177
 178                         gps@a8010000 {
 179                                 compatible = "sirf,prima2-gps";
 180                                 reg = <0xa8010000 0x10000>;
 181                                 interrupts = <7>;
 182                                 clocks = <&clks 9>;
 183                         };
 184
 185                         dsp@a9000000 {
 186                                 compatible = "sirf,prima2-dsp";
 187                                 reg = <0xa9000000 0x1000000>;
 188                                 interrupts = <8>;
 189                                 clocks = <&clks 8>;
 190                         };
 191                 };
 192
 193                 peri-iobg {
 194                         compatible = "simple-bus";
 195                         #address-cells = <1>;
 196                         #size-cells = <1>;
 197                         ranges = <0xb0000000 0xb0000000 0x180000>,
 198                                <0x56000000 0x56000000 0x1b00000>;
 199
 200                         timer@b0020000 {
 201                                 compatible = "sirf,prima2-tick";
 202                                 reg = <0xb0020000 0x1000>;
 203                                 interrupts = <0>;
 204                                 clocks = <&clks 11>;
 205                         };
 206
 207                         nand@b0030000 {
 208                                 compatible = "sirf,prima2-nand";
 209                                 reg = <0xb0030000 0x10000>;
 210                                 interrupts = <41>;
 211                                 clocks = <&clks 26>;
 212                         };
 213
 214                         audio@b0040000 {
 215                                 compatible = "sirf,prima2-audio";
 216                                 reg = <0xb0040000 0x10000>;
 217                                 interrupts = <35>;
 218                                 clocks = <&clks 27>;
 219                         };
 220
 221                         uart0: uart@b0050000 {
 222                                 cell-index = <0>;
 223                                 compatible = "sirf,prima2-uart";
 224                                 reg = <0xb0050000 0x1000>;
 225                                 interrupts = <17>;
 226                                 fifosize = <128>;
 227                                 clocks = <&clks 13>;
 228                                 dmas = <&dmac1 5>, <&dmac0 2>;
 229                                 dma-names = "rx", "tx";
 230                         };
 231
 232                         uart1: uart@b0060000 {
 233                                 cell-index = <1>;
 234                                 compatible = "sirf,prima2-uart";
 235                                 reg = <0xb0060000 0x1000>;
 236                                 interrupts = <18>;
 237                                 fifosize = <32>;
 238                                 clocks = <&clks 14>;
 239                         };
 240
 241                         uart2: uart@b0070000 {
 242                                 cell-index = <2>;
 243                                 compatible = "sirf,prima2-uart";
 244                                 reg = <0xb0070000 0x1000>;
 245                                 interrupts = <19>;
 246                                 fifosize = <128>;
 247                                 clocks = <&clks 15>;
 248                                 dmas = <&dmac0 6>, <&dmac0 7>;
 249                                 dma-names = "rx", "tx";
 250                         };
 251
 252                         usp0: usp@b0080000 {
 253                                 cell-index = <0>;
 254                                 compatible = "sirf,prima2-usp";
 255                                 reg = <0xb0080000 0x10000>;
 256                                 interrupts = <20>;
 257                                 fifosize = <128>;
 258                                 clocks = <&clks 28>;
 259                                 dmas = <&dmac1 1>, <&dmac1 2>;
 260                                 dma-names = "rx", "tx";
 261                         };
 262
 263                         usp1: usp@b0090000 {
 264                                 cell-index = <1>;
 265                                 compatible = "sirf,prima2-usp";
 266                                 reg = <0xb0090000 0x10000>;
 267                                 interrupts = <21>;
 268                                 fifosize = <128>;
 269                                 clocks = <&clks 29>;
 270                                 dmas = <&dmac0 14>, <&dmac0 15>;
 271                                 dma-names = "rx", "tx";
 272                         };
 273
 274                         usp2: usp@b00a0000 {
 275                                 cell-index = <2>;
 276                                 compatible = "sirf,prima2-usp";
 277                                 reg = <0xb00a0000 0x10000>;
 278                                 interrupts = <22>;
 279                                 fifosize = <128>;
 280                                 clocks = <&clks 30>;
 281                                 dmas = <&dmac0 10>, <&dmac0 11>;
 282                                 dma-names = "rx", "tx";
 283                         };
 284
 285                         dmac0: dma-controller@b00b0000 {
 286                                 cell-index = <0>;
 287                                 compatible = "sirf,prima2-dmac";
 288                                 reg = <0xb00b0000 0x10000>;
 289                                 interrupts = <12>;
 290                                 clocks = <&clks 24>;
 291                                 #dma-cells = <1>;
 292                         };
 293
 294                         dmac1: dma-controller@b0160000 {
 295                                 cell-index = <1>;
 296                                 compatible = "sirf,prima2-dmac";
 297                                 reg = <0xb0160000 0x10000>;
 298                                 interrupts = <13>;
 299                                 clocks = <&clks 25>;
 300                                 #dma-cells = <1>;
 301                         };
 302
 303                         vip@b00C0000 {
 304                                 compatible = "sirf,prima2-vip";
 305                                 reg = <0xb00C0000 0x10000>;
 306                                 clocks = <&clks 31>;
 307                                 interrupts = <14>;
 308                                 sirf,vip-dma-rx-channel = <16>;
 309                         };
 310
 311                         spi0: spi@b00d0000 {
 312                                 cell-index = <0>;
 313                                 compatible = "sirf,prima2-spi";
 314                                 reg = <0xb00d0000 0x10000>;
 315                                 interrupts = <15>;
 316                                 sirf,spi-num-chipselects = <1>;
 317                                 dmas = <&dmac1 9>,
 318                                      <&dmac1 4>;
 319                                 dma-names = "rx", "tx";
 320                                 #address-cells = <1>;
 321                                 #size-cells = <0>;
 322                                 clocks = <&clks 19>;
 323                                 status = "disabled";
 324                         };
 325
 326                         spi1: spi@b0170000 {
 327                                 cell-index = <1>;
 328                                 compatible = "sirf,prima2-spi";
 329                                 reg = <0xb0170000 0x10000>;
 330                                 interrupts = <16>;
 331                                 sirf,spi-num-chipselects = <1>;
 332                                 dmas = <&dmac0 12>,
 333                                      <&dmac0 13>;
 334                                 dma-names = "rx", "tx";
 335                                 #address-cells = <1>;
 336                                 #size-cells = <0>;
 337                                 clocks = <&clks 20>;
 338                                 status = "disabled";
 339                         };
 340
 341                         i2c0: i2c@b00e0000 {
 342                                 cell-index = <0>;
 343                                 compatible = "sirf,prima2-i2c";
 344                                 reg = <0xb00e0000 0x10000>;
 345                                 interrupts = <24>;
 346                                 clocks = <&clks 17>;
 347                                 #address-cells = <1>;
 348                                 #size-cells = <0>;
 349                         };
 350
 351                         i2c1: i2c@b00f0000 {
 352                                 cell-index = <1>;
 353                                 compatible = "sirf,prima2-i2c";
 354                                 reg = <0xb00f0000 0x10000>;
 355                                 interrupts = <25>;
 356                                 clocks = <&clks 18>;
 357                                 #address-cells = <1>;
 358                                 #size-cells = <0>;
 359                         };
 360
 361                         tsc@b0110000 {
 362                                 compatible = "sirf,prima2-tsc";
 363                                 reg = <0xb0110000 0x10000>;
 364                                 interrupts = <33>;
 365                                 clocks = <&clks 16>;
 366                         };
 367
 368                         gpio: pinctrl@b0120000 {
 369                                 #gpio-cells = <2>;
 370                                 #interrupt-cells = <2>;
 371                                 compatible = "sirf,prima2-pinctrl";
 372                                 reg = <0xb0120000 0x10000>;
 373                                 interrupts = <43 44 45 46 47>;
 374                                 gpio-controller;
 375                                 interrupt-controller;
 376
 377                                 lcd_16pins_a: lcd0@0 {
 378                                         lcd {
 379                                                 sirf,pins = "lcd_16bitsgrp";
 380                                                 sirf,function = "lcd_16bits";
 381                                         };
 382                                 };
 383                                 lcd_18pins_a: lcd0@1 {
 384                                         lcd {
 385                                                 sirf,pins = "lcd_18bitsgrp";
 386                                                 sirf,function = "lcd_18bits";
 387                                         };
 388                                 };
 389                                 lcd_24pins_a: lcd0@2 {
 390                                         lcd {
 391                                                 sirf,pins = "lcd_24bitsgrp";
 392                                                 sirf,function = "lcd_24bits";
 393                                         };
 394                                 };
 395                                 lcdrom_pins_a: lcdrom0@0 {
 396                                         lcd {
 397                                                 sirf,pins = "lcdromgrp";
 398                                                 sirf,function = "lcdrom";
 399                                         };
 400                                 };
 401                                 uart0_pins_a: uart0@0 {
 402                                         uart {
 403                                                 sirf,pins = "uart0grp";
 404                                                 sirf,function = "uart0";
 405                                         };
 406                                 };
 407                                 uart0_noflow_pins_a: uart0@1 {
 408                                         uart {
 409                                                 sirf,pins = "uart0_nostreamctrlgrp";
 410                                                 sirf,function = "uart0_nostreamctrl";
 411                                         };
 412                                 };
 413                                 uart1_pins_a: uart1@0 {
 414                                         uart {
 415                                                 sirf,pins = "uart1grp";
 416                                                 sirf,function = "uart1";
 417                                         };
 418                                 };
 419                                 uart2_pins_a: uart2@0 {
 420                                         uart {
 421                                                 sirf,pins = "uart2grp";
 422                                                 sirf,function = "uart2";
 423                                         };
 424                                 };
 425                                 uart2_noflow_pins_a: uart2@1 {
 426                                         uart {
 427                                                 sirf,pins = "uart2_nostreamctrlgrp";
 428                                                 sirf,function = "uart2_nostreamctrl";
 429                                         };
 430                                 };
 431                                 spi0_pins_a: spi0@0 {
 432                                         spi {
 433                                                 sirf,pins = "spi0grp";
 434                                                 sirf,function = "spi0";
 435                                         };
 436                                 };
 437                                 spi1_pins_a: spi1@0 {
 438                                         spi {
 439                                                 sirf,pins = "spi1grp";
 440                                                 sirf,function = "spi1";
 441                                         };
 442                                 };
 443                                 i2c0_pins_a: i2c0@0 {
 444                                         i2c {
 445                                                 sirf,pins = "i2c0grp";
 446                                                 sirf,function = "i2c0";
 447                                         };
 448                                 };
 449                                 i2c1_pins_a: i2c1@0 {
 450                                         i2c {
 451                                                 sirf,pins = "i2c1grp";
 452                                                 sirf,function = "i2c1";
 453                                         };
 454                                 };
 455                                 pwm0_pins_a: pwm0@0 {
 456                                         pwm {
 457                                                 sirf,pins = "pwm0grp";
 458                                                 sirf,function = "pwm0";
 459                                         };
 460                                 };
 461                                 pwm1_pins_a: pwm1@0 {
 462                                         pwm {
 463                                                 sirf,pins = "pwm1grp";
 464                                                 sirf,function = "pwm1";
 465                                         };
 466                                 };
 467                                 pwm2_pins_a: pwm2@0 {
 468                                         pwm {
 469                                                 sirf,pins = "pwm2grp";
 470                                                 sirf,function = "pwm2";
 471                                         };
 472                                 };
 473                                 pwm3_pins_a: pwm3@0 {
 474                                         pwm {
 475                                                 sirf,pins = "pwm3grp";
 476                                                 sirf,function = "pwm3";
 477                                         };
 478                                 };
 479                                 gps_pins_a: gps@0 {
 480                                         gps {
 481                                                 sirf,pins = "gpsgrp";
 482                                                 sirf,function = "gps";
 483                                         };
 484                                 };
 485                                 vip_pins_a: vip@0 {
 486                                         vip {
 487                                                 sirf,pins = "vipgrp";
 488                                                 sirf,function = "vip";
 489                                         };
 490                                 };
 491                                 sdmmc0_pins_a: sdmmc0@0 {
 492                                         sdmmc0 {
 493                                                 sirf,pins = "sdmmc0grp";
 494                                                 sirf,function = "sdmmc0";
 495                                         };
 496                                 };
 497                                 sdmmc1_pins_a: sdmmc1@0 {
 498                                         sdmmc1 {
 499                                                 sirf,pins = "sdmmc1grp";
 500                                                 sirf,function = "sdmmc1";
 501                                         };
 502                                 };
 503                                 sdmmc2_pins_a: sdmmc2@0 {
 504                                         sdmmc2 {
 505                                                 sirf,pins = "sdmmc2grp";
 506                                                 sirf,function = "sdmmc2";
 507                                         };
 508                                 };
 509                                 sdmmc3_pins_a: sdmmc3@0 {
 510                                         sdmmc3 {
 511                                                 sirf,pins = "sdmmc3grp";
 512                                                 sirf,function = "sdmmc3";
 513                                         };
 514                                 };
 515                                 sdmmc4_pins_a: sdmmc4@0 {
 516                                         sdmmc4 {
 517                                                 sirf,pins = "sdmmc4grp";
 518                                                 sirf,function = "sdmmc4";
 519                                         };
 520                                 };
 521                                 sdmmc5_pins_a: sdmmc5@0 {
 522                                         sdmmc5 {
 523                                                 sirf,pins = "sdmmc5grp";
 524                                                 sirf,function = "sdmmc5";
 525                                         };
 526                                 };
 527                                 i2s_pins_a: i2s@0 {
 528                                         i2s {
 529                                                 sirf,pins = "i2sgrp";
 530                                                 sirf,function = "i2s";
 531                                         };
 532                                 };
 533                                 ac97_pins_a: ac97@0 {
 534                                         ac97 {
 535                                                 sirf,pins = "ac97grp";
 536                                                 sirf,function = "ac97";
 537                                         };
 538                                 };
 539                                 nand_pins_a: nand@0 {
 540                                         nand {
 541                                                 sirf,pins = "nandgrp";
 542                                                 sirf,function = "nand";
 543                                         };
 544                                 };
 545                                 usp0_pins_a: usp0@0 {
 546                                         usp0 {
 547                                                 sirf,pins = "usp0grp";
 548                                                 sirf,function = "usp0";
 549                                         };
 550                                 };
 551                                 usp0_uart_nostreamctrl_pins_a: usp0@1 {
 552                                         usp0 {
 553                                                 sirf,pins =
 554                                                         "usp0_uart_nostreamctrl_grp";
 555                                                 sirf,function =
 556                                                         "usp0_uart_nostreamctrl";
 557                                         };
 558                                 };
 559                                 usp0_only_utfs_pins_a: usp0@2 {
 560                                         usp0 {
 561                                                 sirf,pins = "usp0_only_utfs_grp";
 562                                                 sirf,function = "usp0_only_utfs";
 563                                         };
 564                                 };
 565                                 usp0_only_urfs_pins_a: usp0@3 {
 566                                         usp0 {
 567                                                 sirf,pins = "usp0_only_urfs_grp";
 568                                                 sirf,function = "usp0_only_urfs";
 569                                         };
 570                                 };
 571                                 usp1_pins_a: usp1@0 {
 572                                         usp1 {
 573                                                 sirf,pins = "usp1grp";
 574                                                 sirf,function = "usp1";
 575                                         };
 576                                 };
 577                                 usp1_uart_nostreamctrl_pins_a: usp1@1 {
 578                                         usp1 {
 579                                                 sirf,pins =
 580                                                         "usp1_uart_nostreamctrl_grp";
 581                                                 sirf,function =
 582                                                         "usp1_uart_nostreamctrl";
 583                                         };
 584                                 };
 585                                 usp2_pins_a: usp2@0 {
 586                                         usp2 {
 587                                                 sirf,pins = "usp2grp";
 588                                                 sirf,function = "usp2";
 589                                         };
 590                                 };
 591                                 usp2_uart_nostreamctrl_pins_a: usp2@1 {
 592                                         usp2 {
 593                                                 sirf,pins =
 594                                                         "usp2_uart_nostreamctrl_grp";
 595                                                 sirf,function =
 596                                                         "usp2_uart_nostreamctrl";
 597                                         };
 598                                 };
 599                                 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
 600                                         usb0_utmi_drvbus {
 601                                                 sirf,pins = "usb0_utmi_drvbusgrp";
 602                                                 sirf,function = "usb0_utmi_drvbus";
 603                                         };
 604                                 };
 605                                 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
 606                                         usb1_utmi_drvbus {
 607                                                 sirf,pins = "usb1_utmi_drvbusgrp";
 608                                                 sirf,function = "usb1_utmi_drvbus";
 609                                         };
 610                                 };
 611                                 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
 612                                         usb1_dp_dn {
 613                                                 sirf,pins = "usb1_dp_dngrp";
 614                                                 sirf,function = "usb1_dp_dn";
 615                                         };
 616                                 };
 617                                 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
 618                                         uart1_route_io_usb1 {
 619                                                 sirf,pins = "uart1_route_io_usb1grp";
 620                                                 sirf,function = "uart1_route_io_usb1";
 621                                         };
 622                                 };
 623                                 warm_rst_pins_a: warm_rst@0 {
 624                                         warm_rst {
 625                                                 sirf,pins = "warm_rstgrp";
 626                                                 sirf,function = "warm_rst";
 627                                         };
 628                                 };
 629                                 pulse_count_pins_a: pulse_count@0 {
 630                                         pulse_count {
 631                                                 sirf,pins = "pulse_countgrp";
 632                                                 sirf,function = "pulse_count";
 633                                         };
 634                                 };
 635                                 cko0_pins_a: cko0@0 {
 636                                         cko0 {
 637                                                 sirf,pins = "cko0grp";
 638                                                 sirf,function = "cko0";
 639                                         };
 640                                 };
 641                                 cko1_pins_a: cko1@0 {
 642                                         cko1 {
 643                                                 sirf,pins = "cko1grp";
 644                                                 sirf,function = "cko1";
 645                                         };
 646                                 };
 647                         };
 648
 649                         pwm@b0130000 {
 650                                 compatible = "sirf,prima2-pwm";
 651                                 reg = <0xb0130000 0x10000>;
 652                                 clocks = <&clks 21>;
 653                         };
 654
 655                         efusesys@b0140000 {
 656                                 compatible = "sirf,prima2-efuse";
 657                                 reg = <0xb0140000 0x10000>;
 658                                 clocks = <&clks 22>;
 659                         };
 660
 661                         pulsec@b0150000 {
 662                                 compatible = "sirf,prima2-pulsec";
 663                                 reg = <0xb0150000 0x10000>;
 664                                 interrupts = <48>;
 665                                 clocks = <&clks 23>;
 666                         };
 667
 668                         pci-iobg {
 669                                 compatible = "sirf,prima2-pciiobg", "simple-bus";
 670                                 #address-cells = <1>;
 671                                 #size-cells = <1>;
 672                                 ranges = <0x56000000 0x56000000 0x1b00000>;
 673
 674                                 sd0: sdhci@56000000 {
 675                                         cell-index = <0>;
 676                                         compatible = "sirf,prima2-sdhc";
 677                                         reg = <0x56000000 0x100000>;
 678                                         interrupts = <38>;
 679                                         status = "disabled";
 680                                         bus-width = <8>;
 681                                         clocks = <&clks 36>;
 682                                 };
 683
 684                                 sd1: sdhci@56100000 {
 685                                         cell-index = <1>;
 686                                         compatible = "sirf,prima2-sdhc";
 687                                         reg = <0x56100000 0x100000>;
 688                                         interrupts = <38>;
 689                                         status = "disabled";
 690                                         bus-width = <4>;
 691                                         clocks = <&clks 36>;
 692                                 };
 693
 694                                 sd2: sdhci@56200000 {
 695                                         cell-index = <2>;
 696                                         compatible = "sirf,prima2-sdhc";
 697                                         reg = <0x56200000 0x100000>;
 698                                         interrupts = <23>;
 699                                         status = "disabled";
 700                                         clocks = <&clks 37>;
 701                                 };
 702
 703                                 sd3: sdhci@56300000 {
 704                                         cell-index = <3>;
 705                                         compatible = "sirf,prima2-sdhc";
 706                                         reg = <0x56300000 0x100000>;
 707                                         interrupts = <23>;
 708                                         status = "disabled";
 709                                         clocks = <&clks 37>;
 710                                 };
 711
 712                                 sd4: sdhci@56400000 {
 713                                         cell-index = <4>;
 714                                         compatible = "sirf,prima2-sdhc";
 715                                         reg = <0x56400000 0x100000>;
 716                                         interrupts = <39>;
 717                                         status = "disabled";
 718                                         clocks = <&clks 38>;
 719                                 };
 720
 721                                 sd5: sdhci@56500000 {
 722                                         cell-index = <5>;
 723                                         compatible = "sirf,prima2-sdhc";
 724                                         reg = <0x56500000 0x100000>;
 725                                         interrupts = <39>;
 726                                         clocks = <&clks 38>;
 727                                 };
 728
 729                                 pci-copy@57900000 {
 730                                         compatible = "sirf,prima2-pcicp";
 731                                         reg = <0x57900000 0x100000>;
 732                                         interrupts = <40>;
 733                                 };
 734
 735                                 rom-interface@57a00000 {
 736                                         compatible = "sirf,prima2-romif";
 737                                         reg = <0x57a00000 0x100000>;
 738                                 };
 739                         };
 740                 };
 741
 742                 rtc-iobg {
 743                         compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
 744                         #address-cells = <1>;
 745                         #size-cells = <1>;
 746                         reg = <0x80030000 0x10000>;
 747
 748                         gpsrtc@1000 {
 749                                 compatible = "sirf,prima2-gpsrtc";
 750                                 reg = <0x1000 0x1000>;
 751                                 interrupts = <55 56 57>;
 752                         };
 753
 754                         sysrtc@2000 {
 755                                 compatible = "sirf,prima2-sysrtc";
 756                                 reg = <0x2000 0x1000>;
 757                                 interrupts = <52 53 54>;
 758                         };
 759
 760                         minigpsrtc@2000 {
 761                                 compatible = "sirf,prima2-minigpsrtc";
 762                                 reg = <0x2000 0x1000>;
 763                                 interrupts = <54>;
 764                         };
 765
 766                         pwrc@3000 {
 767                                 compatible = "sirf,prima2-pwrc";
 768                                 reg = <0x3000 0x1000>;
 769                                 interrupts = <32>;
 770                         };
 771                 };
 772
 773                 uus-iobg {
 774                         compatible = "simple-bus";
 775                         #address-cells = <1>;
 776                         #size-cells = <1>;
 777                         ranges = <0xb8000000 0xb8000000 0x40000>;
 778
 779                         usb0: usb@b00e0000 {
 780                                 compatible = "chipidea,ci13611a-prima2";
 781                                 reg = <0xb8000000 0x10000>;
 782                                 interrupts = <10>;
 783                                 clocks = <&clks 40>;
 784                         };
 785
 786                         usb1: usb@b00f0000 {
 787                                 compatible = "chipidea,ci13611a-prima2";
 788                                 reg = <0xb8010000 0x10000>;
 789                                 interrupts = <11>;
 790                                 clocks = <&clks 41>;
 791                         };
 792
 793                         sata@b00f0000 {
 794                                 compatible = "synopsys,dwc-ahsata";
 795                                 reg = <0xb8020000 0x10000>;
 796                                 interrupts = <37>;
 797                         };
 798
 799                         security@b00f0000 {
 800                                 compatible = "sirf,prima2-security";
 801                                 reg = <0xb8030000 0x10000>;
 802                                 interrupts = <42>;
 803                                 clocks = <&clks 7>;
 804                         };
 805                 };
 806         };
 807 };