| blob | 3b2a94c40f6e3f7ee7666c534149715f7d7e8b7d |
1 /*
2 * Copyright 2012 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
14 /include/ "skeleton.dtsi"
16 / {
17 interrupt-parent = <&intc>;
19 aliases {
20 serial0 = &uart1;
21 serial1 = &uart3;
22 };
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27 cpu@0 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a8";
30 reg = <0x0>;
31 };
32 };
34 memory {
35 reg = <0x40000000 0x20000000>;
36 };
38 clocks {
39 #address-cells = <1>;
40 #size-cells = <1>;
41 ranges;
43 /*
44 * This is a dummy clock, to be used as placeholder on
45 * other mux clocks when a specific parent clock is not
46 * yet implemented. It should be dropped when the driver
47 * is complete.
48 */
49 dummy: dummy {
50 #clock-cells = <0>;
51 compatible = "fixed-clock";
52 clock-frequency = <0>;
53 };
55 osc24M: clk@01c20050 {
56 #clock-cells = <0>;
57 compatible = "allwinner,sun4i-a10-osc-clk";
58 reg = <0x01c20050 0x4>;
59 clock-frequency = <24000000>;
60 clock-output-names = "osc24M";
61 };
63 osc32k: clk@0 {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
67 clock-output-names = "osc32k";
68 };
70 pll1: clk@01c20000 {
71 #clock-cells = <0>;
72 compatible = "allwinner,sun4i-a10-pll1-clk";
73 reg = <0x01c20000 0x4>;
74 clocks = <&osc24M>;
75 clock-output-names = "pll1";
76 };
78 pll4: clk@01c20018 {
79 #clock-cells = <0>;
80 compatible = "allwinner,sun4i-a10-pll1-clk";
81 reg = <0x01c20018 0x4>;
82 clocks = <&osc24M>;
83 clock-output-names = "pll4";
84 };
86 pll5: clk@01c20020 {
87 #clock-cells = <1>;
88 compatible = "allwinner,sun4i-a10-pll5-clk";
89 reg = <0x01c20020 0x4>;
90 clocks = <&osc24M>;
91 clock-output-names = "pll5_ddr", "pll5_other";
92 };
94 pll6: clk@01c20028 {
95 #clock-cells = <1>;
96 compatible = "allwinner,sun4i-a10-pll6-clk";
97 reg = <0x01c20028 0x4>;
98 clocks = <&osc24M>;
99 clock-output-names = "pll6_sata", "pll6_other", "pll6";
100 };
102 /* dummy is 200M */
103 cpu: cpu@01c20054 {
104 #clock-cells = <0>;
105 compatible = "allwinner,sun4i-a10-cpu-clk";
106 reg = <0x01c20054 0x4>;
107 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
108 clock-output-names = "cpu";
109 };
111 axi: axi@01c20054 {
112 #clock-cells = <0>;
113 compatible = "allwinner,sun4i-a10-axi-clk";
114 reg = <0x01c20054 0x4>;
115 clocks = <&cpu>;
116 clock-output-names = "axi";
117 };
119 axi_gates: clk@01c2005c {
120 #clock-cells = <1>;
121 compatible = "allwinner,sun4i-a10-axi-gates-clk";
122 reg = <0x01c2005c 0x4>;
123 clocks = <&axi>;
124 clock-output-names = "axi_dram";
125 };
127 ahb: ahb@01c20054 {
128 #clock-cells = <0>;
129 compatible = "allwinner,sun4i-a10-ahb-clk";
130 reg = <0x01c20054 0x4>;
131 clocks = <&axi>;
132 clock-output-names = "ahb";
133 };
135 ahb_gates: clk@01c20060 {
136 #clock-cells = <1>;
137 compatible = "allwinner,sun5i-a13-ahb-gates-clk";
138 reg = <0x01c20060 0x8>;
139 clocks = <&ahb>;
140 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
141 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
142 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
143 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
144 "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
145 "ahb_de_fe", "ahb_iep", "ahb_mali400";
146 };
148 apb0: apb0@01c20054 {
149 #clock-cells = <0>;
150 compatible = "allwinner,sun4i-a10-apb0-clk";
151 reg = <0x01c20054 0x4>;
152 clocks = <&ahb>;
153 clock-output-names = "apb0";
154 };
156 apb0_gates: clk@01c20068 {
157 #clock-cells = <1>;
158 compatible = "allwinner,sun5i-a13-apb0-gates-clk";
159 reg = <0x01c20068 0x4>;
160 clocks = <&apb0>;
161 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
162 };
164 apb1_mux: apb1_mux@01c20058 {
165 #clock-cells = <0>;
166 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
167 reg = <0x01c20058 0x4>;
168 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
169 clock-output-names = "apb1_mux";
170 };
172 apb1: apb1@01c20058 {
173 #clock-cells = <0>;
174 compatible = "allwinner,sun4i-a10-apb1-clk";
175 reg = <0x01c20058 0x4>;
176 clocks = <&apb1_mux>;
177 clock-output-names = "apb1";
178 };
180 apb1_gates: clk@01c2006c {
181 #clock-cells = <1>;
182 compatible = "allwinner,sun5i-a13-apb1-gates-clk";
183 reg = <0x01c2006c 0x4>;
184 clocks = <&apb1>;
185 clock-output-names = "apb1_i2c0", "apb1_i2c1",
186 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
187 };
189 nand_clk: clk@01c20080 {
190 #clock-cells = <0>;
191 compatible = "allwinner,sun4i-a10-mod0-clk";
192 reg = <0x01c20080 0x4>;
193 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
194 clock-output-names = "nand";
195 };
197 ms_clk: clk@01c20084 {
198 #clock-cells = <0>;
199 compatible = "allwinner,sun4i-a10-mod0-clk";
200 reg = <0x01c20084 0x4>;
201 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
202 clock-output-names = "ms";
203 };
205 mmc0_clk: clk@01c20088 {
206 #clock-cells = <0>;
207 compatible = "allwinner,sun4i-a10-mod0-clk";
208 reg = <0x01c20088 0x4>;
209 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
210 clock-output-names = "mmc0";
211 };
213 mmc1_clk: clk@01c2008c {
214 #clock-cells = <0>;
215 compatible = "allwinner,sun4i-a10-mod0-clk";
216 reg = <0x01c2008c 0x4>;
217 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
218 clock-output-names = "mmc1";
219 };
221 mmc2_clk: clk@01c20090 {
222 #clock-cells = <0>;
223 compatible = "allwinner,sun4i-a10-mod0-clk";
224 reg = <0x01c20090 0x4>;
225 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
226 clock-output-names = "mmc2";
227 };
229 ts_clk: clk@01c20098 {
230 #clock-cells = <0>;
231 compatible = "allwinner,sun4i-a10-mod0-clk";
232 reg = <0x01c20098 0x4>;
233 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
234 clock-output-names = "ts";
235 };
237 ss_clk: clk@01c2009c {
238 #clock-cells = <0>;
239 compatible = "allwinner,sun4i-a10-mod0-clk";
240 reg = <0x01c2009c 0x4>;
241 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
242 clock-output-names = "ss";
243 };
245 spi0_clk: clk@01c200a0 {
246 #clock-cells = <0>;
247 compatible = "allwinner,sun4i-a10-mod0-clk";
248 reg = <0x01c200a0 0x4>;
249 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
250 clock-output-names = "spi0";
251 };
253 spi1_clk: clk@01c200a4 {
254 #clock-cells = <0>;
255 compatible = "allwinner,sun4i-a10-mod0-clk";
256 reg = <0x01c200a4 0x4>;
257 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
258 clock-output-names = "spi1";
259 };
261 spi2_clk: clk@01c200a8 {
262 #clock-cells = <0>;
263 compatible = "allwinner,sun4i-a10-mod0-clk";
264 reg = <0x01c200a8 0x4>;
265 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
266 clock-output-names = "spi2";
267 };
269 ir0_clk: clk@01c200b0 {
270 #clock-cells = <0>;
271 compatible = "allwinner,sun4i-a10-mod0-clk";
272 reg = <0x01c200b0 0x4>;
273 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
274 clock-output-names = "ir0";
275 };
277 usb_clk: clk@01c200cc {
278 #clock-cells = <1>;
279 #reset-cells = <1>;
280 compatible = "allwinner,sun5i-a13-usb-clk";
281 reg = <0x01c200cc 0x4>;
282 clocks = <&pll6 1>;
283 clock-output-names = "usb_ohci0", "usb_phy";
284 };
286 mbus_clk: clk@01c2015c {
287 #clock-cells = <0>;
288 compatible = "allwinner,sun4i-a10-mod0-clk";
289 reg = <0x01c2015c 0x4>;
290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
291 clock-output-names = "mbus";
292 };
293 };
295 soc@01c00000 {
296 compatible = "simple-bus";
297 #address-cells = <1>;
298 #size-cells = <1>;
299 ranges;
301 spi0: spi@01c05000 {
302 compatible = "allwinner,sun4i-a10-spi";
303 reg = <0x01c05000 0x1000>;
304 interrupts = <10>;
305 clocks = <&ahb_gates 20>, <&spi0_clk>;
306 clock-names = "ahb", "mod";
307 status = "disabled";
308 #address-cells = <1>;
309 #size-cells = <0>;
310 };
312 spi1: spi@01c06000 {
313 compatible = "allwinner,sun4i-a10-spi";
314 reg = <0x01c06000 0x1000>;
315 interrupts = <11>;
316 clocks = <&ahb_gates 21>, <&spi1_clk>;
317 clock-names = "ahb", "mod";
318 status = "disabled";
319 #address-cells = <1>;
320 #size-cells = <0>;
321 };
323 mmc0: mmc@01c0f000 {
324 compatible = "allwinner,sun5i-a13-mmc";
325 reg = <0x01c0f000 0x1000>;
326 clocks = <&ahb_gates 8>, <&mmc0_clk>;
327 clock-names = "ahb", "mmc";
328 interrupts = <32>;
329 status = "disabled";
330 };
332 mmc2: mmc@01c11000 {
333 compatible = "allwinner,sun5i-a13-mmc";
334 reg = <0x01c11000 0x1000>;
335 clocks = <&ahb_gates 10>, <&mmc2_clk>;
336 clock-names = "ahb", "mmc";
337 interrupts = <34>;
338 status = "disabled";
339 };
341 usbphy: phy@01c13400 {
342 #phy-cells = <1>;
343 compatible = "allwinner,sun5i-a13-usb-phy";
344 reg = <0x01c13400 0x10 0x01c14800 0x4>;
345 reg-names = "phy_ctrl", "pmu1";
346 clocks = <&usb_clk 8>;
347 clock-names = "usb_phy";
348 resets = <&usb_clk 1>;
349 reset-names = "usb1_reset";
350 status = "disabled";
351 };
353 ehci0: usb@01c14000 {
354 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
355 reg = <0x01c14000 0x100>;
356 interrupts = <39>;
357 clocks = <&ahb_gates 1>;
358 phys = <&usbphy 1>;
359 phy-names = "usb";
360 status = "disabled";
361 };
363 ohci0: usb@01c14400 {
364 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
365 reg = <0x01c14400 0x100>;
366 interrupts = <40>;
367 clocks = <&usb_clk 6>, <&ahb_gates 2>;
368 phys = <&usbphy 1>;
369 phy-names = "usb";
370 status = "disabled";
371 };
373 spi2: spi@01c17000 {
374 compatible = "allwinner,sun4i-a10-spi";
375 reg = <0x01c17000 0x1000>;
376 interrupts = <12>;
377 clocks = <&ahb_gates 22>, <&spi2_clk>;
378 clock-names = "ahb", "mod";
379 status = "disabled";
380 #address-cells = <1>;
381 #size-cells = <0>;
382 };
384 intc: interrupt-controller@01c20400 {
385 compatible = "allwinner,sun4i-a10-ic";
386 reg = <0x01c20400 0x400>;
387 interrupt-controller;
388 #interrupt-cells = <1>;
389 };
391 pio: pinctrl@01c20800 {
392 compatible = "allwinner,sun5i-a13-pinctrl";
393 reg = <0x01c20800 0x400>;
394 interrupts = <28>;
395 clocks = <&apb0_gates 5>;
396 gpio-controller;
397 interrupt-controller;
398 #address-cells = <1>;
399 #size-cells = <0>;
400 #gpio-cells = <3>;
402 uart1_pins_a: uart1@0 {
403 allwinner,pins = "PE10", "PE11";
404 allwinner,function = "uart1";
405 allwinner,drive = <0>;
406 allwinner,pull = <0>;
407 };
409 uart1_pins_b: uart1@1 {
410 allwinner,pins = "PG3", "PG4";
411 allwinner,function = "uart1";
412 allwinner,drive = <0>;
413 allwinner,pull = <0>;
414 };
416 i2c0_pins_a: i2c0@0 {
417 allwinner,pins = "PB0", "PB1";
418 allwinner,function = "i2c0";
419 allwinner,drive = <0>;
420 allwinner,pull = <0>;
421 };
423 i2c1_pins_a: i2c1@0 {
424 allwinner,pins = "PB15", "PB16";
425 allwinner,function = "i2c1";
426 allwinner,drive = <0>;
427 allwinner,pull = <0>;
428 };
430 i2c2_pins_a: i2c2@0 {
431 allwinner,pins = "PB17", "PB18";
432 allwinner,function = "i2c2";
433 allwinner,drive = <0>;
434 allwinner,pull = <0>;
435 };
437 mmc0_pins_a: mmc0@0 {
438 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
439 allwinner,function = "mmc0";
440 allwinner,drive = <2>;
441 allwinner,pull = <0>;
442 };
443 };
445 timer@01c20c00 {
446 compatible = "allwinner,sun4i-a10-timer";
447 reg = <0x01c20c00 0x90>;
448 interrupts = <22>;
449 clocks = <&osc24M>;
450 };
452 wdt: watchdog@01c20c90 {
453 compatible = "allwinner,sun4i-a10-wdt";
454 reg = <0x01c20c90 0x10>;
455 };
457 sid: eeprom@01c23800 {
458 compatible = "allwinner,sun4i-a10-sid";
459 reg = <0x01c23800 0x10>;
460 };
462 rtp: rtp@01c25000 {
463 compatible = "allwinner,sun4i-a10-ts";
464 reg = <0x01c25000 0x100>;
465 interrupts = <29>;
466 };
468 uart1: serial@01c28400 {
469 compatible = "snps,dw-apb-uart";
470 reg = <0x01c28400 0x400>;
471 interrupts = <2>;
472 reg-shift = <2>;
473 reg-io-width = <4>;
474 clocks = <&apb1_gates 17>;
475 status = "disabled";
476 };
478 uart3: serial@01c28c00 {
479 compatible = "snps,dw-apb-uart";
480 reg = <0x01c28c00 0x400>;
481 interrupts = <4>;
482 reg-shift = <2>;
483 reg-io-width = <4>;
484 clocks = <&apb1_gates 19>;
485 status = "disabled";
486 };
488 i2c0: i2c@01c2ac00 {
489 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
490 reg = <0x01c2ac00 0x400>;
491 interrupts = <7>;
492 clocks = <&apb1_gates 0>;
493 clock-frequency = <100000>;
494 status = "disabled";
495 #address-cells = <1>;
496 #size-cells = <0>;
497 };
499 i2c1: i2c@01c2b000 {
500 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
501 reg = <0x01c2b000 0x400>;
502 interrupts = <8>;
503 clocks = <&apb1_gates 1>;
504 clock-frequency = <100000>;
505 status = "disabled";
506 #address-cells = <1>;
507 #size-cells = <0>;
508 };
510 i2c2: i2c@01c2b400 {
511 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
512 reg = <0x01c2b400 0x400>;
513 interrupts = <9>;
514 clocks = <&apb1_gates 2>;
515 clock-frequency = <100000>;
516 status = "disabled";
517 #address-cells = <1>;
518 #size-cells = <0>;
519 };
521 timer@01c60000 {
522 compatible = "allwinner,sun5i-a13-hstimer";
523 reg = <0x01c60000 0x1000>;
524 interrupts = <82>, <83>;
525 clocks = <&ahb_gates 28>;
526 };
527 };
528 };