arch/arm/mach-at91/at91rm9200_time.c

   1 /*
   2  * linux/arch/arm/mach-at91/at91rm9200_time.c
   3  *
   4  *  Copyright (C) 2003 SAN People
   5  *  Copyright (C) 2003 ATMEL
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/clockchips.h>
  26 #include <linux/export.h>
  27 #include <linux/of.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_irq.h>
  30
  31 #include <asm/mach/time.h>
  32
  33 #include <mach/at91_st.h>
  34 #include <mach/hardware.h>
  35
  36 static unsigned long last_crtr;
  37 static u32 irqmask;
  38 static struct clock_event_device clkevt;
  39
  40 #define RM9200_TIMER_LATCH      ((AT91_SLOW_CLOCK + HZ/2) / HZ)
  41
  42 /*
  43  * The ST_CRTR is updated asynchronously to the master clock ... but
  44  * the updates as seen by the CPU don't seem to be strictly monotonic.
  45  * Waiting until we read the same value twice avoids glitching.
  46  */
  47 static inline unsigned long read_CRTR(void)
  48 {
  49         unsigned long x1, x2;
  50
  51         x1 = at91_st_read(AT91_ST_CRTR);
  52         do {
  53                 x2 = at91_st_read(AT91_ST_CRTR);
  54                 if (x1 == x2)
  55                         break;
  56                 x1 = x2;
  57         } while (1);
  58         return x1;
  59 }
  60
  61 /*
  62  * IRQ handler for the timer.
  63  */
  64 static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
  65 {
  66         u32     sr = at91_st_read(AT91_ST_SR) & irqmask;
  67
  68         /*
  69          * irqs should be disabled here, but as the irq is shared they are only
  70          * guaranteed to be off if the timer irq is registered first.
  71          */
  72         WARN_ON_ONCE(!irqs_disabled());
  73
  74         /* simulate "oneshot" timer with alarm */
  75         if (sr & AT91_ST_ALMS) {
  76                 clkevt.event_handler(&clkevt);
  77                 return IRQ_HANDLED;
  78         }
  79
  80         /* periodic mode should handle delayed ticks */
  81         if (sr & AT91_ST_PITS) {
  82                 u32     crtr = read_CRTR();
  83
  84                 while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) {
  85                         last_crtr += RM9200_TIMER_LATCH;
  86                         clkevt.event_handler(&clkevt);
  87                 }
  88                 return IRQ_HANDLED;
  89         }
  90
  91         /* this irq is shared ... */
  92         return IRQ_NONE;
  93 }
  94
  95 static struct irqaction at91rm9200_timer_irq = {
  96         .name           = "at91_tick",
  97         .flags          = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
  98         .handler        = at91rm9200_timer_interrupt,
  99         .irq            = NR_IRQS_LEGACY + AT91_ID_SYS,
 100 };
 101
 102 static cycle_t read_clk32k(struct clocksource *cs)
 103 {
 104         return read_CRTR();
 105 }
 106
 107 static struct clocksource clk32k = {
 108         .name           = "32k_counter",
 109         .rating         = 150,
 110         .read           = read_clk32k,
 111         .mask           = CLOCKSOURCE_MASK(20),
 112         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 113 };
 114
 115 static void
 116 clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 117 {
 118         /* Disable and flush pending timer interrupts */
 119         at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
 120         at91_st_read(AT91_ST_SR);
 121
 122         last_crtr = read_CRTR();
 123         switch (mode) {
 124         case CLOCK_EVT_MODE_PERIODIC:
 125                 /* PIT for periodic irqs; fixed rate of 1/HZ */
 126                 irqmask = AT91_ST_PITS;
 127                 at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
 128                 break;
 129         case CLOCK_EVT_MODE_ONESHOT:
 130                 /* ALM for oneshot irqs, set by next_event()
 131                  * before 32 seconds have passed
 132                  */
 133                 irqmask = AT91_ST_ALMS;
 134                 at91_st_write(AT91_ST_RTAR, last_crtr);
 135                 break;
 136         case CLOCK_EVT_MODE_SHUTDOWN:
 137         case CLOCK_EVT_MODE_UNUSED:
 138         case CLOCK_EVT_MODE_RESUME:
 139                 irqmask = 0;
 140                 break;
 141         }
 142         at91_st_write(AT91_ST_IER, irqmask);
 143 }
 144
 145 static int
 146 clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
 147 {
 148         u32             alm;
 149         int             status = 0;
 150
 151         BUG_ON(delta < 2);
 152
 153         /* The alarm IRQ uses absolute time (now+delta), not the relative
 154          * time (delta) in our calling convention.  Like all clockevents
 155          * using such "match" hardware, we have a race to defend against.
 156          *
 157          * Our defense here is to have set up the clockevent device so the
 158          * delta is at least two.  That way we never end up writing RTAR
 159          * with the value then held in CRTR ... which would mean the match
 160          * wouldn't trigger until 32 seconds later, after CRTR wraps.
 161          */
 162         alm = read_CRTR();
 163
 164         /* Cancel any pending alarm; flush any pending IRQ */
 165         at91_st_write(AT91_ST_RTAR, alm);
 166         at91_st_read(AT91_ST_SR);
 167
 168         /* Schedule alarm by writing RTAR. */
 169         alm += delta;
 170         at91_st_write(AT91_ST_RTAR, alm);
 171
 172         return status;
 173 }
 174
 175 static struct clock_event_device clkevt = {
 176         .name           = "at91_tick",
 177         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 178         .rating         = 150,
 179         .set_next_event = clkevt32k_next_event,
 180         .set_mode       = clkevt32k_mode,
 181 };
 182
 183 void __iomem *at91_st_base;
 184 EXPORT_SYMBOL_GPL(at91_st_base);
 185
 186 #ifdef CONFIG_OF
 187 static struct of_device_id at91rm9200_st_timer_ids[] = {
 188         { .compatible = "atmel,at91rm9200-st" },
 189         { /* sentinel */ }
 190 };
 191
 192 static int __init of_at91rm9200_st_init(void)
 193 {
 194         struct device_node *np;
 195         int ret;
 196
 197         np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
 198         if (!np)
 199                 goto err;
 200
 201         at91_st_base = of_iomap(np, 0);
 202         if (!at91_st_base)
 203                 goto node_err;
 204
 205         /* Get the interrupts property */
 206         ret = irq_of_parse_and_map(np, 0);
 207         if (!ret)
 208                 goto ioremap_err;
 209         at91rm9200_timer_irq.irq = ret;
 210
 211         of_node_put(np);
 212
 213         return 0;
 214
 215 ioremap_err:
 216         iounmap(at91_st_base);
 217 node_err:
 218         of_node_put(np);
 219 err:
 220         return -EINVAL;
 221 }
 222 #else
 223 static int __init of_at91rm9200_st_init(void)
 224 {
 225         return -EINVAL;
 226 }
 227 #endif
 228
 229 void __init at91rm9200_ioremap_st(u32 addr)
 230 {
 231 #ifdef CONFIG_OF
 232         struct device_node *np;
 233
 234         np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
 235         if (np) {
 236                 of_node_put(np);
 237                 return;
 238         }
 239 #endif
 240         at91_st_base = ioremap(addr, 256);
 241         if (!at91_st_base)
 242                 panic("Impossible to ioremap ST\n");
 243 }
 244
 245 /*
 246  * ST (system timer) module supports both clockevents and clocksource.
 247  */
 248 void __init at91rm9200_timer_init(void)
 249 {
 250         /* For device tree enabled device: initialize here */
 251         of_at91rm9200_st_init();
 252
 253         /* Disable all timer interrupts, and clear any pending ones */
 254         at91_st_write(AT91_ST_IDR,
 255                 AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
 256         at91_st_read(AT91_ST_SR);
 257
 258         /* Make IRQs happen for the system timer */
 259         setup_irq(at91rm9200_timer_irq.irq, &at91rm9200_timer_irq);
 260
 261         /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
 262          * directly for the clocksource and all clockevents, after adjusting
 263          * its prescaler from the 1 Hz default.
 264          */
 265         at91_st_write(AT91_ST_RTMR, 1);
 266
 267         /* Setup timer clockevent, with minimum of two ticks (important!!) */
 268         clkevt.cpumask = cpumask_of(0);
 269         clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
 270                                         2, AT91_ST_ALMV);
 271
 272         /* register clocksource */
 273         clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
 274 }