2 * Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
18 #include <linux/module.h>
19 #include <linux/clk.h>
20 #include <linux/clkdev.h>
22 #include <linux/err.h>
27 #include "crmregs-imx3.h"
31 static const char *mcu_main_sel
[] = { "spll", "mpll", };
32 static const char *per_sel
[] = { "per_div", "ipg", };
33 static const char *csi_sel
[] = { "upll", "spll", };
34 static const char *fir_sel
[] = { "mcu_main", "upll", "spll" };
37 dummy
, ckih
, ckil
, mpll
, spll
, upll
, mcu_main
, hsp
, ahb
, nfc
, ipg
,
38 per_div
, per
, csi
, fir
, csi_div
, usb_div_pre
, usb_div_post
, fir_div_pre
,
39 fir_div_post
, sdhc1_gate
, sdhc2_gate
, gpt_gate
, epit1_gate
, epit2_gate
,
40 iim_gate
, ata_gate
, sdma_gate
, cspi3_gate
, rng_gate
, uart1_gate
,
41 uart2_gate
, ssi1_gate
, i2c1_gate
, i2c2_gate
, i2c3_gate
, hantro_gate
,
42 mstick1_gate
, mstick2_gate
, csi_gate
, rtc_gate
, wdog_gate
, pwm_gate
,
43 sim_gate
, ect_gate
, usb_gate
, kpp_gate
, ipu_gate
, uart3_gate
,
44 uart4_gate
, uart5_gate
, owire_gate
, ssi2_gate
, cspi1_gate
, cspi2_gate
,
45 gacc_gate
, emi_gate
, rtic_gate
, firi_gate
, clk_max
48 static struct clk
*clk
[clk_max
];
49 static struct clk_onecell_data clk_data
;
51 int __init
mx31_clocks_init(unsigned long fref
)
53 void __iomem
*base
= MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR
);
55 struct device_node
*np
;
57 clk
[dummy
] = imx_clk_fixed("dummy", 0);
58 clk
[ckih
] = imx_clk_fixed("ckih", fref
);
59 clk
[ckil
] = imx_clk_fixed("ckil", 32768);
60 clk
[mpll
] = imx_clk_pllv1("mpll", "ckih", base
+ MXC_CCM_MPCTL
);
61 clk
[spll
] = imx_clk_pllv1("spll", "ckih", base
+ MXC_CCM_SRPCTL
);
62 clk
[upll
] = imx_clk_pllv1("upll", "ckih", base
+ MXC_CCM_UPCTL
);
63 clk
[mcu_main
] = imx_clk_mux("mcu_main", base
+ MXC_CCM_PMCR0
, 31, 1, mcu_main_sel
, ARRAY_SIZE(mcu_main_sel
));
64 clk
[hsp
] = imx_clk_divider("hsp", "mcu_main", base
+ MXC_CCM_PDR0
, 11, 3);
65 clk
[ahb
] = imx_clk_divider("ahb", "mcu_main", base
+ MXC_CCM_PDR0
, 3, 3);
66 clk
[nfc
] = imx_clk_divider("nfc", "ahb", base
+ MXC_CCM_PDR0
, 8, 3);
67 clk
[ipg
] = imx_clk_divider("ipg", "ahb", base
+ MXC_CCM_PDR0
, 6, 2);
68 clk
[per_div
] = imx_clk_divider("per_div", "upll", base
+ MXC_CCM_PDR0
, 16, 5);
69 clk
[per
] = imx_clk_mux("per", base
+ MXC_CCM_CCMR
, 24, 1, per_sel
, ARRAY_SIZE(per_sel
));
70 clk
[csi
] = imx_clk_mux("csi_sel", base
+ MXC_CCM_CCMR
, 25, 1, csi_sel
, ARRAY_SIZE(csi_sel
));
71 clk
[fir
] = imx_clk_mux("fir_sel", base
+ MXC_CCM_CCMR
, 11, 2, fir_sel
, ARRAY_SIZE(fir_sel
));
72 clk
[csi_div
] = imx_clk_divider("csi_div", "csi_sel", base
+ MXC_CCM_PDR0
, 23, 9);
73 clk
[usb_div_pre
] = imx_clk_divider("usb_div_pre", "upll", base
+ MXC_CCM_PDR1
, 30, 2);
74 clk
[usb_div_post
] = imx_clk_divider("usb_div_post", "usb_div_pre", base
+ MXC_CCM_PDR1
, 27, 3);
75 clk
[fir_div_pre
] = imx_clk_divider("fir_div_pre", "fir_sel", base
+ MXC_CCM_PDR1
, 24, 3);
76 clk
[fir_div_post
] = imx_clk_divider("fir_div_post", "fir_div_pre", base
+ MXC_CCM_PDR1
, 23, 6);
77 clk
[sdhc1_gate
] = imx_clk_gate2("sdhc1_gate", "per", base
+ MXC_CCM_CGR0
, 0);
78 clk
[sdhc2_gate
] = imx_clk_gate2("sdhc2_gate", "per", base
+ MXC_CCM_CGR0
, 2);
79 clk
[gpt_gate
] = imx_clk_gate2("gpt_gate", "per", base
+ MXC_CCM_CGR0
, 4);
80 clk
[epit1_gate
] = imx_clk_gate2("epit1_gate", "per", base
+ MXC_CCM_CGR0
, 6);
81 clk
[epit2_gate
] = imx_clk_gate2("epit2_gate", "per", base
+ MXC_CCM_CGR0
, 8);
82 clk
[iim_gate
] = imx_clk_gate2("iim_gate", "ipg", base
+ MXC_CCM_CGR0
, 10);
83 clk
[ata_gate
] = imx_clk_gate2("ata_gate", "ipg", base
+ MXC_CCM_CGR0
, 12);
84 clk
[sdma_gate
] = imx_clk_gate2("sdma_gate", "ahb", base
+ MXC_CCM_CGR0
, 14);
85 clk
[cspi3_gate
] = imx_clk_gate2("cspi3_gate", "ipg", base
+ MXC_CCM_CGR0
, 16);
86 clk
[rng_gate
] = imx_clk_gate2("rng_gate", "ipg", base
+ MXC_CCM_CGR0
, 18);
87 clk
[uart1_gate
] = imx_clk_gate2("uart1_gate", "per", base
+ MXC_CCM_CGR0
, 20);
88 clk
[uart2_gate
] = imx_clk_gate2("uart2_gate", "per", base
+ MXC_CCM_CGR0
, 22);
89 clk
[ssi1_gate
] = imx_clk_gate2("ssi1_gate", "spll", base
+ MXC_CCM_CGR0
, 24);
90 clk
[i2c1_gate
] = imx_clk_gate2("i2c1_gate", "per", base
+ MXC_CCM_CGR0
, 26);
91 clk
[i2c2_gate
] = imx_clk_gate2("i2c2_gate", "per", base
+ MXC_CCM_CGR0
, 28);
92 clk
[i2c3_gate
] = imx_clk_gate2("i2c3_gate", "per", base
+ MXC_CCM_CGR0
, 30);
93 clk
[hantro_gate
] = imx_clk_gate2("hantro_gate", "per", base
+ MXC_CCM_CGR1
, 0);
94 clk
[mstick1_gate
] = imx_clk_gate2("mstick1_gate", "per", base
+ MXC_CCM_CGR1
, 2);
95 clk
[mstick2_gate
] = imx_clk_gate2("mstick2_gate", "per", base
+ MXC_CCM_CGR1
, 4);
96 clk
[csi_gate
] = imx_clk_gate2("csi_gate", "csi_div", base
+ MXC_CCM_CGR1
, 6);
97 clk
[rtc_gate
] = imx_clk_gate2("rtc_gate", "ipg", base
+ MXC_CCM_CGR1
, 8);
98 clk
[wdog_gate
] = imx_clk_gate2("wdog_gate", "ipg", base
+ MXC_CCM_CGR1
, 10);
99 clk
[pwm_gate
] = imx_clk_gate2("pwm_gate", "per", base
+ MXC_CCM_CGR1
, 12);
100 clk
[sim_gate
] = imx_clk_gate2("sim_gate", "per", base
+ MXC_CCM_CGR1
, 14);
101 clk
[ect_gate
] = imx_clk_gate2("ect_gate", "per", base
+ MXC_CCM_CGR1
, 16);
102 clk
[usb_gate
] = imx_clk_gate2("usb_gate", "ahb", base
+ MXC_CCM_CGR1
, 18);
103 clk
[kpp_gate
] = imx_clk_gate2("kpp_gate", "ipg", base
+ MXC_CCM_CGR1
, 20);
104 clk
[ipu_gate
] = imx_clk_gate2("ipu_gate", "hsp", base
+ MXC_CCM_CGR1
, 22);
105 clk
[uart3_gate
] = imx_clk_gate2("uart3_gate", "per", base
+ MXC_CCM_CGR1
, 24);
106 clk
[uart4_gate
] = imx_clk_gate2("uart4_gate", "per", base
+ MXC_CCM_CGR1
, 26);
107 clk
[uart5_gate
] = imx_clk_gate2("uart5_gate", "per", base
+ MXC_CCM_CGR1
, 28);
108 clk
[owire_gate
] = imx_clk_gate2("owire_gate", "per", base
+ MXC_CCM_CGR1
, 30);
109 clk
[ssi2_gate
] = imx_clk_gate2("ssi2_gate", "spll", base
+ MXC_CCM_CGR2
, 0);
110 clk
[cspi1_gate
] = imx_clk_gate2("cspi1_gate", "ipg", base
+ MXC_CCM_CGR2
, 2);
111 clk
[cspi2_gate
] = imx_clk_gate2("cspi2_gate", "ipg", base
+ MXC_CCM_CGR2
, 4);
112 clk
[gacc_gate
] = imx_clk_gate2("gacc_gate", "per", base
+ MXC_CCM_CGR2
, 6);
113 clk
[emi_gate
] = imx_clk_gate2("emi_gate", "ahb", base
+ MXC_CCM_CGR2
, 8);
114 clk
[rtic_gate
] = imx_clk_gate2("rtic_gate", "ahb", base
+ MXC_CCM_CGR2
, 10);
115 clk
[firi_gate
] = imx_clk_gate2("firi_gate", "upll", base
+MXC_CCM_CGR2
, 12);
117 for (i
= 0; i
< ARRAY_SIZE(clk
); i
++)
119 pr_err("imx31 clk %d: register failed with %ld\n",
122 np
= of_find_compatible_node(NULL
, NULL
, "fsl,imx31-ccm");
126 clk_data
.clk_num
= ARRAY_SIZE(clk
);
127 of_clk_add_provider(np
, of_clk_src_onecell_get
, &clk_data
);
130 clk_register_clkdev(clk
[gpt_gate
], "per", "imx-gpt.0");
131 clk_register_clkdev(clk
[ipg
], "ipg", "imx-gpt.0");
132 clk_register_clkdev(clk
[cspi1_gate
], NULL
, "imx31-cspi.0");
133 clk_register_clkdev(clk
[cspi2_gate
], NULL
, "imx31-cspi.1");
134 clk_register_clkdev(clk
[cspi3_gate
], NULL
, "imx31-cspi.2");
135 clk_register_clkdev(clk
[pwm_gate
], "pwm", NULL
);
136 clk_register_clkdev(clk
[wdog_gate
], NULL
, "imx2-wdt.0");
137 clk_register_clkdev(clk
[rtc_gate
], NULL
, "imx21-rtc");
138 clk_register_clkdev(clk
[epit1_gate
], "epit", NULL
);
139 clk_register_clkdev(clk
[epit2_gate
], "epit", NULL
);
140 clk_register_clkdev(clk
[nfc
], NULL
, "imx27-nand.0");
141 clk_register_clkdev(clk
[ipu_gate
], NULL
, "ipu-core");
142 clk_register_clkdev(clk
[ipu_gate
], NULL
, "mx3_sdc_fb");
143 clk_register_clkdev(clk
[kpp_gate
], NULL
, "imx-keypad");
144 clk_register_clkdev(clk
[usb_div_post
], "per", "mxc-ehci.0");
145 clk_register_clkdev(clk
[usb_gate
], "ahb", "mxc-ehci.0");
146 clk_register_clkdev(clk
[ipg
], "ipg", "mxc-ehci.0");
147 clk_register_clkdev(clk
[usb_div_post
], "per", "mxc-ehci.1");
148 clk_register_clkdev(clk
[usb_gate
], "ahb", "mxc-ehci.1");
149 clk_register_clkdev(clk
[ipg
], "ipg", "mxc-ehci.1");
150 clk_register_clkdev(clk
[usb_div_post
], "per", "mxc-ehci.2");
151 clk_register_clkdev(clk
[usb_gate
], "ahb", "mxc-ehci.2");
152 clk_register_clkdev(clk
[ipg
], "ipg", "mxc-ehci.2");
153 clk_register_clkdev(clk
[usb_div_post
], "per", "imx-udc-mx27");
154 clk_register_clkdev(clk
[usb_gate
], "ahb", "imx-udc-mx27");
155 clk_register_clkdev(clk
[ipg
], "ipg", "imx-udc-mx27");
156 clk_register_clkdev(clk
[csi_gate
], NULL
, "mx3-camera.0");
157 /* i.mx31 has the i.mx21 type uart */
158 clk_register_clkdev(clk
[uart1_gate
], "per", "imx21-uart.0");
159 clk_register_clkdev(clk
[ipg
], "ipg", "imx21-uart.0");
160 clk_register_clkdev(clk
[uart2_gate
], "per", "imx21-uart.1");
161 clk_register_clkdev(clk
[ipg
], "ipg", "imx21-uart.1");
162 clk_register_clkdev(clk
[uart3_gate
], "per", "imx21-uart.2");
163 clk_register_clkdev(clk
[ipg
], "ipg", "imx21-uart.2");
164 clk_register_clkdev(clk
[uart4_gate
], "per", "imx21-uart.3");
165 clk_register_clkdev(clk
[ipg
], "ipg", "imx21-uart.3");
166 clk_register_clkdev(clk
[uart5_gate
], "per", "imx21-uart.4");
167 clk_register_clkdev(clk
[ipg
], "ipg", "imx21-uart.4");
168 clk_register_clkdev(clk
[i2c1_gate
], NULL
, "imx21-i2c.0");
169 clk_register_clkdev(clk
[i2c2_gate
], NULL
, "imx21-i2c.1");
170 clk_register_clkdev(clk
[i2c3_gate
], NULL
, "imx21-i2c.2");
171 clk_register_clkdev(clk
[owire_gate
], NULL
, "mxc_w1.0");
172 clk_register_clkdev(clk
[sdhc1_gate
], NULL
, "imx31-mmc.0");
173 clk_register_clkdev(clk
[sdhc2_gate
], NULL
, "imx31-mmc.1");
174 clk_register_clkdev(clk
[ssi1_gate
], NULL
, "imx-ssi.0");
175 clk_register_clkdev(clk
[ssi2_gate
], NULL
, "imx-ssi.1");
176 clk_register_clkdev(clk
[firi_gate
], "firi", NULL
);
177 clk_register_clkdev(clk
[ata_gate
], NULL
, "pata_imx");
178 clk_register_clkdev(clk
[rtic_gate
], "rtic", NULL
);
179 clk_register_clkdev(clk
[rng_gate
], NULL
, "mxc_rnga");
180 clk_register_clkdev(clk
[sdma_gate
], NULL
, "imx31-sdma");
181 clk_register_clkdev(clk
[iim_gate
], "iim", NULL
);
183 clk_set_parent(clk
[csi
], clk
[upll
]);
184 clk_prepare_enable(clk
[emi_gate
]);
185 clk_prepare_enable(clk
[iim_gate
]);
187 clk_disable_unprepare(clk
[iim_gate
]);
189 mxc_timer_init(MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR
), MX31_INT_GPT
);
194 int __init
mx31_clocks_init_dt(void)
196 struct device_node
*np
;
197 u32 fref
= 26000000; /* default */
199 for_each_compatible_node(np
, NULL
, "fixed-clock") {
200 if (!of_device_is_compatible(np
, "fsl,imx-osc26m"))
203 if (!of_property_read_u32(np
, "clock-frequency", &fref
))
207 return mx31_clocks_init(fref
);