2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/delay.h>
11 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/clk-provider.h>
15 #include <linux/err.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 #include <dt-bindings/clock/imx5-clock.h>
21 #include "crm-regs-imx5.h"
26 /* Low-power Audio Playback Mode clock */
27 static const char *lp_apm_sel
[] = { "osc", };
29 /* This is used multiple times */
30 static const char *standard_pll_sel
[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
31 static const char *periph_apm_sel
[] = { "pll1_sw", "pll3_sw", "lp_apm", };
32 static const char *main_bus_sel
[] = { "pll2_sw", "periph_apm", };
33 static const char *per_lp_apm_sel
[] = { "main_bus", "lp_apm", };
34 static const char *per_root_sel
[] = { "per_podf", "ipg", };
35 static const char *esdhc_c_sel
[] = { "esdhc_a_podf", "esdhc_b_podf", };
36 static const char *esdhc_d_sel
[] = { "esdhc_a_podf", "esdhc_b_podf", };
37 static const char *ssi_apm_sels
[] = { "ckih1", "lp_amp", "ckih2", };
38 static const char *ssi_clk_sels
[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
39 static const char *ssi3_clk_sels
[] = { "ssi1_root_gate", "ssi2_root_gate", };
40 static const char *ssi_ext1_com_sels
[] = { "ssi_ext1_podf", "ssi1_root_gate", };
41 static const char *ssi_ext2_com_sels
[] = { "ssi_ext2_podf", "ssi2_root_gate", };
42 static const char *emi_slow_sel
[] = { "main_bus", "ahb", };
43 static const char *usb_phy_sel_str
[] = { "osc", "usb_phy_podf", };
44 static const char *mx51_ipu_di0_sel
[] = { "di_pred", "osc", "ckih1", "tve_di", };
45 static const char *mx53_ipu_di0_sel
[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
46 static const char *mx53_ldb_di0_sel
[] = { "pll3_sw", "pll4_sw", };
47 static const char *mx51_ipu_di1_sel
[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
48 static const char *mx53_ipu_di1_sel
[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
49 static const char *mx53_ldb_di1_sel
[] = { "pll3_sw", "pll4_sw", };
50 static const char *mx51_tve_ext_sel
[] = { "osc", "ckih1", };
51 static const char *mx53_tve_ext_sel
[] = { "pll4_sw", "ckih1", };
52 static const char *mx51_tve_sel
[] = { "tve_pred", "tve_ext_sel", };
53 static const char *ipu_sel
[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
54 static const char *gpu3d_sel
[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
55 static const char *gpu2d_sel
[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
56 static const char *vpu_sel
[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
57 static const char *mx53_can_sel
[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
58 static const char *mx53_cko1_sel
[] = {
59 "cpu_podf", "pll1_sw", "pll2_sw", "pll3_sw",
60 "emi_slow_podf", "pll4_sw", "nfc_podf", "dummy",
61 "di_pred", "dummy", "dummy", "ahb",
62 "ipg", "per_root", "ckil", "dummy",};
63 static const char *mx53_cko2_sel
[] = {
64 "dummy"/* dptc_core */, "dummy"/* dptc_perich */,
65 "dummy", "esdhc_a_podf",
66 "usboh3_podf", "dummy"/* wrck_clk_root */,
67 "ecspi_podf", "dummy"/* pll1_ref_clk */,
68 "esdhc_b_podf", "dummy"/* ddr_clk_root */,
69 "dummy"/* arm_axi_clk_root */, "dummy"/* usb_phy_out */,
72 "dummy", "esdhc_c_sel",
73 "ssi1_root_podf", "ssi2_root_podf",
75 "dummy"/* lpsr_clk_root */, "dummy"/* pgc_clk_root */,
76 "dummy"/* tve_out */, "usb_phy_sel",
78 "uart_root", "dummy"/* spdif0_clk_root */,
80 static const char *mx51_spdif_xtal_sel
[] = { "osc", "ckih", "ckih2", };
81 static const char *mx53_spdif_xtal_sel
[] = { "osc", "ckih", "ckih2", "pll4_sw", };
82 static const char *spdif_sel
[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
83 static const char *spdif0_com_sel
[] = { "spdif0_podf", "ssi1_root_gate", };
84 static const char *mx51_spdif1_com_sel
[] = { "spdif1_podf", "ssi2_root_gate", };
86 static struct clk
*clk
[IMX5_CLK_END
];
87 static struct clk_onecell_data clk_data
;
89 static void __init
mx5_clocks_common_init(unsigned long rate_ckil
,
90 unsigned long rate_osc
, unsigned long rate_ckih1
,
91 unsigned long rate_ckih2
)
95 clk
[IMX5_CLK_DUMMY
] = imx_clk_fixed("dummy", 0);
96 clk
[IMX5_CLK_CKIL
] = imx_obtain_fixed_clock("ckil", rate_ckil
);
97 clk
[IMX5_CLK_OSC
] = imx_obtain_fixed_clock("osc", rate_osc
);
98 clk
[IMX5_CLK_CKIH1
] = imx_obtain_fixed_clock("ckih1", rate_ckih1
);
99 clk
[IMX5_CLK_CKIH2
] = imx_obtain_fixed_clock("ckih2", rate_ckih2
);
101 clk
[IMX5_CLK_PERIPH_APM
] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR
, 12, 2,
102 periph_apm_sel
, ARRAY_SIZE(periph_apm_sel
));
103 clk
[IMX5_CLK_MAIN_BUS
] = imx_clk_mux("main_bus", MXC_CCM_CBCDR
, 25, 1,
104 main_bus_sel
, ARRAY_SIZE(main_bus_sel
));
105 clk
[IMX5_CLK_PER_LP_APM
] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR
, 1, 1,
106 per_lp_apm_sel
, ARRAY_SIZE(per_lp_apm_sel
));
107 clk
[IMX5_CLK_PER_PRED1
] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR
, 6, 2);
108 clk
[IMX5_CLK_PER_PRED2
] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR
, 3, 3);
109 clk
[IMX5_CLK_PER_PODF
] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR
, 0, 3);
110 clk
[IMX5_CLK_PER_ROOT
] = imx_clk_mux("per_root", MXC_CCM_CBCMR
, 0, 1,
111 per_root_sel
, ARRAY_SIZE(per_root_sel
));
112 clk
[IMX5_CLK_AHB
] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR
, 10, 3);
113 clk
[IMX5_CLK_AHB_MAX
] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0
, 28);
114 clk
[IMX5_CLK_AIPS_TZ1
] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0
, 24);
115 clk
[IMX5_CLK_AIPS_TZ2
] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0
, 26);
116 clk
[IMX5_CLK_TMAX1
] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1
, 0);
117 clk
[IMX5_CLK_TMAX2
] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1
, 2);
118 clk
[IMX5_CLK_TMAX3
] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1
, 4);
119 clk
[IMX5_CLK_SPBA
] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5
, 0);
120 clk
[IMX5_CLK_IPG
] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR
, 8, 2);
121 clk
[IMX5_CLK_AXI_A
] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR
, 16, 3);
122 clk
[IMX5_CLK_AXI_B
] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR
, 19, 3);
123 clk
[IMX5_CLK_UART_SEL
] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1
, 24, 2,
124 standard_pll_sel
, ARRAY_SIZE(standard_pll_sel
));
125 clk
[IMX5_CLK_UART_PRED
] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1
, 3, 3);
126 clk
[IMX5_CLK_UART_ROOT
] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1
, 0, 3);
128 clk
[IMX5_CLK_ESDHC_A_SEL
] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1
, 20, 2,
129 standard_pll_sel
, ARRAY_SIZE(standard_pll_sel
));
130 clk
[IMX5_CLK_ESDHC_B_SEL
] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1
, 16, 2,
131 standard_pll_sel
, ARRAY_SIZE(standard_pll_sel
));
132 clk
[IMX5_CLK_ESDHC_A_PRED
] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1
, 16, 3);
133 clk
[IMX5_CLK_ESDHC_A_PODF
] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1
, 11, 3);
134 clk
[IMX5_CLK_ESDHC_B_PRED
] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1
, 22, 3);
135 clk
[IMX5_CLK_ESDHC_B_PODF
] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1
, 19, 3);
136 clk
[IMX5_CLK_ESDHC_C_SEL
] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1
, 19, 1, esdhc_c_sel
, ARRAY_SIZE(esdhc_c_sel
));
137 clk
[IMX5_CLK_ESDHC_D_SEL
] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1
, 18, 1, esdhc_d_sel
, ARRAY_SIZE(esdhc_d_sel
));
139 clk
[IMX5_CLK_EMI_SEL
] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR
, 26, 1,
140 emi_slow_sel
, ARRAY_SIZE(emi_slow_sel
));
141 clk
[IMX5_CLK_EMI_SLOW_PODF
] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR
, 22, 3);
142 clk
[IMX5_CLK_NFC_PODF
] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR
, 13, 3);
143 clk
[IMX5_CLK_ECSPI_SEL
] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1
, 4, 2,
144 standard_pll_sel
, ARRAY_SIZE(standard_pll_sel
));
145 clk
[IMX5_CLK_ECSPI_PRED
] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2
, 25, 3);
146 clk
[IMX5_CLK_ECSPI_PODF
] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2
, 19, 6);
147 clk
[IMX5_CLK_USBOH3_SEL
] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1
, 22, 2,
148 standard_pll_sel
, ARRAY_SIZE(standard_pll_sel
));
149 clk
[IMX5_CLK_USBOH3_PRED
] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1
, 8, 3);
150 clk
[IMX5_CLK_USBOH3_PODF
] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1
, 6, 2);
151 clk
[IMX5_CLK_USB_PHY_PRED
] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR
, 3, 3);
152 clk
[IMX5_CLK_USB_PHY_PODF
] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR
, 0, 3);
153 clk
[IMX5_CLK_USB_PHY_SEL
] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1
, 26, 1,
154 usb_phy_sel_str
, ARRAY_SIZE(usb_phy_sel_str
));
155 clk
[IMX5_CLK_CPU_PODF
] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR
, 0, 3);
156 clk
[IMX5_CLK_DI_PRED
] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR
, 6, 3);
157 clk
[IMX5_CLK_IIM_GATE
] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0
, 30);
158 clk
[IMX5_CLK_UART1_IPG_GATE
] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1
, 6);
159 clk
[IMX5_CLK_UART1_PER_GATE
] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1
, 8);
160 clk
[IMX5_CLK_UART2_IPG_GATE
] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1
, 10);
161 clk
[IMX5_CLK_UART2_PER_GATE
] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1
, 12);
162 clk
[IMX5_CLK_UART3_IPG_GATE
] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1
, 14);
163 clk
[IMX5_CLK_UART3_PER_GATE
] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1
, 16);
164 clk
[IMX5_CLK_I2C1_GATE
] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1
, 18);
165 clk
[IMX5_CLK_I2C2_GATE
] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1
, 20);
166 clk
[IMX5_CLK_PWM1_IPG_GATE
] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2
, 10);
167 clk
[IMX5_CLK_PWM1_HF_GATE
] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2
, 12);
168 clk
[IMX5_CLK_PWM2_IPG_GATE
] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2
, 14);
169 clk
[IMX5_CLK_PWM2_HF_GATE
] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2
, 16);
170 clk
[IMX5_CLK_GPT_IPG_GATE
] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2
, 18);
171 clk
[IMX5_CLK_GPT_HF_GATE
] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2
, 20);
172 clk
[IMX5_CLK_FEC_GATE
] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2
, 24);
173 clk
[IMX5_CLK_USBOH3_GATE
] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2
, 26);
174 clk
[IMX5_CLK_USBOH3_PER_GATE
] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2
, 28);
175 clk
[IMX5_CLK_ESDHC1_IPG_GATE
] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3
, 0);
176 clk
[IMX5_CLK_ESDHC2_IPG_GATE
] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3
, 4);
177 clk
[IMX5_CLK_ESDHC3_IPG_GATE
] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3
, 8);
178 clk
[IMX5_CLK_ESDHC4_IPG_GATE
] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3
, 12);
179 clk
[IMX5_CLK_SSI1_IPG_GATE
] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3
, 16);
180 clk
[IMX5_CLK_SSI2_IPG_GATE
] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3
, 20);
181 clk
[IMX5_CLK_SSI3_IPG_GATE
] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3
, 24);
182 clk
[IMX5_CLK_ECSPI1_IPG_GATE
] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4
, 18);
183 clk
[IMX5_CLK_ECSPI1_PER_GATE
] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4
, 20);
184 clk
[IMX5_CLK_ECSPI2_IPG_GATE
] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4
, 22);
185 clk
[IMX5_CLK_ECSPI2_PER_GATE
] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4
, 24);
186 clk
[IMX5_CLK_CSPI_IPG_GATE
] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4
, 26);
187 clk
[IMX5_CLK_SDMA_GATE
] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4
, 30);
188 clk
[IMX5_CLK_EMI_FAST_GATE
] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5
, 14);
189 clk
[IMX5_CLK_EMI_SLOW_GATE
] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5
, 16);
190 clk
[IMX5_CLK_IPU_SEL
] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR
, 6, 2, ipu_sel
, ARRAY_SIZE(ipu_sel
));
191 clk
[IMX5_CLK_IPU_GATE
] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5
, 10);
192 clk
[IMX5_CLK_NFC_GATE
] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5
, 20);
193 clk
[IMX5_CLK_IPU_DI0_GATE
] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6
, 10);
194 clk
[IMX5_CLK_IPU_DI1_GATE
] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6
, 12);
195 clk
[IMX5_CLK_GPU3D_SEL
] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR
, 4, 2, gpu3d_sel
, ARRAY_SIZE(gpu3d_sel
));
196 clk
[IMX5_CLK_GPU2D_SEL
] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR
, 16, 2, gpu2d_sel
, ARRAY_SIZE(gpu2d_sel
));
197 clk
[IMX5_CLK_GPU3D_GATE
] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5
, 2);
198 clk
[IMX5_CLK_GARB_GATE
] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5
, 4);
199 clk
[IMX5_CLK_GPU2D_GATE
] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6
, 14);
200 clk
[IMX5_CLK_VPU_SEL
] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR
, 14, 2, vpu_sel
, ARRAY_SIZE(vpu_sel
));
201 clk
[IMX5_CLK_VPU_GATE
] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5
, 6);
202 clk
[IMX5_CLK_VPU_REFERENCE_GATE
] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5
, 8);
203 clk
[IMX5_CLK_UART4_IPG_GATE
] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7
, 8);
204 clk
[IMX5_CLK_UART4_PER_GATE
] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7
, 10);
205 clk
[IMX5_CLK_UART5_IPG_GATE
] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7
, 12);
206 clk
[IMX5_CLK_UART5_PER_GATE
] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7
, 14);
207 clk
[IMX5_CLK_GPC_DVFS
] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5
, 24);
209 clk
[IMX5_CLK_SSI_APM
] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1
, 8, 2, ssi_apm_sels
, ARRAY_SIZE(ssi_apm_sels
));
210 clk
[IMX5_CLK_SSI1_ROOT_SEL
] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1
, 14, 2, ssi_clk_sels
, ARRAY_SIZE(ssi_clk_sels
));
211 clk
[IMX5_CLK_SSI2_ROOT_SEL
] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1
, 12, 2, ssi_clk_sels
, ARRAY_SIZE(ssi_clk_sels
));
212 clk
[IMX5_CLK_SSI3_ROOT_SEL
] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1
, 11, 1, ssi3_clk_sels
, ARRAY_SIZE(ssi3_clk_sels
));
213 clk
[IMX5_CLK_SSI_EXT1_SEL
] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1
, 28, 2, ssi_clk_sels
, ARRAY_SIZE(ssi_clk_sels
));
214 clk
[IMX5_CLK_SSI_EXT2_SEL
] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1
, 30, 2, ssi_clk_sels
, ARRAY_SIZE(ssi_clk_sels
));
215 clk
[IMX5_CLK_SSI_EXT1_COM_SEL
] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1
, 0, 1, ssi_ext1_com_sels
, ARRAY_SIZE(ssi_ext1_com_sels
));
216 clk
[IMX5_CLK_SSI_EXT2_COM_SEL
] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1
, 1, 1, ssi_ext2_com_sels
, ARRAY_SIZE(ssi_ext2_com_sels
));
217 clk
[IMX5_CLK_SSI1_ROOT_PRED
] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR
, 6, 3);
218 clk
[IMX5_CLK_SSI1_ROOT_PODF
] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR
, 0, 6);
219 clk
[IMX5_CLK_SSI2_ROOT_PRED
] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR
, 6, 3);
220 clk
[IMX5_CLK_SSI2_ROOT_PODF
] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR
, 0, 6);
221 clk
[IMX5_CLK_SSI_EXT1_PRED
] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR
, 22, 3);
222 clk
[IMX5_CLK_SSI_EXT1_PODF
] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR
, 16, 6);
223 clk
[IMX5_CLK_SSI_EXT2_PRED
] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR
, 22, 3);
224 clk
[IMX5_CLK_SSI_EXT2_PODF
] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR
, 16, 6);
225 clk
[IMX5_CLK_SSI1_ROOT_GATE
] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3
, 18);
226 clk
[IMX5_CLK_SSI2_ROOT_GATE
] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3
, 22);
227 clk
[IMX5_CLK_SSI3_ROOT_GATE
] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3
, 26);
228 clk
[IMX5_CLK_SSI_EXT1_GATE
] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3
, 28);
229 clk
[IMX5_CLK_SSI_EXT2_GATE
] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3
, 30);
230 clk
[IMX5_CLK_EPIT1_IPG_GATE
] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2
, 2);
231 clk
[IMX5_CLK_EPIT1_HF_GATE
] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2
, 4);
232 clk
[IMX5_CLK_EPIT2_IPG_GATE
] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2
, 6);
233 clk
[IMX5_CLK_EPIT2_HF_GATE
] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2
, 8);
234 clk
[IMX5_CLK_OWIRE_GATE
] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2
, 22);
235 clk
[IMX5_CLK_SRTC_GATE
] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4
, 28);
236 clk
[IMX5_CLK_PATA_GATE
] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4
, 0);
237 clk
[IMX5_CLK_SPDIF0_SEL
] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2
, 0, 2, spdif_sel
, ARRAY_SIZE(spdif_sel
));
238 clk
[IMX5_CLK_SPDIF0_PRED
] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR
, 25, 3);
239 clk
[IMX5_CLK_SPDIF0_PODF
] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR
, 19, 6);
240 clk
[IMX5_CLK_SPDIF0_COM_SEL
] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2
, 4, 1,
241 spdif0_com_sel
, ARRAY_SIZE(spdif0_com_sel
), CLK_SET_RATE_PARENT
);
242 clk
[IMX5_CLK_SPDIF0_GATE
] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5
, 26);
243 clk
[IMX5_CLK_SPDIF_IPG_GATE
] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5
, 30);
244 clk
[IMX5_CLK_SAHARA_IPG_GATE
] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4
, 14);
245 clk
[IMX5_CLK_SATA_REF
] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
247 for (i
= 0; i
< ARRAY_SIZE(clk
); i
++)
249 pr_err("i.MX5 clk %d: register failed with %ld\n",
252 clk_register_clkdev(clk
[IMX5_CLK_GPT_HF_GATE
], "per", "imx-gpt.0");
253 clk_register_clkdev(clk
[IMX5_CLK_GPT_IPG_GATE
], "ipg", "imx-gpt.0");
254 clk_register_clkdev(clk
[IMX5_CLK_UART1_PER_GATE
], "per", "imx21-uart.0");
255 clk_register_clkdev(clk
[IMX5_CLK_UART1_IPG_GATE
], "ipg", "imx21-uart.0");
256 clk_register_clkdev(clk
[IMX5_CLK_UART2_PER_GATE
], "per", "imx21-uart.1");
257 clk_register_clkdev(clk
[IMX5_CLK_UART2_IPG_GATE
], "ipg", "imx21-uart.1");
258 clk_register_clkdev(clk
[IMX5_CLK_UART3_PER_GATE
], "per", "imx21-uart.2");
259 clk_register_clkdev(clk
[IMX5_CLK_UART3_IPG_GATE
], "ipg", "imx21-uart.2");
260 clk_register_clkdev(clk
[IMX5_CLK_UART4_PER_GATE
], "per", "imx21-uart.3");
261 clk_register_clkdev(clk
[IMX5_CLK_UART4_IPG_GATE
], "ipg", "imx21-uart.3");
262 clk_register_clkdev(clk
[IMX5_CLK_UART5_PER_GATE
], "per", "imx21-uart.4");
263 clk_register_clkdev(clk
[IMX5_CLK_UART5_IPG_GATE
], "ipg", "imx21-uart.4");
264 clk_register_clkdev(clk
[IMX5_CLK_ECSPI1_PER_GATE
], "per", "imx51-ecspi.0");
265 clk_register_clkdev(clk
[IMX5_CLK_ECSPI1_IPG_GATE
], "ipg", "imx51-ecspi.0");
266 clk_register_clkdev(clk
[IMX5_CLK_ECSPI2_PER_GATE
], "per", "imx51-ecspi.1");
267 clk_register_clkdev(clk
[IMX5_CLK_ECSPI2_IPG_GATE
], "ipg", "imx51-ecspi.1");
268 clk_register_clkdev(clk
[IMX5_CLK_CSPI_IPG_GATE
], NULL
, "imx35-cspi.2");
269 clk_register_clkdev(clk
[IMX5_CLK_I2C1_GATE
], NULL
, "imx21-i2c.0");
270 clk_register_clkdev(clk
[IMX5_CLK_I2C2_GATE
], NULL
, "imx21-i2c.1");
271 clk_register_clkdev(clk
[IMX5_CLK_USBOH3_PER_GATE
], "per", "mxc-ehci.0");
272 clk_register_clkdev(clk
[IMX5_CLK_USBOH3_GATE
], "ipg", "mxc-ehci.0");
273 clk_register_clkdev(clk
[IMX5_CLK_USBOH3_GATE
], "ahb", "mxc-ehci.0");
274 clk_register_clkdev(clk
[IMX5_CLK_USBOH3_PER_GATE
], "per", "mxc-ehci.1");
275 clk_register_clkdev(clk
[IMX5_CLK_USBOH3_GATE
], "ipg", "mxc-ehci.1");
276 clk_register_clkdev(clk
[IMX5_CLK_USBOH3_GATE
], "ahb", "mxc-ehci.1");
277 clk_register_clkdev(clk
[IMX5_CLK_USBOH3_PER_GATE
], "per", "mxc-ehci.2");
278 clk_register_clkdev(clk
[IMX5_CLK_USBOH3_GATE
], "ipg", "mxc-ehci.2");
279 clk_register_clkdev(clk
[IMX5_CLK_USBOH3_GATE
], "ahb", "mxc-ehci.2");
280 clk_register_clkdev(clk
[IMX5_CLK_USBOH3_PER_GATE
], "per", "imx-udc-mx51");
281 clk_register_clkdev(clk
[IMX5_CLK_USBOH3_GATE
], "ipg", "imx-udc-mx51");
282 clk_register_clkdev(clk
[IMX5_CLK_USBOH3_GATE
], "ahb", "imx-udc-mx51");
283 clk_register_clkdev(clk
[IMX5_CLK_NFC_GATE
], NULL
, "imx51-nand");
284 clk_register_clkdev(clk
[IMX5_CLK_SSI1_IPG_GATE
], NULL
, "imx-ssi.0");
285 clk_register_clkdev(clk
[IMX5_CLK_SSI2_IPG_GATE
], NULL
, "imx-ssi.1");
286 clk_register_clkdev(clk
[IMX5_CLK_SSI3_IPG_GATE
], NULL
, "imx-ssi.2");
287 clk_register_clkdev(clk
[IMX5_CLK_SDMA_GATE
], NULL
, "imx35-sdma");
288 clk_register_clkdev(clk
[IMX5_CLK_CPU_PODF
], NULL
, "cpu0");
289 clk_register_clkdev(clk
[IMX5_CLK_IIM_GATE
], "iim", NULL
);
290 clk_register_clkdev(clk
[IMX5_CLK_DUMMY
], NULL
, "imx2-wdt.0");
291 clk_register_clkdev(clk
[IMX5_CLK_DUMMY
], NULL
, "imx2-wdt.1");
292 clk_register_clkdev(clk
[IMX5_CLK_DUMMY
], NULL
, "imx-keypad");
293 clk_register_clkdev(clk
[IMX5_CLK_IPU_DI1_GATE
], "di1", "imx-tve.0");
294 clk_register_clkdev(clk
[IMX5_CLK_GPC_DVFS
], "gpc_dvfs", NULL
);
295 clk_register_clkdev(clk
[IMX5_CLK_EPIT1_IPG_GATE
], "ipg", "imx-epit.0");
296 clk_register_clkdev(clk
[IMX5_CLK_EPIT1_HF_GATE
], "per", "imx-epit.0");
297 clk_register_clkdev(clk
[IMX5_CLK_EPIT2_IPG_GATE
], "ipg", "imx-epit.1");
298 clk_register_clkdev(clk
[IMX5_CLK_EPIT2_HF_GATE
], "per", "imx-epit.1");
300 /* Set SDHC parents to be PLL2 */
301 clk_set_parent(clk
[IMX5_CLK_ESDHC_A_SEL
], clk
[IMX5_CLK_PLL2_SW
]);
302 clk_set_parent(clk
[IMX5_CLK_ESDHC_B_SEL
], clk
[IMX5_CLK_PLL2_SW
]);
304 /* move usb phy clk to 24MHz */
305 clk_set_parent(clk
[IMX5_CLK_USB_PHY_SEL
], clk
[IMX5_CLK_OSC
]);
307 clk_prepare_enable(clk
[IMX5_CLK_GPC_DVFS
]);
308 clk_prepare_enable(clk
[IMX5_CLK_AHB_MAX
]); /* esdhc3 */
309 clk_prepare_enable(clk
[IMX5_CLK_AIPS_TZ1
]);
310 clk_prepare_enable(clk
[IMX5_CLK_AIPS_TZ2
]); /* fec */
311 clk_prepare_enable(clk
[IMX5_CLK_SPBA
]);
312 clk_prepare_enable(clk
[IMX5_CLK_EMI_FAST_GATE
]); /* fec */
313 clk_prepare_enable(clk
[IMX5_CLK_EMI_SLOW_GATE
]); /* eim */
314 clk_prepare_enable(clk
[IMX5_CLK_MIPI_HSC1_GATE
]);
315 clk_prepare_enable(clk
[IMX5_CLK_MIPI_HSC2_GATE
]);
316 clk_prepare_enable(clk
[IMX5_CLK_MIPI_ESC_GATE
]);
317 clk_prepare_enable(clk
[IMX5_CLK_MIPI_HSP_GATE
]);
318 clk_prepare_enable(clk
[IMX5_CLK_TMAX1
]);
319 clk_prepare_enable(clk
[IMX5_CLK_TMAX2
]); /* esdhc2, fec */
320 clk_prepare_enable(clk
[IMX5_CLK_TMAX3
]); /* esdhc1, esdhc4 */
323 static void __init
mx50_clocks_init(struct device_node
*np
)
328 clk
[IMX5_CLK_PLL1_SW
] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE
);
329 clk
[IMX5_CLK_PLL2_SW
] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE
);
330 clk
[IMX5_CLK_PLL3_SW
] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE
);
332 clk
[IMX5_CLK_LP_APM
] = imx_clk_mux("lp_apm", MXC_CCM_CCSR
, 10, 1,
333 lp_apm_sel
, ARRAY_SIZE(lp_apm_sel
));
334 clk
[IMX5_CLK_ESDHC1_PER_GATE
] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3
, 2);
335 clk
[IMX5_CLK_ESDHC2_PER_GATE
] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3
, 6);
336 clk
[IMX5_CLK_ESDHC3_PER_GATE
] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3
, 10);
337 clk
[IMX5_CLK_ESDHC4_PER_GATE
] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3
, 14);
338 clk
[IMX5_CLK_USB_PHY1_GATE
] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4
, 10);
339 clk
[IMX5_CLK_USB_PHY2_GATE
] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4
, 12);
340 clk
[IMX5_CLK_I2C3_GATE
] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1
, 22);
342 clk
[IMX5_CLK_CKO1_SEL
] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR
, 0, 4,
343 mx53_cko1_sel
, ARRAY_SIZE(mx53_cko1_sel
));
344 clk
[IMX5_CLK_CKO1_PODF
] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR
, 4, 3);
345 clk
[IMX5_CLK_CKO1
] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR
, 7);
347 clk
[IMX5_CLK_CKO2_SEL
] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR
, 16, 5,
348 mx53_cko2_sel
, ARRAY_SIZE(mx53_cko2_sel
));
349 clk
[IMX5_CLK_CKO2_PODF
] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR
, 21, 3);
350 clk
[IMX5_CLK_CKO2
] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR
, 24);
352 for (i
= 0; i
< ARRAY_SIZE(clk
); i
++)
354 pr_err("i.MX50 clk %d: register failed with %ld\n",
358 clk_data
.clk_num
= ARRAY_SIZE(clk
);
359 of_clk_add_provider(np
, of_clk_src_onecell_get
, &clk_data
);
361 mx5_clocks_common_init(0, 0, 0, 0);
363 /* set SDHC root clock to 200MHZ*/
364 clk_set_rate(clk
[IMX5_CLK_ESDHC_A_PODF
], 200000000);
365 clk_set_rate(clk
[IMX5_CLK_ESDHC_B_PODF
], 200000000);
367 clk_prepare_enable(clk
[IMX5_CLK_IIM_GATE
]);
368 imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1
);
369 clk_disable_unprepare(clk
[IMX5_CLK_IIM_GATE
]);
371 r
= clk_round_rate(clk
[IMX5_CLK_USBOH3_PER_GATE
], 54000000);
372 clk_set_rate(clk
[IMX5_CLK_USBOH3_PER_GATE
], r
);
374 mxc_timer_init_dt(of_find_compatible_node(NULL
, NULL
, "fsl,imx50-gpt"));
376 CLK_OF_DECLARE(imx50_ccm
, "fsl,imx50-ccm", mx50_clocks_init
);
378 int __init
mx51_clocks_init(unsigned long rate_ckil
, unsigned long rate_osc
,
379 unsigned long rate_ckih1
, unsigned long rate_ckih2
)
383 struct device_node
*np
;
385 clk
[IMX5_CLK_PLL1_SW
] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE
);
386 clk
[IMX5_CLK_PLL2_SW
] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE
);
387 clk
[IMX5_CLK_PLL3_SW
] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE
);
388 clk
[IMX5_CLK_LP_APM
] = imx_clk_mux("lp_apm", MXC_CCM_CCSR
, 9, 1,
389 lp_apm_sel
, ARRAY_SIZE(lp_apm_sel
));
390 clk
[IMX5_CLK_IPU_DI0_SEL
] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2
, 26, 3,
391 mx51_ipu_di0_sel
, ARRAY_SIZE(mx51_ipu_di0_sel
));
392 clk
[IMX5_CLK_IPU_DI1_SEL
] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2
, 29, 3,
393 mx51_ipu_di1_sel
, ARRAY_SIZE(mx51_ipu_di1_sel
));
394 clk
[IMX5_CLK_TVE_EXT_SEL
] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1
, 6, 1,
395 mx51_tve_ext_sel
, ARRAY_SIZE(mx51_tve_ext_sel
), CLK_SET_RATE_PARENT
);
396 clk
[IMX5_CLK_TVE_SEL
] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1
, 7, 1,
397 mx51_tve_sel
, ARRAY_SIZE(mx51_tve_sel
));
398 clk
[IMX5_CLK_TVE_GATE
] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2
, 30);
399 clk
[IMX5_CLK_TVE_PRED
] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR
, 28, 3);
400 clk
[IMX5_CLK_ESDHC1_PER_GATE
] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3
, 2);
401 clk
[IMX5_CLK_ESDHC2_PER_GATE
] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3
, 6);
402 clk
[IMX5_CLK_ESDHC3_PER_GATE
] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3
, 10);
403 clk
[IMX5_CLK_ESDHC4_PER_GATE
] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3
, 14);
404 clk
[IMX5_CLK_USB_PHY_GATE
] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2
, 0);
405 clk
[IMX5_CLK_HSI2C_GATE
] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1
, 22);
406 clk
[IMX5_CLK_MIPI_HSC1_GATE
] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4
, 6);
407 clk
[IMX5_CLK_MIPI_HSC2_GATE
] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4
, 8);
408 clk
[IMX5_CLK_MIPI_ESC_GATE
] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4
, 10);
409 clk
[IMX5_CLK_MIPI_HSP_GATE
] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4
, 12);
410 clk
[IMX5_CLK_SPDIF_XTAL_SEL
] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1
, 2, 2,
411 mx51_spdif_xtal_sel
, ARRAY_SIZE(mx51_spdif_xtal_sel
));
412 clk
[IMX5_CLK_SPDIF1_SEL
] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2
, 2, 2,
413 spdif_sel
, ARRAY_SIZE(spdif_sel
));
414 clk
[IMX5_CLK_SPDIF1_PRED
] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR
, 16, 3);
415 clk
[IMX5_CLK_SPDIF1_PODF
] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR
, 9, 6);
416 clk
[IMX5_CLK_SPDIF1_COM_SEL
] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2
, 5, 1,
417 mx51_spdif1_com_sel
, ARRAY_SIZE(mx51_spdif1_com_sel
));
418 clk
[IMX5_CLK_SPDIF1_GATE
] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5
, 28);
420 for (i
= 0; i
< ARRAY_SIZE(clk
); i
++)
422 pr_err("i.MX51 clk %d: register failed with %ld\n",
425 np
= of_find_compatible_node(NULL
, NULL
, "fsl,imx51-ccm");
427 clk_data
.clk_num
= ARRAY_SIZE(clk
);
428 of_clk_add_provider(np
, of_clk_src_onecell_get
, &clk_data
);
430 mx5_clocks_common_init(rate_ckil
, rate_osc
, rate_ckih1
, rate_ckih2
);
432 clk_register_clkdev(clk
[IMX5_CLK_HSI2C_GATE
], NULL
, "imx21-i2c.2");
433 clk_register_clkdev(clk
[IMX5_CLK_MX51_MIPI
], "mipi_hsp", NULL
);
434 clk_register_clkdev(clk
[IMX5_CLK_FEC_GATE
], NULL
, "imx27-fec.0");
435 clk_register_clkdev(clk
[IMX5_CLK_USB_PHY_GATE
], "phy", "mxc-ehci.0");
436 clk_register_clkdev(clk
[IMX5_CLK_ESDHC1_IPG_GATE
], "ipg", "sdhci-esdhc-imx51.0");
437 clk_register_clkdev(clk
[IMX5_CLK_DUMMY
], "ahb", "sdhci-esdhc-imx51.0");
438 clk_register_clkdev(clk
[IMX5_CLK_ESDHC1_PER_GATE
], "per", "sdhci-esdhc-imx51.0");
439 clk_register_clkdev(clk
[IMX5_CLK_ESDHC2_IPG_GATE
], "ipg", "sdhci-esdhc-imx51.1");
440 clk_register_clkdev(clk
[IMX5_CLK_DUMMY
], "ahb", "sdhci-esdhc-imx51.1");
441 clk_register_clkdev(clk
[IMX5_CLK_ESDHC2_PER_GATE
], "per", "sdhci-esdhc-imx51.1");
442 clk_register_clkdev(clk
[IMX5_CLK_ESDHC3_IPG_GATE
], "ipg", "sdhci-esdhc-imx51.2");
443 clk_register_clkdev(clk
[IMX5_CLK_DUMMY
], "ahb", "sdhci-esdhc-imx51.2");
444 clk_register_clkdev(clk
[IMX5_CLK_ESDHC3_PER_GATE
], "per", "sdhci-esdhc-imx51.2");
445 clk_register_clkdev(clk
[IMX5_CLK_ESDHC4_IPG_GATE
], "ipg", "sdhci-esdhc-imx51.3");
446 clk_register_clkdev(clk
[IMX5_CLK_DUMMY
], "ahb", "sdhci-esdhc-imx51.3");
447 clk_register_clkdev(clk
[IMX5_CLK_ESDHC4_PER_GATE
], "per", "sdhci-esdhc-imx51.3");
449 /* set the usboh3 parent to pll2_sw */
450 clk_set_parent(clk
[IMX5_CLK_USBOH3_SEL
], clk
[IMX5_CLK_PLL2_SW
]);
452 /* set SDHC root clock to 166.25MHZ*/
453 clk_set_rate(clk
[IMX5_CLK_ESDHC_A_PODF
], 166250000);
454 clk_set_rate(clk
[IMX5_CLK_ESDHC_B_PODF
], 166250000);
457 mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR
), MX51_INT_GPT
);
459 clk_prepare_enable(clk
[IMX5_CLK_IIM_GATE
]);
460 imx_print_silicon_rev("i.MX51", mx51_revision());
461 clk_disable_unprepare(clk
[IMX5_CLK_IIM_GATE
]);
464 * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
465 * longer supported. Set to one for better power saving.
467 * The effect of not setting these bits is that MIPI clocks can't be
468 * enabled without the IPU clock being enabled aswell.
470 val
= readl(MXC_CCM_CCDR
);
472 writel(val
, MXC_CCM_CCDR
);
474 val
= readl(MXC_CCM_CLPCR
);
476 writel(val
, MXC_CCM_CLPCR
);
481 static void __init
mx51_clocks_init_dt(struct device_node
*np
)
483 mx51_clocks_init(0, 0, 0, 0);
485 CLK_OF_DECLARE(imx51_ccm
, "fsl,imx51-ccm", mx51_clocks_init_dt
);
487 static void __init
mx53_clocks_init(struct device_node
*np
)
492 clk
[IMX5_CLK_PLL1_SW
] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE
);
493 clk
[IMX5_CLK_PLL2_SW
] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE
);
494 clk
[IMX5_CLK_PLL3_SW
] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE
);
495 clk
[IMX5_CLK_PLL4_SW
] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE
);
497 clk
[IMX5_CLK_LP_APM
] = imx_clk_mux("lp_apm", MXC_CCM_CCSR
, 10, 1,
498 lp_apm_sel
, ARRAY_SIZE(lp_apm_sel
));
499 clk
[IMX5_CLK_LDB_DI1_DIV_3_5
] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
500 clk
[IMX5_CLK_LDB_DI1_DIV
] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2
, 11, 1, 0);
501 clk
[IMX5_CLK_LDB_DI1_SEL
] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2
, 9, 1,
502 mx53_ldb_di1_sel
, ARRAY_SIZE(mx53_ldb_di1_sel
), CLK_SET_RATE_PARENT
);
503 clk
[IMX5_CLK_DI_PLL4_PODF
] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR
, 16, 3);
504 clk
[IMX5_CLK_LDB_DI0_DIV_3_5
] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
505 clk
[IMX5_CLK_LDB_DI0_DIV
] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2
, 10, 1, 0);
506 clk
[IMX5_CLK_LDB_DI0_SEL
] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2
, 8, 1,
507 mx53_ldb_di0_sel
, ARRAY_SIZE(mx53_ldb_di0_sel
), CLK_SET_RATE_PARENT
);
508 clk
[IMX5_CLK_LDB_DI0_GATE
] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6
, 28);
509 clk
[IMX5_CLK_LDB_DI1_GATE
] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6
, 30);
510 clk
[IMX5_CLK_IPU_DI0_SEL
] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2
, 26, 3,
511 mx53_ipu_di0_sel
, ARRAY_SIZE(mx53_ipu_di0_sel
));
512 clk
[IMX5_CLK_IPU_DI1_SEL
] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2
, 29, 3,
513 mx53_ipu_di1_sel
, ARRAY_SIZE(mx53_ipu_di1_sel
));
514 clk
[IMX5_CLK_TVE_EXT_SEL
] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1
, 6, 1,
515 mx53_tve_ext_sel
, ARRAY_SIZE(mx53_tve_ext_sel
), CLK_SET_RATE_PARENT
);
516 clk
[IMX5_CLK_TVE_GATE
] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2
, 30);
517 clk
[IMX5_CLK_TVE_PRED
] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR
, 28, 3);
518 clk
[IMX5_CLK_ESDHC1_PER_GATE
] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3
, 2);
519 clk
[IMX5_CLK_ESDHC2_PER_GATE
] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3
, 6);
520 clk
[IMX5_CLK_ESDHC3_PER_GATE
] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3
, 10);
521 clk
[IMX5_CLK_ESDHC4_PER_GATE
] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3
, 14);
522 clk
[IMX5_CLK_USB_PHY1_GATE
] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4
, 10);
523 clk
[IMX5_CLK_USB_PHY2_GATE
] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4
, 12);
524 clk
[IMX5_CLK_CAN_SEL
] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2
, 6, 2,
525 mx53_can_sel
, ARRAY_SIZE(mx53_can_sel
));
526 clk
[IMX5_CLK_CAN1_SERIAL_GATE
] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6
, 22);
527 clk
[IMX5_CLK_CAN1_IPG_GATE
] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6
, 20);
528 clk
[IMX5_CLK_OCRAM
] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6
, 2);
529 clk
[IMX5_CLK_CAN2_SERIAL_GATE
] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4
, 8);
530 clk
[IMX5_CLK_CAN2_IPG_GATE
] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4
, 6);
531 clk
[IMX5_CLK_I2C3_GATE
] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1
, 22);
532 clk
[IMX5_CLK_SATA_GATE
] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4
, 2);
534 clk
[IMX5_CLK_CKO1_SEL
] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR
, 0, 4,
535 mx53_cko1_sel
, ARRAY_SIZE(mx53_cko1_sel
));
536 clk
[IMX5_CLK_CKO1_PODF
] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR
, 4, 3);
537 clk
[IMX5_CLK_CKO1
] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR
, 7);
539 clk
[IMX5_CLK_CKO2_SEL
] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR
, 16, 5,
540 mx53_cko2_sel
, ARRAY_SIZE(mx53_cko2_sel
));
541 clk
[IMX5_CLK_CKO2_PODF
] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR
, 21, 3);
542 clk
[IMX5_CLK_CKO2
] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR
, 24);
543 clk
[IMX5_CLK_SPDIF_XTAL_SEL
] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1
, 2, 2,
544 mx53_spdif_xtal_sel
, ARRAY_SIZE(mx53_spdif_xtal_sel
));
546 for (i
= 0; i
< ARRAY_SIZE(clk
); i
++)
548 pr_err("i.MX53 clk %d: register failed with %ld\n",
552 clk_data
.clk_num
= ARRAY_SIZE(clk
);
553 of_clk_add_provider(np
, of_clk_src_onecell_get
, &clk_data
);
555 mx5_clocks_common_init(0, 0, 0, 0);
557 clk_register_clkdev(clk
[IMX5_CLK_I2C3_GATE
], NULL
, "imx21-i2c.2");
558 clk_register_clkdev(clk
[IMX5_CLK_FEC_GATE
], NULL
, "imx25-fec.0");
559 clk_register_clkdev(clk
[IMX5_CLK_USB_PHY1_GATE
], "usb_phy1", "mxc-ehci.0");
560 clk_register_clkdev(clk
[IMX5_CLK_ESDHC1_IPG_GATE
], "ipg", "sdhci-esdhc-imx53.0");
561 clk_register_clkdev(clk
[IMX5_CLK_DUMMY
], "ahb", "sdhci-esdhc-imx53.0");
562 clk_register_clkdev(clk
[IMX5_CLK_ESDHC1_PER_GATE
], "per", "sdhci-esdhc-imx53.0");
563 clk_register_clkdev(clk
[IMX5_CLK_ESDHC2_IPG_GATE
], "ipg", "sdhci-esdhc-imx53.1");
564 clk_register_clkdev(clk
[IMX5_CLK_DUMMY
], "ahb", "sdhci-esdhc-imx53.1");
565 clk_register_clkdev(clk
[IMX5_CLK_ESDHC2_PER_GATE
], "per", "sdhci-esdhc-imx53.1");
566 clk_register_clkdev(clk
[IMX5_CLK_ESDHC3_IPG_GATE
], "ipg", "sdhci-esdhc-imx53.2");
567 clk_register_clkdev(clk
[IMX5_CLK_DUMMY
], "ahb", "sdhci-esdhc-imx53.2");
568 clk_register_clkdev(clk
[IMX5_CLK_ESDHC3_PER_GATE
], "per", "sdhci-esdhc-imx53.2");
569 clk_register_clkdev(clk
[IMX5_CLK_ESDHC4_IPG_GATE
], "ipg", "sdhci-esdhc-imx53.3");
570 clk_register_clkdev(clk
[IMX5_CLK_DUMMY
], "ahb", "sdhci-esdhc-imx53.3");
571 clk_register_clkdev(clk
[IMX5_CLK_ESDHC4_PER_GATE
], "per", "sdhci-esdhc-imx53.3");
573 /* set SDHC root clock to 200MHZ*/
574 clk_set_rate(clk
[IMX5_CLK_ESDHC_A_PODF
], 200000000);
575 clk_set_rate(clk
[IMX5_CLK_ESDHC_B_PODF
], 200000000);
577 /* move can bus clk to 24MHz */
578 clk_set_parent(clk
[IMX5_CLK_CAN_SEL
], clk
[IMX5_CLK_LP_APM
]);
580 clk_prepare_enable(clk
[IMX5_CLK_IIM_GATE
]);
581 imx_print_silicon_rev("i.MX53", mx53_revision());
582 clk_disable_unprepare(clk
[IMX5_CLK_IIM_GATE
]);
584 r
= clk_round_rate(clk
[IMX5_CLK_USBOH3_PER_GATE
], 54000000);
585 clk_set_rate(clk
[IMX5_CLK_USBOH3_PER_GATE
], r
);
587 mxc_timer_init_dt(of_find_compatible_node(NULL
, NULL
, "fsl,imx53-gpt"));
589 CLK_OF_DECLARE(imx53_ccm
, "fsl,imx53-ccm", mx53_clocks_init
);