arch/arm/mach-imx/mach-mx27ads.c

   1 /*
   2  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   3  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   4  *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16 #include <linux/gpio.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/mtd/mtd.h>
  19 #include <linux/mtd/map.h>
  20 #include <linux/mtd/partitions.h>
  21 #include <linux/mtd/physmap.h>
  22 #include <linux/i2c.h>
  23 #include <linux/irq.h>
  24
  25 #include <linux/regulator/fixed.h>
  26 #include <linux/regulator/machine.h>
  27
  28 #include <asm/mach-types.h>
  29 #include <asm/mach/arch.h>
  30 #include <asm/mach/time.h>
  31 #include <asm/mach/map.h>
  32
  33 #include "common.h"
  34 #include "devices-imx27.h"
  35 #include "hardware.h"
  36 #include "iomux-mx27.h"
  37
  38 /*
  39  * Base address of PBC controller, CS4
  40  */
  41 #define PBC_BASE_ADDRESS        0xf4300000
  42 #define PBC_REG_ADDR(offset)    (void __force __iomem *) \
  43                 (PBC_BASE_ADDRESS + (offset))
  44
  45 /* When the PBC address connection is fixed in h/w, defined as 1 */
  46 #define PBC_ADDR_SH             0
  47
  48 /* Offsets for the PBC Controller register */
  49 /*
  50  * PBC Board version register offset
  51  */
  52 #define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
  53 /*
  54  * PBC Board control register 1 set address.
  55  */
  56 #define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
  57 /*
  58  * PBC Board control register 1 clear address.
  59  */
  60 #define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
  61
  62 /* PBC Board Control Register 1 bit definitions */
  63 #define PBC_BCTRL1_LCDON        0x0800  /* Enable the LCD */
  64
  65 /* to determine the correct external crystal reference */
  66 #define CKIH_27MHZ_BIT_SET      (1 << 3)
  67
  68 static const int mx27ads_pins[] __initconst = {
  69         /* UART0 */
  70         PE12_PF_UART1_TXD,
  71         PE13_PF_UART1_RXD,
  72         PE14_PF_UART1_CTS,
  73         PE15_PF_UART1_RTS,
  74         /* UART1 */
  75         PE3_PF_UART2_CTS,
  76         PE4_PF_UART2_RTS,
  77         PE6_PF_UART2_TXD,
  78         PE7_PF_UART2_RXD,
  79         /* UART2 */
  80         PE8_PF_UART3_TXD,
  81         PE9_PF_UART3_RXD,
  82         PE10_PF_UART3_CTS,
  83         PE11_PF_UART3_RTS,
  84         /* UART3 */
  85         PB26_AF_UART4_RTS,
  86         PB28_AF_UART4_TXD,
  87         PB29_AF_UART4_CTS,
  88         PB31_AF_UART4_RXD,
  89         /* UART4 */
  90         PB18_AF_UART5_TXD,
  91         PB19_AF_UART5_RXD,
  92         PB20_AF_UART5_CTS,
  93         PB21_AF_UART5_RTS,
  94         /* UART5 */
  95         PB10_AF_UART6_TXD,
  96         PB12_AF_UART6_CTS,
  97         PB11_AF_UART6_RXD,
  98         PB13_AF_UART6_RTS,
  99         /* FEC */
 100         PD0_AIN_FEC_TXD0,
 101         PD1_AIN_FEC_TXD1,
 102         PD2_AIN_FEC_TXD2,
 103         PD3_AIN_FEC_TXD3,
 104         PD4_AOUT_FEC_RX_ER,
 105         PD5_AOUT_FEC_RXD1,
 106         PD6_AOUT_FEC_RXD2,
 107         PD7_AOUT_FEC_RXD3,
 108         PD8_AF_FEC_MDIO,
 109         PD9_AIN_FEC_MDC,
 110         PD10_AOUT_FEC_CRS,
 111         PD11_AOUT_FEC_TX_CLK,
 112         PD12_AOUT_FEC_RXD0,
 113         PD13_AOUT_FEC_RX_DV,
 114         PD14_AOUT_FEC_RX_CLK,
 115         PD15_AOUT_FEC_COL,
 116         PD16_AIN_FEC_TX_ER,
 117         PF23_AIN_FEC_TX_EN,
 118         /* I2C2 */
 119         PC5_PF_I2C2_SDA,
 120         PC6_PF_I2C2_SCL,
 121         /* FB */
 122         PA5_PF_LSCLK,
 123         PA6_PF_LD0,
 124         PA7_PF_LD1,
 125         PA8_PF_LD2,
 126         PA9_PF_LD3,
 127         PA10_PF_LD4,
 128         PA11_PF_LD5,
 129         PA12_PF_LD6,
 130         PA13_PF_LD7,
 131         PA14_PF_LD8,
 132         PA15_PF_LD9,
 133         PA16_PF_LD10,
 134         PA17_PF_LD11,
 135         PA18_PF_LD12,
 136         PA19_PF_LD13,
 137         PA20_PF_LD14,
 138         PA21_PF_LD15,
 139         PA22_PF_LD16,
 140         PA23_PF_LD17,
 141         PA24_PF_REV,
 142         PA25_PF_CLS,
 143         PA26_PF_PS,
 144         PA27_PF_SPL_SPR,
 145         PA28_PF_HSYNC,
 146         PA29_PF_VSYNC,
 147         PA30_PF_CONTRAST,
 148         PA31_PF_OE_ACD,
 149         /* OWIRE */
 150         PE16_AF_OWIRE,
 151         /* SDHC1*/
 152         PE18_PF_SD1_D0,
 153         PE19_PF_SD1_D1,
 154         PE20_PF_SD1_D2,
 155         PE21_PF_SD1_D3,
 156         PE22_PF_SD1_CMD,
 157         PE23_PF_SD1_CLK,
 158         /* SDHC2*/
 159         PB4_PF_SD2_D0,
 160         PB5_PF_SD2_D1,
 161         PB6_PF_SD2_D2,
 162         PB7_PF_SD2_D3,
 163         PB8_PF_SD2_CMD,
 164         PB9_PF_SD2_CLK,
 165 };
 166
 167 static const struct mxc_nand_platform_data
 168 mx27ads_nand_board_info __initconst = {
 169         .width = 1,
 170         .hw_ecc = 1,
 171 };
 172
 173 /* ADS's NOR flash */
 174 static struct physmap_flash_data mx27ads_flash_data = {
 175         .width = 2,
 176 };
 177
 178 static struct resource mx27ads_flash_resource = {
 179         .start = 0xc0000000,
 180         .end = 0xc0000000 + 0x02000000 - 1,
 181         .flags = IORESOURCE_MEM,
 182
 183 };
 184
 185 static struct platform_device mx27ads_nor_mtd_device = {
 186         .name = "physmap-flash",
 187         .id = 0,
 188         .dev = {
 189                 .platform_data = &mx27ads_flash_data,
 190         },
 191         .num_resources = 1,
 192         .resource = &mx27ads_flash_resource,
 193 };
 194
 195 static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = {
 196         .bitrate = 100000,
 197 };
 198
 199 static struct i2c_board_info mx27ads_i2c_devices[] = {
 200 };
 201
 202 static void vgpio_set(struct gpio_chip *chip, unsigned offset, int value)
 203 {
 204         if (value)
 205                 __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
 206         else
 207                 __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
 208 }
 209
 210 static int vgpio_dir_out(struct gpio_chip *chip, unsigned offset, int value)
 211 {
 212         return 0;
 213 }
 214
 215 #define MX27ADS_LCD_GPIO        (6 * 32)
 216
 217 static struct regulator_consumer_supply mx27ads_lcd_regulator_consumer =
 218         REGULATOR_SUPPLY("lcd", "imx-fb.0");
 219
 220 static struct regulator_init_data mx27ads_lcd_regulator_init_data = {
 221         .constraints    = {
 222                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 223 },
 224         .consumer_supplies      = &mx27ads_lcd_regulator_consumer,
 225         .num_consumer_supplies  = 1,
 226 };
 227
 228 static struct fixed_voltage_config mx27ads_lcd_regulator_pdata = {
 229         .supply_name    = "LCD",
 230         .microvolts     = 3300000,
 231         .gpio           = MX27ADS_LCD_GPIO,
 232         .init_data      = &mx27ads_lcd_regulator_init_data,
 233 };
 234
 235 static void __init mx27ads_regulator_init(void)
 236 {
 237         struct gpio_chip *vchip;
 238
 239         vchip = kzalloc(sizeof(*vchip), GFP_KERNEL);
 240         vchip->owner            = THIS_MODULE;
 241         vchip->label            = "LCD";
 242         vchip->base             = MX27ADS_LCD_GPIO;
 243         vchip->ngpio            = 1;
 244         vchip->direction_output = vgpio_dir_out;
 245         vchip->set              = vgpio_set;
 246         gpiochip_add(vchip);
 247
 248         platform_device_register_data(&platform_bus, "reg-fixed-voltage",
 249                                       PLATFORM_DEVID_AUTO,
 250                                       &mx27ads_lcd_regulator_pdata,
 251                                       sizeof(mx27ads_lcd_regulator_pdata));
 252 }
 253
 254 static struct imx_fb_videomode mx27ads_modes[] = {
 255         {
 256                 .mode = {
 257                         .name           = "Sharp-LQ035Q7",
 258                         .refresh        = 60,
 259                         .xres           = 240,
 260                         .yres           = 320,
 261                         .pixclock       = 188679, /* in ps (5.3MHz) */
 262                         .hsync_len      = 1,
 263                         .left_margin    = 9,
 264                         .right_margin   = 16,
 265                         .vsync_len      = 1,
 266                         .upper_margin   = 7,
 267                         .lower_margin   = 9,
 268                 },
 269                 .bpp            = 16,
 270                 .pcr            = 0xFB008BC0,
 271         },
 272 };
 273
 274 static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
 275         .mode = mx27ads_modes,
 276         .num_modes = ARRAY_SIZE(mx27ads_modes),
 277
 278         /*
 279          * - HSYNC active high
 280          * - VSYNC active high
 281          * - clk notenabled while idle
 282          * - clock inverted
 283          * - data not inverted
 284          * - data enable low active
 285          * - enable sharp mode
 286          */
 287         .pwmr           = 0x00A903FF,
 288         .lscr1          = 0x00120300,
 289         .dmacr          = 0x00020010,
 290 };
 291
 292 static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
 293                               void *data)
 294 {
 295         return request_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), detect_irq,
 296                            IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
 297 }
 298
 299 static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
 300                               void *data)
 301 {
 302         return request_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), detect_irq,
 303                            IRQF_TRIGGER_RISING, "sdhc2-card-detect", data);
 304 }
 305
 306 static void mx27ads_sdhc1_exit(struct device *dev, void *data)
 307 {
 308         free_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), data);
 309 }
 310
 311 static void mx27ads_sdhc2_exit(struct device *dev, void *data)
 312 {
 313         free_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), data);
 314 }
 315
 316 static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
 317         .init = mx27ads_sdhc1_init,
 318         .exit = mx27ads_sdhc1_exit,
 319 };
 320
 321 static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
 322         .init = mx27ads_sdhc2_init,
 323         .exit = mx27ads_sdhc2_exit,
 324 };
 325
 326 static struct platform_device *platform_devices[] __initdata = {
 327         &mx27ads_nor_mtd_device,
 328 };
 329
 330 static const struct imxuart_platform_data uart_pdata __initconst = {
 331         .flags = IMXUART_HAVE_RTSCTS,
 332 };
 333
 334 static void __init mx27ads_board_init(void)
 335 {
 336         imx27_soc_init();
 337
 338         mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
 339                         "mx27ads");
 340
 341         imx27_add_imx_uart0(&uart_pdata);
 342         imx27_add_imx_uart1(&uart_pdata);
 343         imx27_add_imx_uart2(&uart_pdata);
 344         imx27_add_imx_uart3(&uart_pdata);
 345         imx27_add_imx_uart4(&uart_pdata);
 346         imx27_add_imx_uart5(&uart_pdata);
 347         imx27_add_mxc_nand(&mx27ads_nand_board_info);
 348
 349         /* only the i2c master 1 is used on this CPU card */
 350         i2c_register_board_info(1, mx27ads_i2c_devices,
 351                                 ARRAY_SIZE(mx27ads_i2c_devices));
 352         imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
 353         mx27ads_regulator_init();
 354         imx27_add_imx_fb(&mx27ads_fb_data);
 355         imx27_add_mxc_mmc(0, &sdhc1_pdata);
 356         imx27_add_mxc_mmc(1, &sdhc2_pdata);
 357
 358         imx27_add_fec(NULL);
 359         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 360         imx27_add_mxc_w1();
 361 }
 362
 363 static void __init mx27ads_timer_init(void)
 364 {
 365         unsigned long fref = 26000000;
 366
 367         if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
 368                 fref = 27000000;
 369
 370         mx27_clocks_init(fref);
 371 }
 372
 373 static struct map_desc mx27ads_io_desc[] __initdata = {
 374         {
 375                 .virtual = PBC_BASE_ADDRESS,
 376                 .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR),
 377                 .length = SZ_1M,
 378                 .type = MT_DEVICE,
 379         },
 380 };
 381
 382 static void __init mx27ads_map_io(void)
 383 {
 384         mx27_map_io();
 385         iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
 386 }
 387
 388 MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
 389         /* maintainer: Freescale Semiconductor, Inc. */
 390         .atag_offset = 0x100,
 391         .map_io = mx27ads_map_io,
 392         .init_early = imx27_init_early,
 393         .init_irq = mx27_init_irq,
 394         .init_time      = mx27ads_timer_init,
 395         .init_machine = mx27ads_board_init,
 396         .restart        = mxc_restart,
 397 MACHINE_END