arch/arm/mach-imx/mm-imx5.c

   1 /*
   2  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License.  You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  *
  11  * Create static mapping between physical to virtual memory.
  12  */
  13
  14 #include <linux/mm.h>
  15 #include <linux/init.h>
  16 #include <linux/clk.h>
  17 #include <linux/pinctrl/machine.h>
  18 #include <linux/of_address.h>
  19
  20 #include <asm/mach/map.h>
  21
  22 #include "common.h"
  23 #include "devices/devices-common.h"
  24 #include "hardware.h"
  25 #include "iomux-v3.h"
  26
  27 /*
  28  * Define the MX51 memory map.
  29  */
  30 static struct map_desc mx51_io_desc[] __initdata = {
  31         imx_map_entry(MX51, TZIC, MT_DEVICE),
  32         imx_map_entry(MX51, IRAM, MT_DEVICE),
  33         imx_map_entry(MX51, AIPS1, MT_DEVICE),
  34         imx_map_entry(MX51, SPBA0, MT_DEVICE),
  35         imx_map_entry(MX51, AIPS2, MT_DEVICE),
  36 };
  37
  38 /*
  39  * Define the MX53 memory map.
  40  */
  41 static struct map_desc mx53_io_desc[] __initdata = {
  42         imx_map_entry(MX53, TZIC, MT_DEVICE),
  43         imx_map_entry(MX53, AIPS1, MT_DEVICE),
  44         imx_map_entry(MX53, SPBA0, MT_DEVICE),
  45         imx_map_entry(MX53, AIPS2, MT_DEVICE),
  46 };
  47
  48 /*
  49  * This function initializes the memory map. It is called during the
  50  * system startup to create static physical to virtual memory mappings
  51  * for the IO modules.
  52  */
  53 void __init mx51_map_io(void)
  54 {
  55         iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
  56 }
  57
  58 void __init mx53_map_io(void)
  59 {
  60         iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
  61 }
  62
  63 /*
  64  * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
  65  * the Freescale marketing division. However this did not remove the
  66  * hardware from the chip which still needs to be configured for proper
  67  * IPU support.
  68  */
  69 static void __init imx51_ipu_mipi_setup(void)
  70 {
  71         void __iomem *hsc_addr;
  72         hsc_addr = MX51_IO_ADDRESS(MX51_MIPI_HSC_BASE_ADDR);
  73
  74         /* setup MIPI module to legacy mode */
  75         __raw_writel(0xf00, hsc_addr);
  76
  77         /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
  78         __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
  79                 hsc_addr + 0x800);
  80 }
  81
  82 void __init imx51_init_early(void)
  83 {
  84         imx51_ipu_mipi_setup();
  85         mxc_set_cpu_type(MXC_CPU_MX51);
  86         mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
  87         imx_src_init();
  88 }
  89
  90 void __init imx53_init_early(void)
  91 {
  92         mxc_set_cpu_type(MXC_CPU_MX53);
  93         imx_src_init();
  94 }
  95
  96 void __init mx51_init_irq(void)
  97 {
  98         tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
  99 }
 100
 101 void __init mx53_init_irq(void)
 102 {
 103         struct device_node *np;
 104         void __iomem *base;
 105
 106         np = of_find_compatible_node(NULL, NULL, "fsl,imx53-tzic");
 107         base = of_iomap(np, 0);
 108         WARN_ON(!base);
 109
 110         tzic_init_irq(base);
 111 }
 112
 113 static struct sdma_platform_data imx51_sdma_pdata __initdata = {
 114         .fw_name = "sdma-imx51.bin",
 115 };
 116
 117 static const struct resource imx51_audmux_res[] __initconst = {
 118         DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
 119 };
 120
 121 void __init imx51_soc_init(void)
 122 {
 123         mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
 124         mxc_device_init();
 125
 126         /* i.mx51 has the i.mx35 type gpio */
 127         mxc_register_gpio("imx35-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
 128         mxc_register_gpio("imx35-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
 129         mxc_register_gpio("imx35-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
 130         mxc_register_gpio("imx35-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
 131
 132         pinctrl_provide_dummies();
 133
 134         /* i.mx51 has the i.mx35 type sdma */
 135         imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
 136
 137         /* Setup AIPS registers */
 138         imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
 139         imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
 140
 141         /* i.mx51 has the i.mx31 type audmux */
 142         platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
 143                                         ARRAY_SIZE(imx51_audmux_res));
 144 }
 145
 146 void __init imx51_init_late(void)
 147 {
 148         mx51_neon_fixup();
 149         imx5_pm_init();
 150 }
 151
 152 void __init imx53_init_late(void)
 153 {
 154         imx5_pm_init();
 155 }