2 * iop13xx platform Initialization
3 * Copyright (c) 2005-2006, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
20 #include <linux/dma-mapping.h>
21 #include <linux/serial_8250.h>
23 #ifdef CONFIG_MTD_PHYSMAP
24 #include <linux/mtd/physmap.h>
26 #include <asm/mach/map.h>
27 #include <mach/hardware.h>
29 #include <asm/hardware/iop_adma.h>
30 #include <mach/irqs.h>
32 #define IOP13XX_UART_XTAL 33334000
33 #define IOP13XX_SETUP_DEBUG 0
34 #define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))
36 /* Standard IO mapping for all IOP13XX based systems
38 static struct map_desc iop13xx_std_desc
[] __initdata
= {
39 { /* mem mapped registers */
40 .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE
,
41 .pfn
= __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE
),
42 .length
= IOP13XX_PMMR_SIZE
,
47 static struct resource iop13xx_uart0_resources
[] = {
49 .start
= IOP13XX_UART0_PHYS
,
50 .end
= IOP13XX_UART0_PHYS
+ 0x3f,
51 .flags
= IORESOURCE_MEM
,
54 .start
= IRQ_IOP13XX_UART0
,
55 .end
= IRQ_IOP13XX_UART0
,
56 .flags
= IORESOURCE_IRQ
60 static struct resource iop13xx_uart1_resources
[] = {
62 .start
= IOP13XX_UART1_PHYS
,
63 .end
= IOP13XX_UART1_PHYS
+ 0x3f,
64 .flags
= IORESOURCE_MEM
,
67 .start
= IRQ_IOP13XX_UART1
,
68 .end
= IRQ_IOP13XX_UART1
,
69 .flags
= IORESOURCE_IRQ
73 static struct plat_serial8250_port iop13xx_uart0_data
[] = {
75 .membase
= IOP13XX_UART0_VIRT
,
76 .mapbase
= IOP13XX_UART0_PHYS
,
77 .irq
= IRQ_IOP13XX_UART0
,
78 .uartclk
= IOP13XX_UART_XTAL
,
81 .flags
= UPF_SKIP_TEST
,
86 static struct plat_serial8250_port iop13xx_uart1_data
[] = {
88 .membase
= IOP13XX_UART1_VIRT
,
89 .mapbase
= IOP13XX_UART1_PHYS
,
90 .irq
= IRQ_IOP13XX_UART1
,
91 .uartclk
= IOP13XX_UART_XTAL
,
94 .flags
= UPF_SKIP_TEST
,
99 /* The ids are fixed up later in iop13xx_platform_init */
100 static struct platform_device iop13xx_uart0
= {
101 .name
= "serial8250",
103 .dev
.platform_data
= iop13xx_uart0_data
,
105 .resource
= iop13xx_uart0_resources
,
108 static struct platform_device iop13xx_uart1
= {
109 .name
= "serial8250",
111 .dev
.platform_data
= iop13xx_uart1_data
,
113 .resource
= iop13xx_uart1_resources
116 static struct resource iop13xx_i2c_0_resources
[] = {
118 .start
= IOP13XX_I2C0_PHYS
,
119 .end
= IOP13XX_I2C0_PHYS
+ 0x18,
120 .flags
= IORESOURCE_MEM
,
123 .start
= IRQ_IOP13XX_I2C_0
,
124 .end
= IRQ_IOP13XX_I2C_0
,
125 .flags
= IORESOURCE_IRQ
129 static struct resource iop13xx_i2c_1_resources
[] = {
131 .start
= IOP13XX_I2C1_PHYS
,
132 .end
= IOP13XX_I2C1_PHYS
+ 0x18,
133 .flags
= IORESOURCE_MEM
,
136 .start
= IRQ_IOP13XX_I2C_1
,
137 .end
= IRQ_IOP13XX_I2C_1
,
138 .flags
= IORESOURCE_IRQ
142 static struct resource iop13xx_i2c_2_resources
[] = {
144 .start
= IOP13XX_I2C2_PHYS
,
145 .end
= IOP13XX_I2C2_PHYS
+ 0x18,
146 .flags
= IORESOURCE_MEM
,
149 .start
= IRQ_IOP13XX_I2C_2
,
150 .end
= IRQ_IOP13XX_I2C_2
,
151 .flags
= IORESOURCE_IRQ
155 /* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
156 * we just use the same device name.
159 /* The ids are fixed up later in iop13xx_platform_init */
160 static struct platform_device iop13xx_i2c_0_controller
= {
161 .name
= "IOP3xx-I2C",
164 .resource
= iop13xx_i2c_0_resources
167 static struct platform_device iop13xx_i2c_1_controller
= {
168 .name
= "IOP3xx-I2C",
171 .resource
= iop13xx_i2c_1_resources
174 static struct platform_device iop13xx_i2c_2_controller
= {
175 .name
= "IOP3xx-I2C",
178 .resource
= iop13xx_i2c_2_resources
181 #ifdef CONFIG_MTD_PHYSMAP
184 static struct physmap_flash_data iq8134x_flash_data
= {
188 static struct resource iq8134x_flash_resource
= {
189 .start
= IQ81340_FLASHBASE
,
191 .flags
= IORESOURCE_MEM
,
194 static struct platform_device iq8134x_flash
= {
195 .name
= "physmap-flash",
197 .dev
= { .platform_data
= &iq8134x_flash_data
, },
199 .resource
= &iq8134x_flash_resource
,
202 static unsigned long iq8134x_probe_flash_size(void)
204 uint8_t __iomem
*flash_addr
= ioremap(IQ81340_FLASHBASE
, PAGE_SIZE
);
207 unsigned long size
= 0;
208 int width
= iq8134x_flash_data
.width
;
211 /* send CFI 'query' command */
212 writew(0x98, flash_addr
);
214 /* check for CFI compliance */
215 for (i
= 0; i
< 3 * width
; i
+= width
)
216 query
[i
/ width
] = readb(flash_addr
+ (0x10 * width
) + i
);
219 if (memcmp(query
, "QRY", 3) == 0)
220 size
= 1 << readb(flash_addr
+ (0x27 * width
));
222 /* send CFI 'read array' command */
223 writew(0xff, flash_addr
);
233 static struct resource iop13xx_adma_0_resources
[] = {
235 .start
= IOP13XX_ADMA_PHYS_BASE(0),
236 .end
= IOP13XX_ADMA_UPPER_PA(0),
237 .flags
= IORESOURCE_MEM
,
240 .start
= IRQ_IOP13XX_ADMA0_EOT
,
241 .end
= IRQ_IOP13XX_ADMA0_EOT
,
242 .flags
= IORESOURCE_IRQ
245 .start
= IRQ_IOP13XX_ADMA0_EOC
,
246 .end
= IRQ_IOP13XX_ADMA0_EOC
,
247 .flags
= IORESOURCE_IRQ
250 .start
= IRQ_IOP13XX_ADMA0_ERR
,
251 .end
= IRQ_IOP13XX_ADMA0_ERR
,
252 .flags
= IORESOURCE_IRQ
256 static struct resource iop13xx_adma_1_resources
[] = {
258 .start
= IOP13XX_ADMA_PHYS_BASE(1),
259 .end
= IOP13XX_ADMA_UPPER_PA(1),
260 .flags
= IORESOURCE_MEM
,
263 .start
= IRQ_IOP13XX_ADMA1_EOT
,
264 .end
= IRQ_IOP13XX_ADMA1_EOT
,
265 .flags
= IORESOURCE_IRQ
268 .start
= IRQ_IOP13XX_ADMA1_EOC
,
269 .end
= IRQ_IOP13XX_ADMA1_EOC
,
270 .flags
= IORESOURCE_IRQ
273 .start
= IRQ_IOP13XX_ADMA1_ERR
,
274 .end
= IRQ_IOP13XX_ADMA1_ERR
,
275 .flags
= IORESOURCE_IRQ
279 static struct resource iop13xx_adma_2_resources
[] = {
281 .start
= IOP13XX_ADMA_PHYS_BASE(2),
282 .end
= IOP13XX_ADMA_UPPER_PA(2),
283 .flags
= IORESOURCE_MEM
,
286 .start
= IRQ_IOP13XX_ADMA2_EOT
,
287 .end
= IRQ_IOP13XX_ADMA2_EOT
,
288 .flags
= IORESOURCE_IRQ
291 .start
= IRQ_IOP13XX_ADMA2_EOC
,
292 .end
= IRQ_IOP13XX_ADMA2_EOC
,
293 .flags
= IORESOURCE_IRQ
296 .start
= IRQ_IOP13XX_ADMA2_ERR
,
297 .end
= IRQ_IOP13XX_ADMA2_ERR
,
298 .flags
= IORESOURCE_IRQ
302 static u64 iop13xx_adma_dmamask
= DMA_BIT_MASK(64);
303 static struct iop_adma_platform_data iop13xx_adma_0_data
= {
305 .pool_size
= PAGE_SIZE
,
308 static struct iop_adma_platform_data iop13xx_adma_1_data
= {
310 .pool_size
= PAGE_SIZE
,
313 static struct iop_adma_platform_data iop13xx_adma_2_data
= {
315 .pool_size
= PAGE_SIZE
,
318 /* The ids are fixed up later in iop13xx_platform_init */
319 static struct platform_device iop13xx_adma_0_channel
= {
323 .resource
= iop13xx_adma_0_resources
,
325 .dma_mask
= &iop13xx_adma_dmamask
,
326 .coherent_dma_mask
= DMA_BIT_MASK(64),
327 .platform_data
= (void *) &iop13xx_adma_0_data
,
331 static struct platform_device iop13xx_adma_1_channel
= {
335 .resource
= iop13xx_adma_1_resources
,
337 .dma_mask
= &iop13xx_adma_dmamask
,
338 .coherent_dma_mask
= DMA_BIT_MASK(64),
339 .platform_data
= (void *) &iop13xx_adma_1_data
,
343 static struct platform_device iop13xx_adma_2_channel
= {
347 .resource
= iop13xx_adma_2_resources
,
349 .dma_mask
= &iop13xx_adma_dmamask
,
350 .coherent_dma_mask
= DMA_BIT_MASK(64),
351 .platform_data
= (void *) &iop13xx_adma_2_data
,
355 void __init
iop13xx_map_io(void)
357 /* Initialize the Static Page Table maps */
358 iotable_init(iop13xx_std_desc
, ARRAY_SIZE(iop13xx_std_desc
));
361 static int init_uart
;
363 static int init_adma
;
365 void __init
iop13xx_platform_init(void)
368 u32 uart_idx
, i2c_idx
, adma_idx
, plat_idx
;
369 struct platform_device
*iop13xx_devices
[IQ81340_MAX_PLAT_DEVICES
];
371 /* set the bases so we can read the device id */
372 iop13xx_set_atu_mmr_bases();
374 memset(iop13xx_devices
, 0, sizeof(iop13xx_devices
));
376 if (init_uart
== IOP13XX_INIT_UART_DEFAULT
) {
377 switch (iop13xx_dev_id()) {
378 /* enable both uarts on iop341 */
383 init_uart
|= IOP13XX_INIT_UART_0
;
384 init_uart
|= IOP13XX_INIT_UART_1
;
386 /* only enable uart 1 */
388 init_uart
|= IOP13XX_INIT_UART_1
;
392 if (init_i2c
== IOP13XX_INIT_I2C_DEFAULT
) {
393 switch (iop13xx_dev_id()) {
394 /* enable all i2c units on iop341 and iop342 */
403 init_i2c
|= IOP13XX_INIT_I2C_0
;
404 init_i2c
|= IOP13XX_INIT_I2C_1
;
405 init_i2c
|= IOP13XX_INIT_I2C_2
;
407 /* only enable i2c 1 and 2 */
409 init_i2c
|= IOP13XX_INIT_I2C_1
;
410 init_i2c
|= IOP13XX_INIT_I2C_2
;
414 if (init_adma
== IOP13XX_INIT_ADMA_DEFAULT
) {
415 init_adma
|= IOP13XX_INIT_ADMA_0
;
416 init_adma
|= IOP13XX_INIT_ADMA_1
;
417 init_adma
|= IOP13XX_INIT_ADMA_2
;
424 /* uart 1 (if enabled) is ttyS0 */
425 if (init_uart
& IOP13XX_INIT_UART_1
) {
426 PRINTK("Adding uart1 to platform device list\n");
427 iop13xx_uart1
.id
= uart_idx
++;
428 iop13xx_devices
[plat_idx
++] = &iop13xx_uart1
;
430 if (init_uart
& IOP13XX_INIT_UART_0
) {
431 PRINTK("Adding uart0 to platform device list\n");
432 iop13xx_uart0
.id
= uart_idx
++;
433 iop13xx_devices
[plat_idx
++] = &iop13xx_uart0
;
436 for(i
= 0; i
< IQ81340_NUM_I2C
; i
++) {
437 if ((init_i2c
& (1 << i
)) && IOP13XX_SETUP_DEBUG
)
438 printk("Adding i2c%d to platform device list\n", i
);
439 switch(init_i2c
& (1 << i
)) {
440 case IOP13XX_INIT_I2C_0
:
441 iop13xx_i2c_0_controller
.id
= i2c_idx
++;
442 iop13xx_devices
[plat_idx
++] =
443 &iop13xx_i2c_0_controller
;
445 case IOP13XX_INIT_I2C_1
:
446 iop13xx_i2c_1_controller
.id
= i2c_idx
++;
447 iop13xx_devices
[plat_idx
++] =
448 &iop13xx_i2c_1_controller
;
450 case IOP13XX_INIT_I2C_2
:
451 iop13xx_i2c_2_controller
.id
= i2c_idx
++;
452 iop13xx_devices
[plat_idx
++] =
453 &iop13xx_i2c_2_controller
;
458 /* initialize adma channel ids and capabilities */
460 for (i
= 0; i
< IQ81340_NUM_ADMA
; i
++) {
461 struct iop_adma_platform_data
*plat_data
;
462 if ((init_adma
& (1 << i
)) && IOP13XX_SETUP_DEBUG
)
464 "Adding adma%d to platform device list\n", i
);
465 switch (init_adma
& (1 << i
)) {
466 case IOP13XX_INIT_ADMA_0
:
467 iop13xx_adma_0_channel
.id
= adma_idx
++;
468 iop13xx_devices
[plat_idx
++] = &iop13xx_adma_0_channel
;
469 plat_data
= &iop13xx_adma_0_data
;
470 dma_cap_set(DMA_MEMCPY
, plat_data
->cap_mask
);
471 dma_cap_set(DMA_XOR
, plat_data
->cap_mask
);
472 dma_cap_set(DMA_XOR_VAL
, plat_data
->cap_mask
);
473 dma_cap_set(DMA_INTERRUPT
, plat_data
->cap_mask
);
475 case IOP13XX_INIT_ADMA_1
:
476 iop13xx_adma_1_channel
.id
= adma_idx
++;
477 iop13xx_devices
[plat_idx
++] = &iop13xx_adma_1_channel
;
478 plat_data
= &iop13xx_adma_1_data
;
479 dma_cap_set(DMA_MEMCPY
, plat_data
->cap_mask
);
480 dma_cap_set(DMA_XOR
, plat_data
->cap_mask
);
481 dma_cap_set(DMA_XOR_VAL
, plat_data
->cap_mask
);
482 dma_cap_set(DMA_INTERRUPT
, plat_data
->cap_mask
);
484 case IOP13XX_INIT_ADMA_2
:
485 iop13xx_adma_2_channel
.id
= adma_idx
++;
486 iop13xx_devices
[plat_idx
++] = &iop13xx_adma_2_channel
;
487 plat_data
= &iop13xx_adma_2_data
;
488 dma_cap_set(DMA_MEMCPY
, plat_data
->cap_mask
);
489 dma_cap_set(DMA_XOR
, plat_data
->cap_mask
);
490 dma_cap_set(DMA_XOR_VAL
, plat_data
->cap_mask
);
491 dma_cap_set(DMA_INTERRUPT
, plat_data
->cap_mask
);
492 dma_cap_set(DMA_PQ
, plat_data
->cap_mask
);
493 dma_cap_set(DMA_PQ_VAL
, plat_data
->cap_mask
);
498 #ifdef CONFIG_MTD_PHYSMAP
499 iq8134x_flash_resource
.end
= iq8134x_flash_resource
.start
+
500 iq8134x_probe_flash_size() - 1;
501 if (iq8134x_flash_resource
.end
> iq8134x_flash_resource
.start
)
502 iop13xx_devices
[plat_idx
++] = &iq8134x_flash
;
504 printk(KERN_ERR
"%s: Failed to probe flash size\n", __func__
);
507 platform_add_devices(iop13xx_devices
, plat_idx
);
510 static int __init
iop13xx_init_uart_setup(char *str
)
513 while (*str
!= '\0') {
516 init_uart
|= IOP13XX_INIT_UART_0
;
519 init_uart
|= IOP13XX_INIT_UART_1
;
525 PRINTK("\"iop13xx_init_uart\" malformed"
526 " at character: \'%c\'", *str
);
528 init_uart
= IOP13XX_INIT_UART_DEFAULT
;
536 static int __init
iop13xx_init_i2c_setup(char *str
)
539 while (*str
!= '\0') {
542 init_i2c
|= IOP13XX_INIT_I2C_0
;
545 init_i2c
|= IOP13XX_INIT_I2C_1
;
548 init_i2c
|= IOP13XX_INIT_I2C_2
;
554 PRINTK("\"iop13xx_init_i2c\" malformed"
555 " at character: \'%c\'", *str
);
557 init_i2c
= IOP13XX_INIT_I2C_DEFAULT
;
565 static int __init
iop13xx_init_adma_setup(char *str
)
568 while (*str
!= '\0') {
571 init_adma
|= IOP13XX_INIT_ADMA_0
;
574 init_adma
|= IOP13XX_INIT_ADMA_1
;
577 init_adma
|= IOP13XX_INIT_ADMA_2
;
583 PRINTK("\"iop13xx_init_adma\" malformed"
584 " at character: \'%c\'", *str
);
586 init_adma
= IOP13XX_INIT_ADMA_DEFAULT
;
594 __setup("iop13xx_init_adma", iop13xx_init_adma_setup
);
595 __setup("iop13xx_init_uart", iop13xx_init_uart_setup
);
596 __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup
);
598 void iop13xx_restart(enum reboot_mode mode
, const char *cmd
)
601 * Reset the internal bus (warning both cores are reset)
603 write_wdtcr(IOP_WDTCR_EN_ARM
);
604 write_wdtcr(IOP_WDTCR_EN
);
605 write_wdtsr(IOP13XX_WDTSR_WRITE_EN
| IOP13XX_WDTCR_IB_RESET
);