arch/arm/mach-ixp4xx/include/mach/io.h

   1 /*
   2  * arch/arm/mach-ixp4xx/include/mach/io.h
   3  *
   4  * Author: Deepak Saxena <dsaxena@plexity.net>
   5  *
   6  * Copyright (C) 2002-2005  MontaVista Software, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ASM_ARM_ARCH_IO_H
  14 #define __ASM_ARM_ARCH_IO_H
  15
  16 #include <linux/bitops.h>
  17
  18 #include <mach/hardware.h>
  19
  20 extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
  21 extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
  22
  23
  24 /*
  25  * IXP4xx provides two methods of accessing PCI memory space:
  26  *
  27  * 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB).
  28  *    To access PCI via this space, we simply ioremap() the BAR
  29  *    into the kernel and we can use the standard read[bwl]/write[bwl]
  30  *    macros. This is the preffered method due to speed but it
  31  *    limits the system to just 64MB of PCI memory. This can be
  32  *    problematic if using video cards and other memory-heavy targets.
  33  *
  34  * 2) If > 64MB of memory space is required, the IXP4xx can use indirect
  35  *    registers to access the whole 4 GB of PCI memory space (as we do below
  36  *    for I/O transactions). This allows currently for up to 1 GB (0x10000000
  37  *    to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that
  38  *    every PCI access requires three local register accesses plus a spinlock,
  39  *    but in some cases the performance hit is acceptable. In addition, you
  40  *    cannot mmap() PCI devices in this case.
  41  */
  42 #ifdef  CONFIG_IXP4XX_INDIRECT_PCI
  43
  44 /*
  45  * In the case of using indirect PCI, we simply return the actual PCI
  46  * address and our read/write implementation use that to drive the
  47  * access registers. If something outside of PCI is ioremap'd, we
  48  * fallback to the default.
  49  */
  50
  51 extern unsigned long pcibios_min_mem;
  52 static inline int is_pci_memory(u32 addr)
  53 {
  54         return (addr >= pcibios_min_mem) && (addr <= 0x4FFFFFFF);
  55 }
  56
  57 #define writeb(v, p)                    __indirect_writeb(v, p)
  58 #define writew(v, p)                    __indirect_writew(v, p)
  59 #define writel(v, p)                    __indirect_writel(v, p)
  60
  61 #define writesb(p, v, l)                __indirect_writesb(p, v, l)
  62 #define writesw(p, v, l)                __indirect_writesw(p, v, l)
  63 #define writesl(p, v, l)                __indirect_writesl(p, v, l)
  64
  65 #define readb(p)                        __indirect_readb(p)
  66 #define readw(p)                        __indirect_readw(p)
  67 #define readl(p)                        __indirect_readl(p)
  68
  69 #define readsb(p, v, l)                 __indirect_readsb(p, v, l)
  70 #define readsw(p, v, l)                 __indirect_readsw(p, v, l)
  71 #define readsl(p, v, l)                 __indirect_readsl(p, v, l)
  72
  73 static inline void __indirect_writeb(u8 value, volatile void __iomem *p)
  74 {
  75         u32 addr = (u32)p;
  76         u32 n, byte_enables, data;
  77
  78         if (!is_pci_memory(addr)) {
  79                 __raw_writeb(value, addr);
  80                 return;
  81         }
  82
  83         n = addr % 4;
  84         byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
  85         data = value << (8*n);
  86         ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
  87 }
  88
  89 static inline void __indirect_writesb(volatile void __iomem *bus_addr,
  90                                       const u8 *vaddr, int count)
  91 {
  92         while (count--)
  93                 writeb(*vaddr++, bus_addr);
  94 }
  95
  96 static inline void __indirect_writew(u16 value, volatile void __iomem *p)
  97 {
  98         u32 addr = (u32)p;
  99         u32 n, byte_enables, data;
 100
 101         if (!is_pci_memory(addr)) {
 102                 __raw_writew(value, addr);
 103                 return;
 104         }
 105
 106         n = addr % 4;
 107         byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
 108         data = value << (8*n);
 109         ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
 110 }
 111
 112 static inline void __indirect_writesw(volatile void __iomem *bus_addr,
 113                                       const u16 *vaddr, int count)
 114 {
 115         while (count--)
 116                 writew(*vaddr++, bus_addr);
 117 }
 118
 119 static inline void __indirect_writel(u32 value, volatile void __iomem *p)
 120 {
 121         u32 addr = (__force u32)p;
 122
 123         if (!is_pci_memory(addr)) {
 124                 __raw_writel(value, p);
 125                 return;
 126         }
 127
 128         ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
 129 }
 130
 131 static inline void __indirect_writesl(volatile void __iomem *bus_addr,
 132                                       const u32 *vaddr, int count)
 133 {
 134         while (count--)
 135                 writel(*vaddr++, bus_addr);
 136 }
 137
 138 static inline unsigned char __indirect_readb(const volatile void __iomem *p)
 139 {
 140         u32 addr = (u32)p;
 141         u32 n, byte_enables, data;
 142
 143         if (!is_pci_memory(addr))
 144                 return __raw_readb(addr);
 145
 146         n = addr % 4;
 147         byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
 148         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
 149                 return 0xff;
 150
 151         return data >> (8*n);
 152 }
 153
 154 static inline void __indirect_readsb(const volatile void __iomem *bus_addr,
 155                                      u8 *vaddr, u32 count)
 156 {
 157         while (count--)
 158                 *vaddr++ = readb(bus_addr);
 159 }
 160
 161 static inline unsigned short __indirect_readw(const volatile void __iomem *p)
 162 {
 163         u32 addr = (u32)p;
 164         u32 n, byte_enables, data;
 165
 166         if (!is_pci_memory(addr))
 167                 return __raw_readw(addr);
 168
 169         n = addr % 4;
 170         byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
 171         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
 172                 return 0xffff;
 173
 174         return data>>(8*n);
 175 }
 176
 177 static inline void __indirect_readsw(const volatile void __iomem *bus_addr,
 178                                      u16 *vaddr, u32 count)
 179 {
 180         while (count--)
 181                 *vaddr++ = readw(bus_addr);
 182 }
 183
 184 static inline unsigned long __indirect_readl(const volatile void __iomem *p)
 185 {
 186         u32 addr = (__force u32)p;
 187         u32 data;
 188
 189         if (!is_pci_memory(addr))
 190                 return __raw_readl(p);
 191
 192         if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
 193                 return 0xffffffff;
 194
 195         return data;
 196 }
 197
 198 static inline void __indirect_readsl(const volatile void __iomem *bus_addr,
 199                                      u32 *vaddr, u32 count)
 200 {
 201         while (count--)
 202                 *vaddr++ = readl(bus_addr);
 203 }
 204
 205
 206 /*
 207  * We can use the built-in functions b/c they end up calling writeb/readb
 208  */
 209 #define memset_io(c,v,l)                _memset_io((c),(v),(l))
 210 #define memcpy_fromio(a,c,l)            _memcpy_fromio((a),(c),(l))
 211 #define memcpy_toio(c,a,l)              _memcpy_toio((c),(a),(l))
 212
 213 #endif /* CONFIG_IXP4XX_INDIRECT_PCI */
 214
 215 #ifndef CONFIG_PCI
 216
 217 #define __io(v)         __typesafe_io(v)
 218
 219 #else
 220
 221 /*
 222  * IXP4xx does not have a transparent cpu -> PCI I/O translation
 223  * window.  Instead, it has a set of registers that must be tweaked
 224  * with the proper byte lanes, command types, and address for the
 225  * transaction.  This means that we need to override the default
 226  * I/O functions.
 227  */
 228
 229 static inline void outb(u8 value, u32 addr)
 230 {
 231         u32 n, byte_enables, data;
 232         n = addr % 4;
 233         byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
 234         data = value << (8*n);
 235         ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
 236 }
 237
 238 static inline void outsb(u32 io_addr, const u8 *vaddr, u32 count)
 239 {
 240         while (count--)
 241                 outb(*vaddr++, io_addr);
 242 }
 243
 244 static inline void outw(u16 value, u32 addr)
 245 {
 246         u32 n, byte_enables, data;
 247         n = addr % 4;
 248         byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
 249         data = value << (8*n);
 250         ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
 251 }
 252
 253 static inline void outsw(u32 io_addr, const u16 *vaddr, u32 count)
 254 {
 255         while (count--)
 256                 outw(cpu_to_le16(*vaddr++), io_addr);
 257 }
 258
 259 static inline void outl(u32 value, u32 addr)
 260 {
 261         ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
 262 }
 263
 264 static inline void outsl(u32 io_addr, const u32 *vaddr, u32 count)
 265 {
 266         while (count--)
 267                 outl(cpu_to_le32(*vaddr++), io_addr);
 268 }
 269
 270 static inline u8 inb(u32 addr)
 271 {
 272         u32 n, byte_enables, data;
 273         n = addr % 4;
 274         byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
 275         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
 276                 return 0xff;
 277
 278         return data >> (8*n);
 279 }
 280
 281 static inline void insb(u32 io_addr, u8 *vaddr, u32 count)
 282 {
 283         while (count--)
 284                 *vaddr++ = inb(io_addr);
 285 }
 286
 287 static inline u16 inw(u32 addr)
 288 {
 289         u32 n, byte_enables, data;
 290         n = addr % 4;
 291         byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
 292         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
 293                 return 0xffff;
 294
 295         return data>>(8*n);
 296 }
 297
 298 static inline void insw(u32 io_addr, u16 *vaddr, u32 count)
 299 {
 300         while (count--)
 301                 *vaddr++ = le16_to_cpu(inw(io_addr));
 302 }
 303
 304 static inline u32 inl(u32 addr)
 305 {
 306         u32 data;
 307         if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
 308                 return 0xffffffff;
 309
 310         return data;
 311 }
 312
 313 static inline void insl(u32 io_addr, u32 *vaddr, u32 count)
 314 {
 315         while (count--)
 316                 *vaddr++ = le32_to_cpu(inl(io_addr));
 317 }
 318
 319 #define PIO_OFFSET      0x10000UL
 320 #define PIO_MASK        0x0ffffUL
 321
 322 #define __is_io_address(p)      (((unsigned long)p >= PIO_OFFSET) && \
 323                                         ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
 324
 325 #define ioread8(p)                      ioread8(p)
 326 static inline unsigned int ioread8(const void __iomem *addr)
 327 {
 328         unsigned long port = (unsigned long __force)addr;
 329         if (__is_io_address(port))
 330                 return (unsigned int)inb(port & PIO_MASK);
 331         else
 332 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 333                 return (unsigned int)__raw_readb(addr);
 334 #else
 335                 return (unsigned int)__indirect_readb(addr);
 336 #endif
 337 }
 338
 339 #define ioread8_rep(p, v, c)            ioread8_rep(p, v, c)
 340 static inline void ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
 341 {
 342         unsigned long port = (unsigned long __force)addr;
 343         if (__is_io_address(port))
 344                 insb(port & PIO_MASK, vaddr, count);
 345         else
 346 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 347                 __raw_readsb(addr, vaddr, count);
 348 #else
 349                 __indirect_readsb(addr, vaddr, count);
 350 #endif
 351 }
 352
 353 #define ioread16(p)                     ioread16(p)
 354 static inline unsigned int ioread16(const void __iomem *addr)
 355 {
 356         unsigned long port = (unsigned long __force)addr;
 357         if (__is_io_address(port))
 358                 return  (unsigned int)inw(port & PIO_MASK);
 359         else
 360 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 361                 return le16_to_cpu((__force __le16)__raw_readw(addr));
 362 #else
 363                 return (unsigned int)__indirect_readw(addr);
 364 #endif
 365 }
 366
 367 #define ioread16_rep(p, v, c)           ioread16_rep(p, v, c)
 368 static inline void ioread16_rep(const void __iomem *addr, void *vaddr,
 369                                 u32 count)
 370 {
 371         unsigned long port = (unsigned long __force)addr;
 372         if (__is_io_address(port))
 373                 insw(port & PIO_MASK, vaddr, count);
 374         else
 375 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 376                 __raw_readsw(addr, vaddr, count);
 377 #else
 378                 __indirect_readsw(addr, vaddr, count);
 379 #endif
 380 }
 381
 382 #define ioread32(p)                     ioread32(p)
 383 static inline unsigned int ioread32(const void __iomem *addr)
 384 {
 385         unsigned long port = (unsigned long __force)addr;
 386         if (__is_io_address(port))
 387                 return  (unsigned int)inl(port & PIO_MASK);
 388         else {
 389 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 390                 return le32_to_cpu((__force __le32)__raw_readl(addr));
 391 #else
 392                 return (unsigned int)__indirect_readl(addr);
 393 #endif
 394         }
 395 }
 396
 397 #define ioread32_rep(p, v, c)           ioread32_rep(p, v, c)
 398 static inline void ioread32_rep(const void __iomem *addr, void *vaddr,
 399                                 u32 count)
 400 {
 401         unsigned long port = (unsigned long __force)addr;
 402         if (__is_io_address(port))
 403                 insl(port & PIO_MASK, vaddr, count);
 404         else
 405 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 406                 __raw_readsl(addr, vaddr, count);
 407 #else
 408                 __indirect_readsl(addr, vaddr, count);
 409 #endif
 410 }
 411
 412 #define iowrite8(v, p)                  iowrite8(v, p)
 413 static inline void iowrite8(u8 value, void __iomem *addr)
 414 {
 415         unsigned long port = (unsigned long __force)addr;
 416         if (__is_io_address(port))
 417                 outb(value, port & PIO_MASK);
 418         else
 419 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 420                 __raw_writeb(value, addr);
 421 #else
 422                 __indirect_writeb(value, addr);
 423 #endif
 424 }
 425
 426 #define iowrite8_rep(p, v, c)           iowrite8_rep(p, v, c)
 427 static inline void iowrite8_rep(void __iomem *addr, const void *vaddr,
 428                                 u32 count)
 429 {
 430         unsigned long port = (unsigned long __force)addr;
 431         if (__is_io_address(port))
 432                 outsb(port & PIO_MASK, vaddr, count);
 433         else
 434 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 435                 __raw_writesb(addr, vaddr, count);
 436 #else
 437                 __indirect_writesb(addr, vaddr, count);
 438 #endif
 439 }
 440
 441 #define iowrite16(v, p)                 iowrite16(v, p)
 442 static inline void iowrite16(u16 value, void __iomem *addr)
 443 {
 444         unsigned long port = (unsigned long __force)addr;
 445         if (__is_io_address(port))
 446                 outw(value, port & PIO_MASK);
 447         else
 448 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 449                 __raw_writew(cpu_to_le16(value), addr);
 450 #else
 451                 __indirect_writew(value, addr);
 452 #endif
 453 }
 454
 455 #define iowrite16_rep(p, v, c)          iowrite16_rep(p, v, c)
 456 static inline void iowrite16_rep(void __iomem *addr, const void *vaddr,
 457                                  u32 count)
 458 {
 459         unsigned long port = (unsigned long __force)addr;
 460         if (__is_io_address(port))
 461                 outsw(port & PIO_MASK, vaddr, count);
 462         else
 463 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 464                 __raw_writesw(addr, vaddr, count);
 465 #else
 466                 __indirect_writesw(addr, vaddr, count);
 467 #endif
 468 }
 469
 470 #define iowrite32(v, p)                 iowrite32(v, p)
 471 static inline void iowrite32(u32 value, void __iomem *addr)
 472 {
 473         unsigned long port = (unsigned long __force)addr;
 474         if (__is_io_address(port))
 475                 outl(value, port & PIO_MASK);
 476         else
 477 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 478                 __raw_writel((u32 __force)cpu_to_le32(value), addr);
 479 #else
 480                 __indirect_writel(value, addr);
 481 #endif
 482 }
 483
 484 #define iowrite32_rep(p, v, c)          iowrite32_rep(p, v, c)
 485 static inline void iowrite32_rep(void __iomem *addr, const void *vaddr,
 486                                  u32 count)
 487 {
 488         unsigned long port = (unsigned long __force)addr;
 489         if (__is_io_address(port))
 490                 outsl(port & PIO_MASK, vaddr, count);
 491         else
 492 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 493                 __raw_writesl(addr, vaddr, count);
 494 #else
 495                 __indirect_writesl(addr, vaddr, count);
 496 #endif
 497 }
 498
 499 #define ioport_map(port, nr)            ((void __iomem*)(port + PIO_OFFSET))
 500 #define ioport_unmap(addr)
 501 #endif /* CONFIG_PCI */
 502
 503 #endif /* __ASM_ARM_ARCH_IO_H */