| blob | cd1c724869c7eff671e9c43c559c08998d3fde56 |
1 /*
2 * Hardware definitions for TI OMAP1610/5912/1710 processors.
3 *
4 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
27 #ifndef __ASM_ARCH_OMAP16XX_H
28 #define __ASM_ARCH_OMAP16XX_H
30 /*
31 * ----------------------------------------------------------------------------
32 * Base addresses
33 * ----------------------------------------------------------------------------
34 */
36 /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
38 #define OMAP16XX_DSP_BASE 0xE0000000
39 #define OMAP16XX_DSP_SIZE 0x28000
40 #define OMAP16XX_DSP_START 0xE0000000
42 #define OMAP16XX_DSPREG_BASE 0xE1000000
43 #define OMAP16XX_DSPREG_SIZE SZ_128K
44 #define OMAP16XX_DSPREG_START 0xE1000000
46 #define OMAP16XX_SEC_BASE 0xFFFE4000
47 #define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
48 #define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
49 #define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
51 /*
52 * ---------------------------------------------------------------------------
53 * Interrupts
54 * ---------------------------------------------------------------------------
55 */
56 #define OMAP_IH2_0_BASE (0xfffe0000)
57 #define OMAP_IH2_1_BASE (0xfffe0100)
58 #define OMAP_IH2_2_BASE (0xfffe0200)
59 #define OMAP_IH2_3_BASE (0xfffe0300)
61 #define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
62 #define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
63 #define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
64 #define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
65 #define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
66 #define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
67 #define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
69 #define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
70 #define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
71 #define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
72 #define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
73 #define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
74 #define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
75 #define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
77 #define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
78 #define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
79 #define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
80 #define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
81 #define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
82 #define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
83 #define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
85 #define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
86 #define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
87 #define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
88 #define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
89 #define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
90 #define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
91 #define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
93 /*
94 * ----------------------------------------------------------------------------
95 * Clocks
96 * ----------------------------------------------------------------------------
97 */
98 #define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
100 /*
101 * ----------------------------------------------------------------------------
102 * Pin configuration registers
103 * ----------------------------------------------------------------------------
104 */
105 #define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8)
106 #define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9)
107 #define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10)
108 #define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11)
109 #define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13)
111 /*
112 * ----------------------------------------------------------------------------
113 * System control registers
114 * ----------------------------------------------------------------------------
115 */
116 #define OMAP1610_RESET_CONTROL 0xfffe1140
118 /*
119 * ---------------------------------------------------------------------------
120 * TIPB bus interface
121 * ---------------------------------------------------------------------------
122 */
123 #define TIPB_SWITCH_BASE (0xfffbc800)
124 #define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
126 /* UART3 Registers Mapping through MPU bus */
127 #define UART3_RHR (OMAP1_UART3_BASE + 0)
128 #define UART3_THR (OMAP1_UART3_BASE + 0)
129 #define UART3_DLL (OMAP1_UART3_BASE + 0)
130 #define UART3_IER (OMAP1_UART3_BASE + 4)
131 #define UART3_DLH (OMAP1_UART3_BASE + 4)
132 #define UART3_IIR (OMAP1_UART3_BASE + 8)
133 #define UART3_FCR (OMAP1_UART3_BASE + 8)
134 #define UART3_EFR (OMAP1_UART3_BASE + 8)
135 #define UART3_LCR (OMAP1_UART3_BASE + 0x0C)
136 #define UART3_MCR (OMAP1_UART3_BASE + 0x10)
137 #define UART3_XON1_ADDR1 (OMAP1_UART3_BASE + 0x10)
138 #define UART3_XON2_ADDR2 (OMAP1_UART3_BASE + 0x14)
139 #define UART3_LSR (OMAP1_UART3_BASE + 0x14)
140 #define UART3_TCR (OMAP1_UART3_BASE + 0x18)
141 #define UART3_MSR (OMAP1_UART3_BASE + 0x18)
142 #define UART3_XOFF1 (OMAP1_UART3_BASE + 0x18)
143 #define UART3_XOFF2 (OMAP1_UART3_BASE + 0x1C)
144 #define UART3_SPR (OMAP1_UART3_BASE + 0x1C)
145 #define UART3_TLR (OMAP1_UART3_BASE + 0x1C)
146 #define UART3_MDR1 (OMAP1_UART3_BASE + 0x20)
147 #define UART3_MDR2 (OMAP1_UART3_BASE + 0x24)
148 #define UART3_SFLSR (OMAP1_UART3_BASE + 0x28)
149 #define UART3_TXFLL (OMAP1_UART3_BASE + 0x28)
150 #define UART3_RESUME (OMAP1_UART3_BASE + 0x2C)
151 #define UART3_TXFLH (OMAP1_UART3_BASE + 0x2C)
152 #define UART3_SFREGL (OMAP1_UART3_BASE + 0x30)
153 #define UART3_RXFLL (OMAP1_UART3_BASE + 0x30)
154 #define UART3_SFREGH (OMAP1_UART3_BASE + 0x34)
155 #define UART3_RXFLH (OMAP1_UART3_BASE + 0x34)
156 #define UART3_BLR (OMAP1_UART3_BASE + 0x38)
157 #define UART3_ACREG (OMAP1_UART3_BASE + 0x3C)
158 #define UART3_DIV16 (OMAP1_UART3_BASE + 0x3C)
159 #define UART3_SCR (OMAP1_UART3_BASE + 0x40)
160 #define UART3_SSR (OMAP1_UART3_BASE + 0x44)
161 #define UART3_EBLR (OMAP1_UART3_BASE + 0x48)
162 #define UART3_OSC_12M_SEL (OMAP1_UART3_BASE + 0x4C)
163 #define UART3_MVR (OMAP1_UART3_BASE + 0x50)
165 /*
166 * ---------------------------------------------------------------------------
167 * Watchdog timer
168 * ---------------------------------------------------------------------------
169 */
171 /* 32-bit Watchdog timer in OMAP 16XX */
172 #define OMAP_16XX_WATCHDOG_BASE (0xfffeb000)
173 #define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00)
174 #define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
175 #define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
176 #define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24)
177 #define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28)
178 #define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c)
179 #define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30)
180 #define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34)
181 #define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48)
183 #define WCLR_PRE_SHIFT 5
184 #define WCLR_PTV_SHIFT 2
186 #define WWPS_W_PEND_WSPR (1 << 4)
187 #define WWPS_W_PEND_WTGR (1 << 3)
188 #define WWPS_W_PEND_WLDR (1 << 2)
189 #define WWPS_W_PEND_WCRR (1 << 1)
190 #define WWPS_W_PEND_WCLR (1 << 0)
192 #define WSPR_ENABLE_0 (0x0000bbbb)
193 #define WSPR_ENABLE_1 (0x00004444)
194 #define WSPR_DISABLE_0 (0x0000aaaa)
195 #define WSPR_DISABLE_1 (0x00005555)
197 #define OMAP16XX_DSP_MMU_BASE (0xfffed200)
198 #define OMAP16XX_MAILBOX_BASE (0xfffcf000)