4 * Copyright (C) 2007-2012 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation
7 * Written by Paul Walmsley
8 * Updated to COMMON clk data format by Rajendra Nayak <rnayak@ti.com>
9 * With many device clock fixes by Kevin Hilman and Jouni Högander
10 * DPLL bypass clock support added by Roman Tereshonkov
15 * Virtual clocks are introduced as convenient tools.
16 * They are sources for other clocks and not supposed
17 * to be requested from drivers directly.
20 #include <linux/kernel.h>
21 #include <linux/clk.h>
22 #include <linux/clk-private.h>
23 #include <linux/list.h>
29 #include "clock3xxx.h"
30 #include "clock34xx.h"
31 #include "clock36xx.h"
32 #include "clock3517.h"
34 #include "cm-regbits-34xx.h"
36 #include "prm-regbits-34xx.h"
43 #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
45 /* Maximum DPLL multiplier, divider values for OMAP3 */
46 #define OMAP3_MAX_DPLL_MULT 2047
47 #define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
48 #define OMAP3_MAX_DPLL_DIV 128
50 DEFINE_CLK_FIXED_RATE(dummy_apb_pclk
, CLK_IS_ROOT
, 0x0, 0x0);
52 DEFINE_CLK_FIXED_RATE(mcbsp_clks
, CLK_IS_ROOT
, 0x0, 0x0);
54 DEFINE_CLK_FIXED_RATE(omap_32k_fck
, CLK_IS_ROOT
, 32768, 0x0);
56 DEFINE_CLK_FIXED_RATE(pclk_ck
, CLK_IS_ROOT
, 27000000, 0x0);
58 DEFINE_CLK_FIXED_RATE(rmii_ck
, CLK_IS_ROOT
, 50000000, 0x0);
60 DEFINE_CLK_FIXED_RATE(secure_32k_fck
, CLK_IS_ROOT
, 32768, 0x0);
62 DEFINE_CLK_FIXED_RATE(sys_altclk
, CLK_IS_ROOT
, 0x0, 0x0);
64 DEFINE_CLK_FIXED_RATE(virt_12m_ck
, CLK_IS_ROOT
, 12000000, 0x0);
66 DEFINE_CLK_FIXED_RATE(virt_13m_ck
, CLK_IS_ROOT
, 13000000, 0x0);
68 DEFINE_CLK_FIXED_RATE(virt_16_8m_ck
, CLK_IS_ROOT
, 16800000, 0x0);
70 DEFINE_CLK_FIXED_RATE(virt_19200000_ck
, CLK_IS_ROOT
, 19200000, 0x0);
72 DEFINE_CLK_FIXED_RATE(virt_26000000_ck
, CLK_IS_ROOT
, 26000000, 0x0);
74 DEFINE_CLK_FIXED_RATE(virt_38_4m_ck
, CLK_IS_ROOT
, 38400000, 0x0);
76 static const char *osc_sys_ck_parent_names
[] = {
77 "virt_12m_ck", "virt_13m_ck", "virt_19200000_ck", "virt_26000000_ck",
78 "virt_38_4m_ck", "virt_16_8m_ck",
81 DEFINE_CLK_MUX(osc_sys_ck
, osc_sys_ck_parent_names
, NULL
, 0x0,
82 OMAP3430_PRM_CLKSEL
, OMAP3430_SYS_CLKIN_SEL_SHIFT
,
83 OMAP3430_SYS_CLKIN_SEL_WIDTH
, 0x0, NULL
);
85 DEFINE_CLK_DIVIDER(sys_ck
, "osc_sys_ck", &osc_sys_ck
, 0x0,
86 OMAP3430_PRM_CLKSRC_CTRL
, OMAP_SYSCLKDIV_SHIFT
,
87 OMAP_SYSCLKDIV_WIDTH
, CLK_DIVIDER_ONE_BASED
, NULL
);
89 static struct dpll_data dpll3_dd
= {
90 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
91 .mult_mask
= OMAP3430_CORE_DPLL_MULT_MASK
,
92 .div1_mask
= OMAP3430_CORE_DPLL_DIV_MASK
,
93 .clk_bypass
= &sys_ck
,
95 .freqsel_mask
= OMAP3430_CORE_DPLL_FREQSEL_MASK
,
96 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
97 .enable_mask
= OMAP3430_EN_CORE_DPLL_MASK
,
98 .auto_recal_bit
= OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT
,
99 .recal_en_bit
= OMAP3430_CORE_DPLL_RECAL_EN_SHIFT
,
100 .recal_st_bit
= OMAP3430_CORE_DPLL_ST_SHIFT
,
101 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_AUTOIDLE
),
102 .autoidle_mask
= OMAP3430_AUTO_CORE_DPLL_MASK
,
103 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST
),
104 .idlest_mask
= OMAP3430_ST_CORE_CLK_MASK
,
105 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
107 .max_divider
= OMAP3_MAX_DPLL_DIV
,
110 static struct clk dpll3_ck
;
112 static const char *dpll3_ck_parent_names
[] = {
116 static const struct clk_ops dpll3_ck_ops
= {
117 .init
= &omap2_init_clk_clkdm
,
118 .get_parent
= &omap2_init_dpll_parent
,
119 .recalc_rate
= &omap3_dpll_recalc
,
120 .round_rate
= &omap2_dpll_round_rate
,
123 static struct clk_hw_omap dpll3_ck_hw
= {
127 .ops
= &clkhwops_omap3_dpll
,
128 .dpll_data
= &dpll3_dd
,
129 .clkdm_name
= "dpll3_clkdm",
132 DEFINE_STRUCT_CLK(dpll3_ck
, dpll3_ck_parent_names
, dpll3_ck_ops
);
134 DEFINE_CLK_DIVIDER(dpll3_m2_ck
, "dpll3_ck", &dpll3_ck
, 0x0,
135 OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
136 OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT
,
137 OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH
,
138 CLK_DIVIDER_ONE_BASED
, NULL
);
140 static struct clk core_ck
;
142 static const char *core_ck_parent_names
[] = {
146 static const struct clk_ops core_ck_ops
= {};
148 DEFINE_STRUCT_CLK_HW_OMAP(core_ck
, NULL
);
149 DEFINE_STRUCT_CLK(core_ck
, core_ck_parent_names
, core_ck_ops
);
151 DEFINE_CLK_DIVIDER(l3_ick
, "core_ck", &core_ck
, 0x0,
152 OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
153 OMAP3430_CLKSEL_L3_SHIFT
, OMAP3430_CLKSEL_L3_WIDTH
,
154 CLK_DIVIDER_ONE_BASED
, NULL
);
156 DEFINE_CLK_DIVIDER(l4_ick
, "l3_ick", &l3_ick
, 0x0,
157 OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
158 OMAP3430_CLKSEL_L4_SHIFT
, OMAP3430_CLKSEL_L4_WIDTH
,
159 CLK_DIVIDER_ONE_BASED
, NULL
);
161 static struct clk security_l4_ick2
;
163 static const char *security_l4_ick2_parent_names
[] = {
167 DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2
, NULL
);
168 DEFINE_STRUCT_CLK(security_l4_ick2
, security_l4_ick2_parent_names
, core_ck_ops
);
170 static struct clk aes1_ick
;
172 static const char *aes1_ick_parent_names
[] = {
176 static const struct clk_ops aes1_ick_ops
= {
177 .enable
= &omap2_dflt_clk_enable
,
178 .disable
= &omap2_dflt_clk_disable
,
179 .is_enabled
= &omap2_dflt_clk_is_enabled
,
182 static struct clk_hw_omap aes1_ick_hw
= {
186 .ops
= &clkhwops_iclk_wait
,
187 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
188 .enable_bit
= OMAP3430_EN_AES1_SHIFT
,
191 DEFINE_STRUCT_CLK(aes1_ick
, aes1_ick_parent_names
, aes1_ick_ops
);
193 static struct clk core_l4_ick
;
195 static const struct clk_ops core_l4_ick_ops
= {
196 .init
= &omap2_init_clk_clkdm
,
199 DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick
, "core_l4_clkdm");
200 DEFINE_STRUCT_CLK(core_l4_ick
, security_l4_ick2_parent_names
, core_l4_ick_ops
);
202 static struct clk aes2_ick
;
204 static const char *aes2_ick_parent_names
[] = {
208 static const struct clk_ops aes2_ick_ops
= {
209 .init
= &omap2_init_clk_clkdm
,
210 .enable
= &omap2_dflt_clk_enable
,
211 .disable
= &omap2_dflt_clk_disable
,
212 .is_enabled
= &omap2_dflt_clk_is_enabled
,
215 static struct clk_hw_omap aes2_ick_hw
= {
219 .ops
= &clkhwops_iclk_wait
,
220 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
221 .enable_bit
= OMAP3430_EN_AES2_SHIFT
,
222 .clkdm_name
= "core_l4_clkdm",
225 DEFINE_STRUCT_CLK(aes2_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
227 static struct clk dpll1_fck
;
229 static struct dpll_data dpll1_dd
= {
230 .mult_div1_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
231 .mult_mask
= OMAP3430_MPU_DPLL_MULT_MASK
,
232 .div1_mask
= OMAP3430_MPU_DPLL_DIV_MASK
,
233 .clk_bypass
= &dpll1_fck
,
235 .freqsel_mask
= OMAP3430_MPU_DPLL_FREQSEL_MASK
,
236 .control_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKEN_PLL
),
237 .enable_mask
= OMAP3430_EN_MPU_DPLL_MASK
,
238 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
239 .auto_recal_bit
= OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT
,
240 .recal_en_bit
= OMAP3430_MPU_DPLL_RECAL_EN_SHIFT
,
241 .recal_st_bit
= OMAP3430_MPU_DPLL_ST_SHIFT
,
242 .autoidle_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_AUTOIDLE_PLL
),
243 .autoidle_mask
= OMAP3430_AUTO_MPU_DPLL_MASK
,
244 .idlest_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_IDLEST_PLL
),
245 .idlest_mask
= OMAP3430_ST_MPU_CLK_MASK
,
246 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
248 .max_divider
= OMAP3_MAX_DPLL_DIV
,
251 static struct clk dpll1_ck
;
253 static const struct clk_ops dpll1_ck_ops
= {
254 .init
= &omap2_init_clk_clkdm
,
255 .enable
= &omap3_noncore_dpll_enable
,
256 .disable
= &omap3_noncore_dpll_disable
,
257 .get_parent
= &omap2_init_dpll_parent
,
258 .recalc_rate
= &omap3_dpll_recalc
,
259 .set_rate
= &omap3_noncore_dpll_set_rate
,
260 .round_rate
= &omap2_dpll_round_rate
,
263 static struct clk_hw_omap dpll1_ck_hw
= {
267 .ops
= &clkhwops_omap3_dpll
,
268 .dpll_data
= &dpll1_dd
,
269 .clkdm_name
= "dpll1_clkdm",
272 DEFINE_STRUCT_CLK(dpll1_ck
, dpll3_ck_parent_names
, dpll1_ck_ops
);
274 DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck
, "dpll1_ck", &dpll1_ck
, 0x0, 2, 1);
276 DEFINE_CLK_DIVIDER(dpll1_x2m2_ck
, "dpll1_x2_ck", &dpll1_x2_ck
, 0x0,
277 OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKSEL2_PLL
),
278 OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT
,
279 OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH
,
280 CLK_DIVIDER_ONE_BASED
, NULL
);
282 static struct clk mpu_ck
;
284 static const char *mpu_ck_parent_names
[] = {
288 DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck
, "mpu_clkdm");
289 DEFINE_STRUCT_CLK(mpu_ck
, mpu_ck_parent_names
, core_l4_ick_ops
);
291 DEFINE_CLK_DIVIDER(arm_fck
, "mpu_ck", &mpu_ck
, 0x0,
292 OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_IDLEST_PLL
),
293 OMAP3430_ST_MPU_CLK_SHIFT
, OMAP3430_ST_MPU_CLK_WIDTH
,
296 static struct clk cam_ick
;
298 static struct clk_hw_omap cam_ick_hw
= {
302 .ops
= &clkhwops_iclk
,
303 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_ICLKEN
),
304 .enable_bit
= OMAP3430_EN_CAM_SHIFT
,
305 .clkdm_name
= "cam_clkdm",
308 DEFINE_STRUCT_CLK(cam_ick
, security_l4_ick2_parent_names
, aes2_ick_ops
);
311 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
313 static struct dpll_data dpll4_dd
;
315 static struct dpll_data dpll4_dd_34xx __initdata
= {
316 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL2
),
317 .mult_mask
= OMAP3430_PERIPH_DPLL_MULT_MASK
,
318 .div1_mask
= OMAP3430_PERIPH_DPLL_DIV_MASK
,
319 .clk_bypass
= &sys_ck
,
321 .freqsel_mask
= OMAP3430_PERIPH_DPLL_FREQSEL_MASK
,
322 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
323 .enable_mask
= OMAP3430_EN_PERIPH_DPLL_MASK
,
324 .modes
= (1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
),
325 .auto_recal_bit
= OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT
,
326 .recal_en_bit
= OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT
,
327 .recal_st_bit
= OMAP3430_PERIPH_DPLL_ST_SHIFT
,
328 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_AUTOIDLE
),
329 .autoidle_mask
= OMAP3430_AUTO_PERIPH_DPLL_MASK
,
330 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST
),
331 .idlest_mask
= OMAP3430_ST_PERIPH_CLK_MASK
,
332 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
334 .max_divider
= OMAP3_MAX_DPLL_DIV
,
337 static struct dpll_data dpll4_dd_3630 __initdata
= {
338 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL2
),
339 .mult_mask
= OMAP3630_PERIPH_DPLL_MULT_MASK
,
340 .div1_mask
= OMAP3430_PERIPH_DPLL_DIV_MASK
,
341 .clk_bypass
= &sys_ck
,
343 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
344 .enable_mask
= OMAP3430_EN_PERIPH_DPLL_MASK
,
345 .modes
= (1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
),
346 .auto_recal_bit
= OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT
,
347 .recal_en_bit
= OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT
,
348 .recal_st_bit
= OMAP3430_PERIPH_DPLL_ST_SHIFT
,
349 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_AUTOIDLE
),
350 .autoidle_mask
= OMAP3430_AUTO_PERIPH_DPLL_MASK
,
351 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST
),
352 .idlest_mask
= OMAP3430_ST_PERIPH_CLK_MASK
,
353 .dco_mask
= OMAP3630_PERIPH_DPLL_DCO_SEL_MASK
,
354 .sddiv_mask
= OMAP3630_PERIPH_DPLL_SD_DIV_MASK
,
355 .max_multiplier
= OMAP3630_MAX_JTYPE_DPLL_MULT
,
357 .max_divider
= OMAP3_MAX_DPLL_DIV
,
361 static struct clk dpll4_ck
;
363 static const struct clk_ops dpll4_ck_ops
= {
364 .init
= &omap2_init_clk_clkdm
,
365 .enable
= &omap3_noncore_dpll_enable
,
366 .disable
= &omap3_noncore_dpll_disable
,
367 .get_parent
= &omap2_init_dpll_parent
,
368 .recalc_rate
= &omap3_dpll_recalc
,
369 .set_rate
= &omap3_dpll4_set_rate
,
370 .round_rate
= &omap2_dpll_round_rate
,
373 static struct clk_hw_omap dpll4_ck_hw
= {
377 .dpll_data
= &dpll4_dd
,
378 .ops
= &clkhwops_omap3_dpll
,
379 .clkdm_name
= "dpll4_clkdm",
382 DEFINE_STRUCT_CLK(dpll4_ck
, dpll3_ck_parent_names
, dpll4_ck_ops
);
384 static const struct clk_div_table dpll4_mx_ck_div_table
[] = {
385 { .div
= 1, .val
= 1 },
386 { .div
= 2, .val
= 2 },
387 { .div
= 3, .val
= 3 },
388 { .div
= 4, .val
= 4 },
389 { .div
= 5, .val
= 5 },
390 { .div
= 6, .val
= 6 },
391 { .div
= 7, .val
= 7 },
392 { .div
= 8, .val
= 8 },
393 { .div
= 9, .val
= 9 },
394 { .div
= 10, .val
= 10 },
395 { .div
= 11, .val
= 11 },
396 { .div
= 12, .val
= 12 },
397 { .div
= 13, .val
= 13 },
398 { .div
= 14, .val
= 14 },
399 { .div
= 15, .val
= 15 },
400 { .div
= 16, .val
= 16 },
401 { .div
= 17, .val
= 17 },
402 { .div
= 18, .val
= 18 },
403 { .div
= 19, .val
= 19 },
404 { .div
= 20, .val
= 20 },
405 { .div
= 21, .val
= 21 },
406 { .div
= 22, .val
= 22 },
407 { .div
= 23, .val
= 23 },
408 { .div
= 24, .val
= 24 },
409 { .div
= 25, .val
= 25 },
410 { .div
= 26, .val
= 26 },
411 { .div
= 27, .val
= 27 },
412 { .div
= 28, .val
= 28 },
413 { .div
= 29, .val
= 29 },
414 { .div
= 30, .val
= 30 },
415 { .div
= 31, .val
= 31 },
416 { .div
= 32, .val
= 32 },
420 DEFINE_CLK_DIVIDER(dpll4_m5_ck
, "dpll4_ck", &dpll4_ck
, 0x0,
421 OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_CLKSEL
),
422 OMAP3430_CLKSEL_CAM_SHIFT
, OMAP3630_CLKSEL_CAM_WIDTH
,
423 CLK_DIVIDER_ONE_BASED
, NULL
);
425 static struct clk dpll4_m5x2_ck
;
427 static const char *dpll4_m5x2_ck_parent_names
[] = {
431 static const struct clk_ops dpll4_m5x2_ck_ops
= {
432 .init
= &omap2_init_clk_clkdm
,
433 .enable
= &omap2_dflt_clk_enable
,
434 .disable
= &omap2_dflt_clk_disable
,
435 .is_enabled
= &omap2_dflt_clk_is_enabled
,
436 .set_rate
= &omap3_clkoutx2_set_rate
,
437 .recalc_rate
= &omap3_clkoutx2_recalc
,
438 .round_rate
= &omap3_clkoutx2_round_rate
,
441 static const struct clk_ops dpll4_m5x2_ck_3630_ops
= {
442 .init
= &omap2_init_clk_clkdm
,
443 .enable
= &omap36xx_pwrdn_clk_enable_with_hsdiv_restore
,
444 .disable
= &omap2_dflt_clk_disable
,
445 .recalc_rate
= &omap3_clkoutx2_recalc
,
448 static struct clk_hw_omap dpll4_m5x2_ck_hw
= {
450 .clk
= &dpll4_m5x2_ck
,
452 .ops
= &clkhwops_wait
,
453 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
454 .enable_bit
= OMAP3430_PWRDN_CAM_SHIFT
,
455 .flags
= INVERT_ENABLE
,
456 .clkdm_name
= "dpll4_clkdm",
459 DEFINE_STRUCT_CLK_FLAGS(dpll4_m5x2_ck
, dpll4_m5x2_ck_parent_names
,
460 dpll4_m5x2_ck_ops
, CLK_SET_RATE_PARENT
);
462 static struct clk dpll4_m5x2_ck_3630
= {
463 .name
= "dpll4_m5x2_ck",
464 .hw
= &dpll4_m5x2_ck_hw
.hw
,
465 .parent_names
= dpll4_m5x2_ck_parent_names
,
466 .num_parents
= ARRAY_SIZE(dpll4_m5x2_ck_parent_names
),
467 .ops
= &dpll4_m5x2_ck_3630_ops
,
468 .flags
= CLK_SET_RATE_PARENT
,
471 static struct clk cam_mclk
;
473 static const char *cam_mclk_parent_names
[] = {
477 static struct clk_hw_omap cam_mclk_hw
= {
481 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_FCLKEN
),
482 .enable_bit
= OMAP3430_EN_CAM_SHIFT
,
483 .clkdm_name
= "cam_clkdm",
486 static struct clk cam_mclk
= {
488 .hw
= &cam_mclk_hw
.hw
,
489 .parent_names
= cam_mclk_parent_names
,
490 .num_parents
= ARRAY_SIZE(cam_mclk_parent_names
),
491 .ops
= &aes2_ick_ops
,
492 .flags
= CLK_SET_RATE_PARENT
,
495 static const struct clksel_rate clkout2_src_core_rates
[] = {
496 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
500 static const struct clksel_rate clkout2_src_sys_rates
[] = {
501 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
505 static const struct clksel_rate clkout2_src_96m_rates
[] = {
506 { .div
= 1, .val
= 2, .flags
= RATE_IN_3XXX
},
510 DEFINE_CLK_DIVIDER(dpll4_m2_ck
, "dpll4_ck", &dpll4_ck
, 0x0,
511 OMAP_CM_REGADDR(PLL_MOD
, OMAP3430_CM_CLKSEL3
),
512 OMAP3430_DIV_96M_SHIFT
, OMAP3630_DIV_96M_WIDTH
,
513 CLK_DIVIDER_ONE_BASED
, NULL
);
515 static struct clk dpll4_m2x2_ck
;
517 static const char *dpll4_m2x2_ck_parent_names
[] = {
521 static struct clk_hw_omap dpll4_m2x2_ck_hw
= {
523 .clk
= &dpll4_m2x2_ck
,
525 .ops
= &clkhwops_wait
,
526 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
527 .enable_bit
= OMAP3430_PWRDN_96M_SHIFT
,
528 .flags
= INVERT_ENABLE
,
529 .clkdm_name
= "dpll4_clkdm",
532 DEFINE_STRUCT_CLK(dpll4_m2x2_ck
, dpll4_m2x2_ck_parent_names
, dpll4_m5x2_ck_ops
);
534 static struct clk dpll4_m2x2_ck_3630
= {
535 .name
= "dpll4_m2x2_ck",
536 .hw
= &dpll4_m2x2_ck_hw
.hw
,
537 .parent_names
= dpll4_m2x2_ck_parent_names
,
538 .num_parents
= ARRAY_SIZE(dpll4_m2x2_ck_parent_names
),
539 .ops
= &dpll4_m5x2_ck_3630_ops
,
542 static struct clk omap_96m_alwon_fck
;
544 static const char *omap_96m_alwon_fck_parent_names
[] = {
548 DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck
, NULL
);
549 DEFINE_STRUCT_CLK(omap_96m_alwon_fck
, omap_96m_alwon_fck_parent_names
,
552 static struct clk cm_96m_fck
;
554 static const char *cm_96m_fck_parent_names
[] = {
555 "omap_96m_alwon_fck",
558 DEFINE_STRUCT_CLK_HW_OMAP(cm_96m_fck
, NULL
);
559 DEFINE_STRUCT_CLK(cm_96m_fck
, cm_96m_fck_parent_names
, core_ck_ops
);
561 static const struct clksel_rate clkout2_src_54m_rates
[] = {
562 { .div
= 1, .val
= 3, .flags
= RATE_IN_3XXX
},
566 DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck
, "dpll4_ck", &dpll4_ck
, 0x0,
567 OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_CLKSEL
),
568 OMAP3430_CLKSEL_TV_SHIFT
, OMAP3630_CLKSEL_TV_WIDTH
,
569 0, dpll4_mx_ck_div_table
, NULL
);
571 static struct clk dpll4_m3x2_ck
;
573 static const char *dpll4_m3x2_ck_parent_names
[] = {
577 static struct clk_hw_omap dpll4_m3x2_ck_hw
= {
579 .clk
= &dpll4_m3x2_ck
,
581 .ops
= &clkhwops_wait
,
582 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
583 .enable_bit
= OMAP3430_PWRDN_TV_SHIFT
,
584 .flags
= INVERT_ENABLE
,
585 .clkdm_name
= "dpll4_clkdm",
588 DEFINE_STRUCT_CLK(dpll4_m3x2_ck
, dpll4_m3x2_ck_parent_names
, dpll4_m5x2_ck_ops
);
590 static struct clk dpll4_m3x2_ck_3630
= {
591 .name
= "dpll4_m3x2_ck",
592 .hw
= &dpll4_m3x2_ck_hw
.hw
,
593 .parent_names
= dpll4_m3x2_ck_parent_names
,
594 .num_parents
= ARRAY_SIZE(dpll4_m3x2_ck_parent_names
),
595 .ops
= &dpll4_m5x2_ck_3630_ops
,
598 static const char *omap_54m_fck_parent_names
[] = {
599 "dpll4_m3x2_ck", "sys_altclk",
602 DEFINE_CLK_MUX(omap_54m_fck
, omap_54m_fck_parent_names
, NULL
, 0x0,
603 OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
), OMAP3430_SOURCE_54M_SHIFT
,
604 OMAP3430_SOURCE_54M_WIDTH
, 0x0, NULL
);
606 static const struct clksel clkout2_src_clksel
[] = {
607 { .parent
= &core_ck
, .rates
= clkout2_src_core_rates
},
608 { .parent
= &sys_ck
, .rates
= clkout2_src_sys_rates
},
609 { .parent
= &cm_96m_fck
, .rates
= clkout2_src_96m_rates
},
610 { .parent
= &omap_54m_fck
, .rates
= clkout2_src_54m_rates
},
614 static const char *clkout2_src_ck_parent_names
[] = {
615 "core_ck", "sys_ck", "cm_96m_fck", "omap_54m_fck",
618 static const struct clk_ops clkout2_src_ck_ops
= {
619 .init
= &omap2_init_clk_clkdm
,
620 .enable
= &omap2_dflt_clk_enable
,
621 .disable
= &omap2_dflt_clk_disable
,
622 .is_enabled
= &omap2_dflt_clk_is_enabled
,
623 .recalc_rate
= &omap2_clksel_recalc
,
624 .get_parent
= &omap2_clksel_find_parent_index
,
625 .set_parent
= &omap2_clksel_set_parent
,
628 DEFINE_CLK_OMAP_MUX_GATE(clkout2_src_ck
, "core_clkdm",
629 clkout2_src_clksel
, OMAP3430_CM_CLKOUT_CTRL
,
630 OMAP3430_CLKOUT2SOURCE_MASK
,
631 OMAP3430_CM_CLKOUT_CTRL
, OMAP3430_CLKOUT2_EN_SHIFT
,
632 NULL
, clkout2_src_ck_parent_names
, clkout2_src_ck_ops
);
634 static const struct clksel_rate omap_48m_cm96m_rates
[] = {
635 { .div
= 2, .val
= 0, .flags
= RATE_IN_3XXX
},
639 static const struct clksel_rate omap_48m_alt_rates
[] = {
640 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
644 static const struct clksel omap_48m_clksel
[] = {
645 { .parent
= &cm_96m_fck
, .rates
= omap_48m_cm96m_rates
},
646 { .parent
= &sys_altclk
, .rates
= omap_48m_alt_rates
},
650 static const char *omap_48m_fck_parent_names
[] = {
651 "cm_96m_fck", "sys_altclk",
654 static struct clk omap_48m_fck
;
656 static const struct clk_ops omap_48m_fck_ops
= {
657 .recalc_rate
= &omap2_clksel_recalc
,
658 .get_parent
= &omap2_clksel_find_parent_index
,
659 .set_parent
= &omap2_clksel_set_parent
,
662 static struct clk_hw_omap omap_48m_fck_hw
= {
664 .clk
= &omap_48m_fck
,
666 .clksel
= omap_48m_clksel
,
667 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
668 .clksel_mask
= OMAP3430_SOURCE_48M_MASK
,
671 DEFINE_STRUCT_CLK(omap_48m_fck
, omap_48m_fck_parent_names
, omap_48m_fck_ops
);
673 DEFINE_CLK_FIXED_FACTOR(omap_12m_fck
, "omap_48m_fck", &omap_48m_fck
, 0x0, 1, 4);
675 static struct clk core_12m_fck
;
677 static const char *core_12m_fck_parent_names
[] = {
681 DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck
, "core_l4_clkdm");
682 DEFINE_STRUCT_CLK(core_12m_fck
, core_12m_fck_parent_names
, core_l4_ick_ops
);
684 static struct clk core_48m_fck
;
686 static const char *core_48m_fck_parent_names
[] = {
690 DEFINE_STRUCT_CLK_HW_OMAP(core_48m_fck
, "core_l4_clkdm");
691 DEFINE_STRUCT_CLK(core_48m_fck
, core_48m_fck_parent_names
, core_l4_ick_ops
);
693 static const char *omap_96m_fck_parent_names
[] = {
694 "cm_96m_fck", "sys_ck",
697 DEFINE_CLK_MUX(omap_96m_fck
, omap_96m_fck_parent_names
, NULL
, 0x0,
698 OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
699 OMAP3430_SOURCE_96M_SHIFT
, OMAP3430_SOURCE_96M_WIDTH
, 0x0, NULL
);
701 static struct clk core_96m_fck
;
703 static const char *core_96m_fck_parent_names
[] = {
707 DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck
, "core_l4_clkdm");
708 DEFINE_STRUCT_CLK(core_96m_fck
, core_96m_fck_parent_names
, core_l4_ick_ops
);
710 static struct clk core_l3_ick
;
712 static const char *core_l3_ick_parent_names
[] = {
716 DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick
, "core_l3_clkdm");
717 DEFINE_STRUCT_CLK(core_l3_ick
, core_l3_ick_parent_names
, core_l4_ick_ops
);
719 DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck
, "dpll3_m2_ck", &dpll3_m2_ck
, 0x0, 2, 1);
721 static struct clk corex2_fck
;
723 static const char *corex2_fck_parent_names
[] = {
727 DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck
, NULL
);
728 DEFINE_STRUCT_CLK(corex2_fck
, corex2_fck_parent_names
, core_ck_ops
);
730 static struct clk cpefuse_fck
;
732 static struct clk_hw_omap cpefuse_fck_hw
= {
736 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP3430ES2_CM_FCLKEN3
),
737 .enable_bit
= OMAP3430ES2_EN_CPEFUSE_SHIFT
,
738 .clkdm_name
= "core_l4_clkdm",
741 DEFINE_STRUCT_CLK(cpefuse_fck
, dpll3_ck_parent_names
, aes2_ick_ops
);
743 static struct clk csi2_96m_fck
;
745 static const char *csi2_96m_fck_parent_names
[] = {
749 static struct clk_hw_omap csi2_96m_fck_hw
= {
751 .clk
= &csi2_96m_fck
,
753 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_FCLKEN
),
754 .enable_bit
= OMAP3430_EN_CSI2_SHIFT
,
755 .clkdm_name
= "cam_clkdm",
758 DEFINE_STRUCT_CLK(csi2_96m_fck
, csi2_96m_fck_parent_names
, aes2_ick_ops
);
760 static struct clk d2d_26m_fck
;
762 static struct clk_hw_omap d2d_26m_fck_hw
= {
766 .ops
= &clkhwops_wait
,
767 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
768 .enable_bit
= OMAP3430ES1_EN_D2D_SHIFT
,
769 .clkdm_name
= "d2d_clkdm",
772 DEFINE_STRUCT_CLK(d2d_26m_fck
, dpll3_ck_parent_names
, aes2_ick_ops
);
774 static struct clk des1_ick
;
776 static struct clk_hw_omap des1_ick_hw
= {
780 .ops
= &clkhwops_iclk_wait
,
781 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
782 .enable_bit
= OMAP3430_EN_DES1_SHIFT
,
785 DEFINE_STRUCT_CLK(des1_ick
, aes1_ick_parent_names
, aes1_ick_ops
);
787 static struct clk des2_ick
;
789 static struct clk_hw_omap des2_ick_hw
= {
793 .ops
= &clkhwops_iclk_wait
,
794 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
795 .enable_bit
= OMAP3430_EN_DES2_SHIFT
,
796 .clkdm_name
= "core_l4_clkdm",
799 DEFINE_STRUCT_CLK(des2_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
801 DEFINE_CLK_DIVIDER(dpll1_fck
, "core_ck", &core_ck
, 0x0,
802 OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
803 OMAP3430_MPU_CLK_SRC_SHIFT
, OMAP3430_MPU_CLK_SRC_WIDTH
,
804 CLK_DIVIDER_ONE_BASED
, NULL
);
806 static struct clk dpll2_fck
;
808 static struct dpll_data dpll2_dd
= {
809 .mult_div1_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
810 .mult_mask
= OMAP3430_IVA2_DPLL_MULT_MASK
,
811 .div1_mask
= OMAP3430_IVA2_DPLL_DIV_MASK
,
812 .clk_bypass
= &dpll2_fck
,
814 .freqsel_mask
= OMAP3430_IVA2_DPLL_FREQSEL_MASK
,
815 .control_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKEN_PLL
),
816 .enable_mask
= OMAP3430_EN_IVA2_DPLL_MASK
,
817 .modes
= ((1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
) |
818 (1 << DPLL_LOW_POWER_BYPASS
)),
819 .auto_recal_bit
= OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT
,
820 .recal_en_bit
= OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT
,
821 .recal_st_bit
= OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT
,
822 .autoidle_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_AUTOIDLE_PLL
),
823 .autoidle_mask
= OMAP3430_AUTO_IVA2_DPLL_MASK
,
824 .idlest_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_IDLEST_PLL
),
825 .idlest_mask
= OMAP3430_ST_IVA2_CLK_MASK
,
826 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
828 .max_divider
= OMAP3_MAX_DPLL_DIV
,
831 static struct clk dpll2_ck
;
833 static struct clk_hw_omap dpll2_ck_hw
= {
837 .ops
= &clkhwops_omap3_dpll
,
838 .dpll_data
= &dpll2_dd
,
839 .clkdm_name
= "dpll2_clkdm",
842 DEFINE_STRUCT_CLK(dpll2_ck
, dpll3_ck_parent_names
, dpll1_ck_ops
);
844 DEFINE_CLK_DIVIDER(dpll2_fck
, "core_ck", &core_ck
, 0x0,
845 OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
846 OMAP3430_IVA2_CLK_SRC_SHIFT
, OMAP3430_IVA2_CLK_SRC_WIDTH
,
847 CLK_DIVIDER_ONE_BASED
, NULL
);
849 DEFINE_CLK_DIVIDER(dpll2_m2_ck
, "dpll2_ck", &dpll2_ck
, 0x0,
850 OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKSEL2_PLL
),
851 OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT
,
852 OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH
,
853 CLK_DIVIDER_ONE_BASED
, NULL
);
855 DEFINE_CLK_DIVIDER(dpll3_m3_ck
, "dpll3_ck", &dpll3_ck
, 0x0,
856 OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
857 OMAP3430_DIV_DPLL3_SHIFT
, OMAP3430_DIV_DPLL3_WIDTH
,
858 CLK_DIVIDER_ONE_BASED
, NULL
);
860 static struct clk dpll3_m3x2_ck
;
862 static const char *dpll3_m3x2_ck_parent_names
[] = {
866 static struct clk_hw_omap dpll3_m3x2_ck_hw
= {
868 .clk
= &dpll3_m3x2_ck
,
870 .ops
= &clkhwops_wait
,
871 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
872 .enable_bit
= OMAP3430_PWRDN_EMU_CORE_SHIFT
,
873 .flags
= INVERT_ENABLE
,
874 .clkdm_name
= "dpll3_clkdm",
877 DEFINE_STRUCT_CLK(dpll3_m3x2_ck
, dpll3_m3x2_ck_parent_names
, dpll4_m5x2_ck_ops
);
879 static struct clk dpll3_m3x2_ck_3630
= {
880 .name
= "dpll3_m3x2_ck",
881 .hw
= &dpll3_m3x2_ck_hw
.hw
,
882 .parent_names
= dpll3_m3x2_ck_parent_names
,
883 .num_parents
= ARRAY_SIZE(dpll3_m3x2_ck_parent_names
),
884 .ops
= &dpll4_m5x2_ck_3630_ops
,
887 DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck
, "dpll3_ck", &dpll3_ck
, 0x0, 2, 1);
889 DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck
, "dpll4_ck", &dpll4_ck
, 0x0,
890 OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_CLKSEL
),
891 OMAP3430_CLKSEL_DSS1_SHIFT
, OMAP3630_CLKSEL_DSS1_WIDTH
,
892 0, dpll4_mx_ck_div_table
, NULL
);
894 static struct clk dpll4_m4x2_ck
;
896 static const char *dpll4_m4x2_ck_parent_names
[] = {
900 static struct clk_hw_omap dpll4_m4x2_ck_hw
= {
902 .clk
= &dpll4_m4x2_ck
,
904 .ops
= &clkhwops_wait
,
905 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
906 .enable_bit
= OMAP3430_PWRDN_DSS1_SHIFT
,
907 .flags
= INVERT_ENABLE
,
908 .clkdm_name
= "dpll4_clkdm",
911 DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck
, dpll4_m4x2_ck_parent_names
,
912 dpll4_m5x2_ck_ops
, CLK_SET_RATE_PARENT
);
914 static struct clk dpll4_m4x2_ck_3630
= {
915 .name
= "dpll4_m4x2_ck",
916 .hw
= &dpll4_m4x2_ck_hw
.hw
,
917 .parent_names
= dpll4_m4x2_ck_parent_names
,
918 .num_parents
= ARRAY_SIZE(dpll4_m4x2_ck_parent_names
),
919 .ops
= &dpll4_m5x2_ck_3630_ops
,
920 .flags
= CLK_SET_RATE_PARENT
,
923 DEFINE_CLK_DIVIDER(dpll4_m6_ck
, "dpll4_ck", &dpll4_ck
, 0x0,
924 OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
925 OMAP3430_DIV_DPLL4_SHIFT
, OMAP3630_DIV_DPLL4_WIDTH
,
926 CLK_DIVIDER_ONE_BASED
, NULL
);
928 static struct clk dpll4_m6x2_ck
;
930 static const char *dpll4_m6x2_ck_parent_names
[] = {
934 static struct clk_hw_omap dpll4_m6x2_ck_hw
= {
936 .clk
= &dpll4_m6x2_ck
,
938 .ops
= &clkhwops_wait
,
939 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
940 .enable_bit
= OMAP3430_PWRDN_EMU_PERIPH_SHIFT
,
941 .flags
= INVERT_ENABLE
,
942 .clkdm_name
= "dpll4_clkdm",
945 DEFINE_STRUCT_CLK(dpll4_m6x2_ck
, dpll4_m6x2_ck_parent_names
, dpll4_m5x2_ck_ops
);
947 static struct clk dpll4_m6x2_ck_3630
= {
948 .name
= "dpll4_m6x2_ck",
949 .hw
= &dpll4_m6x2_ck_hw
.hw
,
950 .parent_names
= dpll4_m6x2_ck_parent_names
,
951 .num_parents
= ARRAY_SIZE(dpll4_m6x2_ck_parent_names
),
952 .ops
= &dpll4_m5x2_ck_3630_ops
,
955 DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck
, "dpll4_ck", &dpll4_ck
, 0x0, 2, 1);
957 static struct dpll_data dpll5_dd
= {
958 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_CLKSEL4
),
959 .mult_mask
= OMAP3430ES2_PERIPH2_DPLL_MULT_MASK
,
960 .div1_mask
= OMAP3430ES2_PERIPH2_DPLL_DIV_MASK
,
961 .clk_bypass
= &sys_ck
,
963 .freqsel_mask
= OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK
,
964 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_CLKEN2
),
965 .enable_mask
= OMAP3430ES2_EN_PERIPH2_DPLL_MASK
,
966 .modes
= (1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
),
967 .auto_recal_bit
= OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT
,
968 .recal_en_bit
= OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT
,
969 .recal_st_bit
= OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT
,
970 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_AUTOIDLE2_PLL
),
971 .autoidle_mask
= OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK
,
972 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST2
),
973 .idlest_mask
= OMAP3430ES2_ST_PERIPH2_CLK_MASK
,
974 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
976 .max_divider
= OMAP3_MAX_DPLL_DIV
,
979 static struct clk dpll5_ck
;
981 static struct clk_hw_omap dpll5_ck_hw
= {
985 .ops
= &clkhwops_omap3_dpll
,
986 .dpll_data
= &dpll5_dd
,
987 .clkdm_name
= "dpll5_clkdm",
990 DEFINE_STRUCT_CLK(dpll5_ck
, dpll3_ck_parent_names
, dpll1_ck_ops
);
992 DEFINE_CLK_DIVIDER(dpll5_m2_ck
, "dpll5_ck", &dpll5_ck
, 0x0,
993 OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_CLKSEL5
),
994 OMAP3430ES2_DIV_120M_SHIFT
, OMAP3430ES2_DIV_120M_WIDTH
,
995 CLK_DIVIDER_ONE_BASED
, NULL
);
997 static struct clk dss1_alwon_fck_3430es1
;
999 static const char *dss1_alwon_fck_3430es1_parent_names
[] = {
1003 static struct clk_hw_omap dss1_alwon_fck_3430es1_hw
= {
1005 .clk
= &dss1_alwon_fck_3430es1
,
1007 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
1008 .enable_bit
= OMAP3430_EN_DSS1_SHIFT
,
1009 .clkdm_name
= "dss_clkdm",
1012 DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es1
,
1013 dss1_alwon_fck_3430es1_parent_names
, aes2_ick_ops
,
1014 CLK_SET_RATE_PARENT
);
1016 static struct clk dss1_alwon_fck_3430es2
;
1018 static struct clk_hw_omap dss1_alwon_fck_3430es2_hw
= {
1020 .clk
= &dss1_alwon_fck_3430es2
,
1022 .ops
= &clkhwops_omap3430es2_dss_usbhost_wait
,
1023 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
1024 .enable_bit
= OMAP3430_EN_DSS1_SHIFT
,
1025 .clkdm_name
= "dss_clkdm",
1028 DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es2
,
1029 dss1_alwon_fck_3430es1_parent_names
, aes2_ick_ops
,
1030 CLK_SET_RATE_PARENT
);
1032 static struct clk dss2_alwon_fck
;
1034 static struct clk_hw_omap dss2_alwon_fck_hw
= {
1036 .clk
= &dss2_alwon_fck
,
1038 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
1039 .enable_bit
= OMAP3430_EN_DSS2_SHIFT
,
1040 .clkdm_name
= "dss_clkdm",
1043 DEFINE_STRUCT_CLK(dss2_alwon_fck
, dpll3_ck_parent_names
, aes2_ick_ops
);
1045 static struct clk dss_96m_fck
;
1047 static struct clk_hw_omap dss_96m_fck_hw
= {
1049 .clk
= &dss_96m_fck
,
1051 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
1052 .enable_bit
= OMAP3430_EN_TV_SHIFT
,
1053 .clkdm_name
= "dss_clkdm",
1056 DEFINE_STRUCT_CLK(dss_96m_fck
, core_96m_fck_parent_names
, aes2_ick_ops
);
1058 static struct clk dss_ick_3430es1
;
1060 static struct clk_hw_omap dss_ick_3430es1_hw
= {
1062 .clk
= &dss_ick_3430es1
,
1064 .ops
= &clkhwops_iclk
,
1065 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_ICLKEN
),
1066 .enable_bit
= OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT
,
1067 .clkdm_name
= "dss_clkdm",
1070 DEFINE_STRUCT_CLK(dss_ick_3430es1
, security_l4_ick2_parent_names
, aes2_ick_ops
);
1072 static struct clk dss_ick_3430es2
;
1074 static struct clk_hw_omap dss_ick_3430es2_hw
= {
1076 .clk
= &dss_ick_3430es2
,
1078 .ops
= &clkhwops_omap3430es2_iclk_dss_usbhost_wait
,
1079 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_ICLKEN
),
1080 .enable_bit
= OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT
,
1081 .clkdm_name
= "dss_clkdm",
1084 DEFINE_STRUCT_CLK(dss_ick_3430es2
, security_l4_ick2_parent_names
, aes2_ick_ops
);
1086 static struct clk dss_tv_fck
;
1088 static const char *dss_tv_fck_parent_names
[] = {
1092 static struct clk_hw_omap dss_tv_fck_hw
= {
1096 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
1097 .enable_bit
= OMAP3430_EN_TV_SHIFT
,
1098 .clkdm_name
= "dss_clkdm",
1101 DEFINE_STRUCT_CLK(dss_tv_fck
, dss_tv_fck_parent_names
, aes2_ick_ops
);
1103 static struct clk emac_fck
;
1105 static const char *emac_fck_parent_names
[] = {
1109 static struct clk_hw_omap emac_fck_hw
= {
1113 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
1114 .enable_bit
= AM35XX_CPGMAC_FCLK_SHIFT
,
1117 DEFINE_STRUCT_CLK(emac_fck
, emac_fck_parent_names
, aes1_ick_ops
);
1119 static struct clk ipss_ick
;
1121 static const char *ipss_ick_parent_names
[] = {
1125 static struct clk_hw_omap ipss_ick_hw
= {
1129 .ops
= &clkhwops_am35xx_ipss_wait
,
1130 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1131 .enable_bit
= AM35XX_EN_IPSS_SHIFT
,
1132 .clkdm_name
= "core_l3_clkdm",
1135 DEFINE_STRUCT_CLK(ipss_ick
, ipss_ick_parent_names
, aes2_ick_ops
);
1137 static struct clk emac_ick
;
1139 static const char *emac_ick_parent_names
[] = {
1143 static struct clk_hw_omap emac_ick_hw
= {
1147 .ops
= &clkhwops_am35xx_ipss_module_wait
,
1148 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
1149 .enable_bit
= AM35XX_CPGMAC_VBUSP_CLK_SHIFT
,
1150 .clkdm_name
= "core_l3_clkdm",
1153 DEFINE_STRUCT_CLK(emac_ick
, emac_ick_parent_names
, aes2_ick_ops
);
1155 static struct clk emu_core_alwon_ck
;
1157 static const char *emu_core_alwon_ck_parent_names
[] = {
1161 DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck
, "dpll3_clkdm");
1162 DEFINE_STRUCT_CLK(emu_core_alwon_ck
, emu_core_alwon_ck_parent_names
,
1165 static struct clk emu_mpu_alwon_ck
;
1167 static const char *emu_mpu_alwon_ck_parent_names
[] = {
1171 DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck
, NULL
);
1172 DEFINE_STRUCT_CLK(emu_mpu_alwon_ck
, emu_mpu_alwon_ck_parent_names
, core_ck_ops
);
1174 static struct clk emu_per_alwon_ck
;
1176 static const char *emu_per_alwon_ck_parent_names
[] = {
1180 DEFINE_STRUCT_CLK_HW_OMAP(emu_per_alwon_ck
, "dpll4_clkdm");
1181 DEFINE_STRUCT_CLK(emu_per_alwon_ck
, emu_per_alwon_ck_parent_names
,
1184 static const char *emu_src_ck_parent_names
[] = {
1185 "sys_ck", "emu_core_alwon_ck", "emu_per_alwon_ck", "emu_mpu_alwon_ck",
1188 static const struct clksel_rate emu_src_sys_rates
[] = {
1189 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
1193 static const struct clksel_rate emu_src_core_rates
[] = {
1194 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
1198 static const struct clksel_rate emu_src_per_rates
[] = {
1199 { .div
= 1, .val
= 2, .flags
= RATE_IN_3XXX
},
1203 static const struct clksel_rate emu_src_mpu_rates
[] = {
1204 { .div
= 1, .val
= 3, .flags
= RATE_IN_3XXX
},
1208 static const struct clksel emu_src_clksel
[] = {
1209 { .parent
= &sys_ck
, .rates
= emu_src_sys_rates
},
1210 { .parent
= &emu_core_alwon_ck
, .rates
= emu_src_core_rates
},
1211 { .parent
= &emu_per_alwon_ck
, .rates
= emu_src_per_rates
},
1212 { .parent
= &emu_mpu_alwon_ck
, .rates
= emu_src_mpu_rates
},
1216 static const struct clk_ops emu_src_ck_ops
= {
1217 .init
= &omap2_init_clk_clkdm
,
1218 .recalc_rate
= &omap2_clksel_recalc
,
1219 .get_parent
= &omap2_clksel_find_parent_index
,
1220 .set_parent
= &omap2_clksel_set_parent
,
1221 .enable
= &omap2_clkops_enable_clkdm
,
1222 .disable
= &omap2_clkops_disable_clkdm
,
1225 static struct clk emu_src_ck
;
1227 static struct clk_hw_omap emu_src_ck_hw
= {
1231 .clksel
= emu_src_clksel
,
1232 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
1233 .clksel_mask
= OMAP3430_MUX_CTRL_MASK
,
1234 .clkdm_name
= "emu_clkdm",
1237 DEFINE_STRUCT_CLK(emu_src_ck
, emu_src_ck_parent_names
, emu_src_ck_ops
);
1239 DEFINE_CLK_DIVIDER(atclk_fck
, "emu_src_ck", &emu_src_ck
, 0x0,
1240 OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
1241 OMAP3430_CLKSEL_ATCLK_SHIFT
, OMAP3430_CLKSEL_ATCLK_WIDTH
,
1242 CLK_DIVIDER_ONE_BASED
, NULL
);
1244 static struct clk fac_ick
;
1246 static struct clk_hw_omap fac_ick_hw
= {
1250 .ops
= &clkhwops_iclk_wait
,
1251 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1252 .enable_bit
= OMAP3430ES1_EN_FAC_SHIFT
,
1253 .clkdm_name
= "core_l4_clkdm",
1256 DEFINE_STRUCT_CLK(fac_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
1258 static struct clk fshostusb_fck
;
1260 static const char *fshostusb_fck_parent_names
[] = {
1264 static struct clk_hw_omap fshostusb_fck_hw
= {
1266 .clk
= &fshostusb_fck
,
1268 .ops
= &clkhwops_wait
,
1269 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1270 .enable_bit
= OMAP3430ES1_EN_FSHOSTUSB_SHIFT
,
1271 .clkdm_name
= "core_l4_clkdm",
1274 DEFINE_STRUCT_CLK(fshostusb_fck
, fshostusb_fck_parent_names
, aes2_ick_ops
);
1276 static struct clk gfx_l3_ck
;
1278 static struct clk_hw_omap gfx_l3_ck_hw
= {
1282 .ops
= &clkhwops_wait
,
1283 .enable_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_ICLKEN
),
1284 .enable_bit
= OMAP_EN_GFX_SHIFT
,
1285 .clkdm_name
= "gfx_3430es1_clkdm",
1288 DEFINE_STRUCT_CLK(gfx_l3_ck
, core_l3_ick_parent_names
, aes1_ick_ops
);
1290 DEFINE_CLK_DIVIDER(gfx_l3_fck
, "l3_ick", &l3_ick
, 0x0,
1291 OMAP_CM_REGADDR(GFX_MOD
, CM_CLKSEL
),
1292 OMAP_CLKSEL_GFX_SHIFT
, OMAP_CLKSEL_GFX_WIDTH
,
1293 CLK_DIVIDER_ONE_BASED
, NULL
);
1295 static struct clk gfx_cg1_ck
;
1297 static const char *gfx_cg1_ck_parent_names
[] = {
1301 static struct clk_hw_omap gfx_cg1_ck_hw
= {
1305 .ops
= &clkhwops_wait
,
1306 .enable_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_FCLKEN
),
1307 .enable_bit
= OMAP3430ES1_EN_2D_SHIFT
,
1308 .clkdm_name
= "gfx_3430es1_clkdm",
1311 DEFINE_STRUCT_CLK(gfx_cg1_ck
, gfx_cg1_ck_parent_names
, aes2_ick_ops
);
1313 static struct clk gfx_cg2_ck
;
1315 static struct clk_hw_omap gfx_cg2_ck_hw
= {
1319 .ops
= &clkhwops_wait
,
1320 .enable_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_FCLKEN
),
1321 .enable_bit
= OMAP3430ES1_EN_3D_SHIFT
,
1322 .clkdm_name
= "gfx_3430es1_clkdm",
1325 DEFINE_STRUCT_CLK(gfx_cg2_ck
, gfx_cg1_ck_parent_names
, aes2_ick_ops
);
1327 static struct clk gfx_l3_ick
;
1329 static const char *gfx_l3_ick_parent_names
[] = {
1333 DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick
, "gfx_3430es1_clkdm");
1334 DEFINE_STRUCT_CLK(gfx_l3_ick
, gfx_l3_ick_parent_names
, core_l4_ick_ops
);
1336 static struct clk wkup_32k_fck
;
1338 static const char *wkup_32k_fck_parent_names
[] = {
1342 DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck
, "wkup_clkdm");
1343 DEFINE_STRUCT_CLK(wkup_32k_fck
, wkup_32k_fck_parent_names
, core_l4_ick_ops
);
1345 static struct clk gpio1_dbck
;
1347 static const char *gpio1_dbck_parent_names
[] = {
1351 static struct clk_hw_omap gpio1_dbck_hw
= {
1355 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
1356 .enable_bit
= OMAP3430_EN_GPIO1_SHIFT
,
1357 .clkdm_name
= "wkup_clkdm",
1360 DEFINE_STRUCT_CLK(gpio1_dbck
, gpio1_dbck_parent_names
, aes2_ick_ops
);
1362 static struct clk wkup_l4_ick
;
1364 DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick
, "wkup_clkdm");
1365 DEFINE_STRUCT_CLK(wkup_l4_ick
, dpll3_ck_parent_names
, core_l4_ick_ops
);
1367 static struct clk gpio1_ick
;
1369 static const char *gpio1_ick_parent_names
[] = {
1373 static struct clk_hw_omap gpio1_ick_hw
= {
1377 .ops
= &clkhwops_iclk_wait
,
1378 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
1379 .enable_bit
= OMAP3430_EN_GPIO1_SHIFT
,
1380 .clkdm_name
= "wkup_clkdm",
1383 DEFINE_STRUCT_CLK(gpio1_ick
, gpio1_ick_parent_names
, aes2_ick_ops
);
1385 static struct clk per_32k_alwon_fck
;
1387 DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck
, "per_clkdm");
1388 DEFINE_STRUCT_CLK(per_32k_alwon_fck
, wkup_32k_fck_parent_names
,
1391 static struct clk gpio2_dbck
;
1393 static const char *gpio2_dbck_parent_names
[] = {
1394 "per_32k_alwon_fck",
1397 static struct clk_hw_omap gpio2_dbck_hw
= {
1401 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1402 .enable_bit
= OMAP3430_EN_GPIO2_SHIFT
,
1403 .clkdm_name
= "per_clkdm",
1406 DEFINE_STRUCT_CLK(gpio2_dbck
, gpio2_dbck_parent_names
, aes2_ick_ops
);
1408 static struct clk per_l4_ick
;
1410 DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick
, "per_clkdm");
1411 DEFINE_STRUCT_CLK(per_l4_ick
, security_l4_ick2_parent_names
, core_l4_ick_ops
);
1413 static struct clk gpio2_ick
;
1415 static const char *gpio2_ick_parent_names
[] = {
1419 static struct clk_hw_omap gpio2_ick_hw
= {
1423 .ops
= &clkhwops_iclk_wait
,
1424 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1425 .enable_bit
= OMAP3430_EN_GPIO2_SHIFT
,
1426 .clkdm_name
= "per_clkdm",
1429 DEFINE_STRUCT_CLK(gpio2_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1431 static struct clk gpio3_dbck
;
1433 static struct clk_hw_omap gpio3_dbck_hw
= {
1437 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1438 .enable_bit
= OMAP3430_EN_GPIO3_SHIFT
,
1439 .clkdm_name
= "per_clkdm",
1442 DEFINE_STRUCT_CLK(gpio3_dbck
, gpio2_dbck_parent_names
, aes2_ick_ops
);
1444 static struct clk gpio3_ick
;
1446 static struct clk_hw_omap gpio3_ick_hw
= {
1450 .ops
= &clkhwops_iclk_wait
,
1451 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1452 .enable_bit
= OMAP3430_EN_GPIO3_SHIFT
,
1453 .clkdm_name
= "per_clkdm",
1456 DEFINE_STRUCT_CLK(gpio3_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1458 static struct clk gpio4_dbck
;
1460 static struct clk_hw_omap gpio4_dbck_hw
= {
1464 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1465 .enable_bit
= OMAP3430_EN_GPIO4_SHIFT
,
1466 .clkdm_name
= "per_clkdm",
1469 DEFINE_STRUCT_CLK(gpio4_dbck
, gpio2_dbck_parent_names
, aes2_ick_ops
);
1471 static struct clk gpio4_ick
;
1473 static struct clk_hw_omap gpio4_ick_hw
= {
1477 .ops
= &clkhwops_iclk_wait
,
1478 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1479 .enable_bit
= OMAP3430_EN_GPIO4_SHIFT
,
1480 .clkdm_name
= "per_clkdm",
1483 DEFINE_STRUCT_CLK(gpio4_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1485 static struct clk gpio5_dbck
;
1487 static struct clk_hw_omap gpio5_dbck_hw
= {
1491 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1492 .enable_bit
= OMAP3430_EN_GPIO5_SHIFT
,
1493 .clkdm_name
= "per_clkdm",
1496 DEFINE_STRUCT_CLK(gpio5_dbck
, gpio2_dbck_parent_names
, aes2_ick_ops
);
1498 static struct clk gpio5_ick
;
1500 static struct clk_hw_omap gpio5_ick_hw
= {
1504 .ops
= &clkhwops_iclk_wait
,
1505 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1506 .enable_bit
= OMAP3430_EN_GPIO5_SHIFT
,
1507 .clkdm_name
= "per_clkdm",
1510 DEFINE_STRUCT_CLK(gpio5_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1512 static struct clk gpio6_dbck
;
1514 static struct clk_hw_omap gpio6_dbck_hw
= {
1518 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1519 .enable_bit
= OMAP3430_EN_GPIO6_SHIFT
,
1520 .clkdm_name
= "per_clkdm",
1523 DEFINE_STRUCT_CLK(gpio6_dbck
, gpio2_dbck_parent_names
, aes2_ick_ops
);
1525 static struct clk gpio6_ick
;
1527 static struct clk_hw_omap gpio6_ick_hw
= {
1531 .ops
= &clkhwops_iclk_wait
,
1532 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1533 .enable_bit
= OMAP3430_EN_GPIO6_SHIFT
,
1534 .clkdm_name
= "per_clkdm",
1537 DEFINE_STRUCT_CLK(gpio6_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1539 static struct clk gpmc_fck
;
1541 static struct clk_hw_omap gpmc_fck_hw
= {
1545 .flags
= ENABLE_ON_INIT
,
1546 .clkdm_name
= "core_l3_clkdm",
1549 DEFINE_STRUCT_CLK(gpmc_fck
, ipss_ick_parent_names
, core_l4_ick_ops
);
1551 static const struct clksel omap343x_gpt_clksel
[] = {
1552 { .parent
= &omap_32k_fck
, .rates
= gpt_32k_rates
},
1553 { .parent
= &sys_ck
, .rates
= gpt_sys_rates
},
1557 static const char *gpt10_fck_parent_names
[] = {
1558 "omap_32k_fck", "sys_ck",
1561 DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck
, "core_l4_clkdm", omap343x_gpt_clksel
,
1562 OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1563 OMAP3430_CLKSEL_GPT10_MASK
,
1564 OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1565 OMAP3430_EN_GPT10_SHIFT
, &clkhwops_wait
,
1566 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1568 static struct clk gpt10_ick
;
1570 static struct clk_hw_omap gpt10_ick_hw
= {
1574 .ops
= &clkhwops_iclk_wait
,
1575 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1576 .enable_bit
= OMAP3430_EN_GPT10_SHIFT
,
1577 .clkdm_name
= "core_l4_clkdm",
1580 DEFINE_STRUCT_CLK(gpt10_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
1582 DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck
, "core_l4_clkdm", omap343x_gpt_clksel
,
1583 OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1584 OMAP3430_CLKSEL_GPT11_MASK
,
1585 OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1586 OMAP3430_EN_GPT11_SHIFT
, &clkhwops_wait
,
1587 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1589 static struct clk gpt11_ick
;
1591 static struct clk_hw_omap gpt11_ick_hw
= {
1595 .ops
= &clkhwops_iclk_wait
,
1596 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1597 .enable_bit
= OMAP3430_EN_GPT11_SHIFT
,
1598 .clkdm_name
= "core_l4_clkdm",
1601 DEFINE_STRUCT_CLK(gpt11_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
1603 static struct clk gpt12_fck
;
1605 static const char *gpt12_fck_parent_names
[] = {
1609 DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck
, "wkup_clkdm");
1610 DEFINE_STRUCT_CLK(gpt12_fck
, gpt12_fck_parent_names
, core_l4_ick_ops
);
1612 static struct clk gpt12_ick
;
1614 static struct clk_hw_omap gpt12_ick_hw
= {
1618 .ops
= &clkhwops_iclk_wait
,
1619 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
1620 .enable_bit
= OMAP3430_EN_GPT12_SHIFT
,
1621 .clkdm_name
= "wkup_clkdm",
1624 DEFINE_STRUCT_CLK(gpt12_ick
, gpio1_ick_parent_names
, aes2_ick_ops
);
1626 DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck
, "wkup_clkdm", omap343x_gpt_clksel
,
1627 OMAP_CM_REGADDR(WKUP_MOD
, CM_CLKSEL
),
1628 OMAP3430_CLKSEL_GPT1_MASK
,
1629 OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
1630 OMAP3430_EN_GPT1_SHIFT
, &clkhwops_wait
,
1631 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1633 static struct clk gpt1_ick
;
1635 static struct clk_hw_omap gpt1_ick_hw
= {
1639 .ops
= &clkhwops_iclk_wait
,
1640 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
1641 .enable_bit
= OMAP3430_EN_GPT1_SHIFT
,
1642 .clkdm_name
= "wkup_clkdm",
1645 DEFINE_STRUCT_CLK(gpt1_ick
, gpio1_ick_parent_names
, aes2_ick_ops
);
1647 DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck
, "per_clkdm", omap343x_gpt_clksel
,
1648 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
1649 OMAP3430_CLKSEL_GPT2_MASK
,
1650 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1651 OMAP3430_EN_GPT2_SHIFT
, &clkhwops_wait
,
1652 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1654 static struct clk gpt2_ick
;
1656 static struct clk_hw_omap gpt2_ick_hw
= {
1660 .ops
= &clkhwops_iclk_wait
,
1661 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1662 .enable_bit
= OMAP3430_EN_GPT2_SHIFT
,
1663 .clkdm_name
= "per_clkdm",
1666 DEFINE_STRUCT_CLK(gpt2_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1668 DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck
, "per_clkdm", omap343x_gpt_clksel
,
1669 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
1670 OMAP3430_CLKSEL_GPT3_MASK
,
1671 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1672 OMAP3430_EN_GPT3_SHIFT
, &clkhwops_wait
,
1673 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1675 static struct clk gpt3_ick
;
1677 static struct clk_hw_omap gpt3_ick_hw
= {
1681 .ops
= &clkhwops_iclk_wait
,
1682 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1683 .enable_bit
= OMAP3430_EN_GPT3_SHIFT
,
1684 .clkdm_name
= "per_clkdm",
1687 DEFINE_STRUCT_CLK(gpt3_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1689 DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck
, "per_clkdm", omap343x_gpt_clksel
,
1690 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
1691 OMAP3430_CLKSEL_GPT4_MASK
,
1692 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1693 OMAP3430_EN_GPT4_SHIFT
, &clkhwops_wait
,
1694 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1696 static struct clk gpt4_ick
;
1698 static struct clk_hw_omap gpt4_ick_hw
= {
1702 .ops
= &clkhwops_iclk_wait
,
1703 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1704 .enable_bit
= OMAP3430_EN_GPT4_SHIFT
,
1705 .clkdm_name
= "per_clkdm",
1708 DEFINE_STRUCT_CLK(gpt4_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1710 DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck
, "per_clkdm", omap343x_gpt_clksel
,
1711 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
1712 OMAP3430_CLKSEL_GPT5_MASK
,
1713 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1714 OMAP3430_EN_GPT5_SHIFT
, &clkhwops_wait
,
1715 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1717 static struct clk gpt5_ick
;
1719 static struct clk_hw_omap gpt5_ick_hw
= {
1723 .ops
= &clkhwops_iclk_wait
,
1724 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1725 .enable_bit
= OMAP3430_EN_GPT5_SHIFT
,
1726 .clkdm_name
= "per_clkdm",
1729 DEFINE_STRUCT_CLK(gpt5_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1731 DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck
, "per_clkdm", omap343x_gpt_clksel
,
1732 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
1733 OMAP3430_CLKSEL_GPT6_MASK
,
1734 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1735 OMAP3430_EN_GPT6_SHIFT
, &clkhwops_wait
,
1736 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1738 static struct clk gpt6_ick
;
1740 static struct clk_hw_omap gpt6_ick_hw
= {
1744 .ops
= &clkhwops_iclk_wait
,
1745 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1746 .enable_bit
= OMAP3430_EN_GPT6_SHIFT
,
1747 .clkdm_name
= "per_clkdm",
1750 DEFINE_STRUCT_CLK(gpt6_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1752 DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck
, "per_clkdm", omap343x_gpt_clksel
,
1753 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
1754 OMAP3430_CLKSEL_GPT7_MASK
,
1755 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1756 OMAP3430_EN_GPT7_SHIFT
, &clkhwops_wait
,
1757 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1759 static struct clk gpt7_ick
;
1761 static struct clk_hw_omap gpt7_ick_hw
= {
1765 .ops
= &clkhwops_iclk_wait
,
1766 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1767 .enable_bit
= OMAP3430_EN_GPT7_SHIFT
,
1768 .clkdm_name
= "per_clkdm",
1771 DEFINE_STRUCT_CLK(gpt7_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1773 DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck
, "per_clkdm", omap343x_gpt_clksel
,
1774 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
1775 OMAP3430_CLKSEL_GPT8_MASK
,
1776 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1777 OMAP3430_EN_GPT8_SHIFT
, &clkhwops_wait
,
1778 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1780 static struct clk gpt8_ick
;
1782 static struct clk_hw_omap gpt8_ick_hw
= {
1786 .ops
= &clkhwops_iclk_wait
,
1787 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1788 .enable_bit
= OMAP3430_EN_GPT8_SHIFT
,
1789 .clkdm_name
= "per_clkdm",
1792 DEFINE_STRUCT_CLK(gpt8_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1794 DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck
, "per_clkdm", omap343x_gpt_clksel
,
1795 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
1796 OMAP3430_CLKSEL_GPT9_MASK
,
1797 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1798 OMAP3430_EN_GPT9_SHIFT
, &clkhwops_wait
,
1799 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1801 static struct clk gpt9_ick
;
1803 static struct clk_hw_omap gpt9_ick_hw
= {
1807 .ops
= &clkhwops_iclk_wait
,
1808 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1809 .enable_bit
= OMAP3430_EN_GPT9_SHIFT
,
1810 .clkdm_name
= "per_clkdm",
1813 DEFINE_STRUCT_CLK(gpt9_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1815 static struct clk hdq_fck
;
1817 static const char *hdq_fck_parent_names
[] = {
1821 static struct clk_hw_omap hdq_fck_hw
= {
1825 .ops
= &clkhwops_wait
,
1826 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1827 .enable_bit
= OMAP3430_EN_HDQ_SHIFT
,
1828 .clkdm_name
= "core_l4_clkdm",
1831 DEFINE_STRUCT_CLK(hdq_fck
, hdq_fck_parent_names
, aes2_ick_ops
);
1833 static struct clk hdq_ick
;
1835 static struct clk_hw_omap hdq_ick_hw
= {
1839 .ops
= &clkhwops_iclk_wait
,
1840 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1841 .enable_bit
= OMAP3430_EN_HDQ_SHIFT
,
1842 .clkdm_name
= "core_l4_clkdm",
1845 DEFINE_STRUCT_CLK(hdq_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
1847 static struct clk hecc_ck
;
1849 static struct clk_hw_omap hecc_ck_hw
= {
1853 .ops
= &clkhwops_am35xx_ipss_module_wait
,
1854 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
1855 .enable_bit
= AM35XX_HECC_VBUSP_CLK_SHIFT
,
1856 .clkdm_name
= "core_l3_clkdm",
1859 DEFINE_STRUCT_CLK(hecc_ck
, dpll3_ck_parent_names
, aes2_ick_ops
);
1861 static struct clk hsotgusb_fck_am35xx
;
1863 static struct clk_hw_omap hsotgusb_fck_am35xx_hw
= {
1865 .clk
= &hsotgusb_fck_am35xx
,
1867 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
1868 .enable_bit
= AM35XX_USBOTG_FCLK_SHIFT
,
1869 .clkdm_name
= "core_l3_clkdm",
1872 DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx
, dpll3_ck_parent_names
, aes2_ick_ops
);
1874 static struct clk hsotgusb_ick_3430es1
;
1876 static struct clk_hw_omap hsotgusb_ick_3430es1_hw
= {
1878 .clk
= &hsotgusb_ick_3430es1
,
1880 .ops
= &clkhwops_iclk
,
1881 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1882 .enable_bit
= OMAP3430_EN_HSOTGUSB_SHIFT
,
1883 .clkdm_name
= "core_l3_clkdm",
1886 DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1
, ipss_ick_parent_names
, aes2_ick_ops
);
1888 static struct clk hsotgusb_ick_3430es2
;
1890 static struct clk_hw_omap hsotgusb_ick_3430es2_hw
= {
1892 .clk
= &hsotgusb_ick_3430es2
,
1894 .ops
= &clkhwops_omap3430es2_iclk_hsotgusb_wait
,
1895 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1896 .enable_bit
= OMAP3430_EN_HSOTGUSB_SHIFT
,
1897 .clkdm_name
= "core_l3_clkdm",
1900 DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2
, ipss_ick_parent_names
, aes2_ick_ops
);
1902 static struct clk hsotgusb_ick_am35xx
;
1904 static struct clk_hw_omap hsotgusb_ick_am35xx_hw
= {
1906 .clk
= &hsotgusb_ick_am35xx
,
1908 .ops
= &clkhwops_am35xx_ipss_module_wait
,
1909 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
1910 .enable_bit
= AM35XX_USBOTG_VBUSP_CLK_SHIFT
,
1911 .clkdm_name
= "core_l3_clkdm",
1914 DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx
, emac_ick_parent_names
, aes2_ick_ops
);
1916 static struct clk i2c1_fck
;
1918 static struct clk_hw_omap i2c1_fck_hw
= {
1922 .ops
= &clkhwops_wait
,
1923 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1924 .enable_bit
= OMAP3430_EN_I2C1_SHIFT
,
1925 .clkdm_name
= "core_l4_clkdm",
1928 DEFINE_STRUCT_CLK(i2c1_fck
, csi2_96m_fck_parent_names
, aes2_ick_ops
);
1930 static struct clk i2c1_ick
;
1932 static struct clk_hw_omap i2c1_ick_hw
= {
1936 .ops
= &clkhwops_iclk_wait
,
1937 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1938 .enable_bit
= OMAP3430_EN_I2C1_SHIFT
,
1939 .clkdm_name
= "core_l4_clkdm",
1942 DEFINE_STRUCT_CLK(i2c1_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
1944 static struct clk i2c2_fck
;
1946 static struct clk_hw_omap i2c2_fck_hw
= {
1950 .ops
= &clkhwops_wait
,
1951 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1952 .enable_bit
= OMAP3430_EN_I2C2_SHIFT
,
1953 .clkdm_name
= "core_l4_clkdm",
1956 DEFINE_STRUCT_CLK(i2c2_fck
, csi2_96m_fck_parent_names
, aes2_ick_ops
);
1958 static struct clk i2c2_ick
;
1960 static struct clk_hw_omap i2c2_ick_hw
= {
1964 .ops
= &clkhwops_iclk_wait
,
1965 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1966 .enable_bit
= OMAP3430_EN_I2C2_SHIFT
,
1967 .clkdm_name
= "core_l4_clkdm",
1970 DEFINE_STRUCT_CLK(i2c2_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
1972 static struct clk i2c3_fck
;
1974 static struct clk_hw_omap i2c3_fck_hw
= {
1978 .ops
= &clkhwops_wait
,
1979 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1980 .enable_bit
= OMAP3430_EN_I2C3_SHIFT
,
1981 .clkdm_name
= "core_l4_clkdm",
1984 DEFINE_STRUCT_CLK(i2c3_fck
, csi2_96m_fck_parent_names
, aes2_ick_ops
);
1986 static struct clk i2c3_ick
;
1988 static struct clk_hw_omap i2c3_ick_hw
= {
1992 .ops
= &clkhwops_iclk_wait
,
1993 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1994 .enable_bit
= OMAP3430_EN_I2C3_SHIFT
,
1995 .clkdm_name
= "core_l4_clkdm",
1998 DEFINE_STRUCT_CLK(i2c3_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2000 static struct clk icr_ick
;
2002 static struct clk_hw_omap icr_ick_hw
= {
2006 .ops
= &clkhwops_iclk_wait
,
2007 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2008 .enable_bit
= OMAP3430_EN_ICR_SHIFT
,
2009 .clkdm_name
= "core_l4_clkdm",
2012 DEFINE_STRUCT_CLK(icr_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2014 static struct clk iva2_ck
;
2016 static const char *iva2_ck_parent_names
[] = {
2020 static struct clk_hw_omap iva2_ck_hw
= {
2024 .ops
= &clkhwops_wait
,
2025 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, CM_FCLKEN
),
2026 .enable_bit
= OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT
,
2027 .clkdm_name
= "iva2_clkdm",
2030 DEFINE_STRUCT_CLK(iva2_ck
, iva2_ck_parent_names
, aes2_ick_ops
);
2032 static struct clk mad2d_ick
;
2034 static struct clk_hw_omap mad2d_ick_hw
= {
2038 .ops
= &clkhwops_iclk_wait
,
2039 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN3
),
2040 .enable_bit
= OMAP3430_EN_MAD2D_SHIFT
,
2041 .clkdm_name
= "d2d_clkdm",
2044 DEFINE_STRUCT_CLK(mad2d_ick
, core_l3_ick_parent_names
, aes2_ick_ops
);
2046 static struct clk mailboxes_ick
;
2048 static struct clk_hw_omap mailboxes_ick_hw
= {
2050 .clk
= &mailboxes_ick
,
2052 .ops
= &clkhwops_iclk_wait
,
2053 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2054 .enable_bit
= OMAP3430_EN_MAILBOXES_SHIFT
,
2055 .clkdm_name
= "core_l4_clkdm",
2058 DEFINE_STRUCT_CLK(mailboxes_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2060 static const struct clksel_rate common_mcbsp_96m_rates
[] = {
2061 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
2065 static const struct clksel_rate common_mcbsp_mcbsp_rates
[] = {
2066 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
2070 static const struct clksel mcbsp_15_clksel
[] = {
2071 { .parent
= &core_96m_fck
, .rates
= common_mcbsp_96m_rates
},
2072 { .parent
= &mcbsp_clks
, .rates
= common_mcbsp_mcbsp_rates
},
2076 static const char *mcbsp1_fck_parent_names
[] = {
2077 "core_96m_fck", "mcbsp_clks",
2080 DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck
, "core_l4_clkdm", mcbsp_15_clksel
,
2081 OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0
),
2082 OMAP2_MCBSP1_CLKS_MASK
,
2083 OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2084 OMAP3430_EN_MCBSP1_SHIFT
, &clkhwops_wait
,
2085 mcbsp1_fck_parent_names
, clkout2_src_ck_ops
);
2087 static struct clk mcbsp1_ick
;
2089 static struct clk_hw_omap mcbsp1_ick_hw
= {
2093 .ops
= &clkhwops_iclk_wait
,
2094 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2095 .enable_bit
= OMAP3430_EN_MCBSP1_SHIFT
,
2096 .clkdm_name
= "core_l4_clkdm",
2099 DEFINE_STRUCT_CLK(mcbsp1_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2101 static struct clk per_96m_fck
;
2103 DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck
, "per_clkdm");
2104 DEFINE_STRUCT_CLK(per_96m_fck
, cm_96m_fck_parent_names
, core_l4_ick_ops
);
2106 static const struct clksel mcbsp_234_clksel
[] = {
2107 { .parent
= &per_96m_fck
, .rates
= common_mcbsp_96m_rates
},
2108 { .parent
= &mcbsp_clks
, .rates
= common_mcbsp_mcbsp_rates
},
2112 static const char *mcbsp2_fck_parent_names
[] = {
2113 "per_96m_fck", "mcbsp_clks",
2116 DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck
, "per_clkdm", mcbsp_234_clksel
,
2117 OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0
),
2118 OMAP2_MCBSP2_CLKS_MASK
,
2119 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2120 OMAP3430_EN_MCBSP2_SHIFT
, &clkhwops_wait
,
2121 mcbsp2_fck_parent_names
, clkout2_src_ck_ops
);
2123 static struct clk mcbsp2_ick
;
2125 static struct clk_hw_omap mcbsp2_ick_hw
= {
2129 .ops
= &clkhwops_iclk_wait
,
2130 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2131 .enable_bit
= OMAP3430_EN_MCBSP2_SHIFT
,
2132 .clkdm_name
= "per_clkdm",
2135 DEFINE_STRUCT_CLK(mcbsp2_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
2137 DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck
, "per_clkdm", mcbsp_234_clksel
,
2138 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1
),
2139 OMAP2_MCBSP3_CLKS_MASK
,
2140 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2141 OMAP3430_EN_MCBSP3_SHIFT
, &clkhwops_wait
,
2142 mcbsp2_fck_parent_names
, clkout2_src_ck_ops
);
2144 static struct clk mcbsp3_ick
;
2146 static struct clk_hw_omap mcbsp3_ick_hw
= {
2150 .ops
= &clkhwops_iclk_wait
,
2151 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2152 .enable_bit
= OMAP3430_EN_MCBSP3_SHIFT
,
2153 .clkdm_name
= "per_clkdm",
2156 DEFINE_STRUCT_CLK(mcbsp3_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
2158 DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck
, "per_clkdm", mcbsp_234_clksel
,
2159 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1
),
2160 OMAP2_MCBSP4_CLKS_MASK
,
2161 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2162 OMAP3430_EN_MCBSP4_SHIFT
, &clkhwops_wait
,
2163 mcbsp2_fck_parent_names
, clkout2_src_ck_ops
);
2165 static struct clk mcbsp4_ick
;
2167 static struct clk_hw_omap mcbsp4_ick_hw
= {
2171 .ops
= &clkhwops_iclk_wait
,
2172 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2173 .enable_bit
= OMAP3430_EN_MCBSP4_SHIFT
,
2174 .clkdm_name
= "per_clkdm",
2177 DEFINE_STRUCT_CLK(mcbsp4_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
2179 DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck
, "core_l4_clkdm", mcbsp_15_clksel
,
2180 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1
),
2181 OMAP2_MCBSP5_CLKS_MASK
,
2182 OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2183 OMAP3430_EN_MCBSP5_SHIFT
, &clkhwops_wait
,
2184 mcbsp1_fck_parent_names
, clkout2_src_ck_ops
);
2186 static struct clk mcbsp5_ick
;
2188 static struct clk_hw_omap mcbsp5_ick_hw
= {
2192 .ops
= &clkhwops_iclk_wait
,
2193 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2194 .enable_bit
= OMAP3430_EN_MCBSP5_SHIFT
,
2195 .clkdm_name
= "core_l4_clkdm",
2198 DEFINE_STRUCT_CLK(mcbsp5_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2200 static struct clk mcspi1_fck
;
2202 static struct clk_hw_omap mcspi1_fck_hw
= {
2206 .ops
= &clkhwops_wait
,
2207 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2208 .enable_bit
= OMAP3430_EN_MCSPI1_SHIFT
,
2209 .clkdm_name
= "core_l4_clkdm",
2212 DEFINE_STRUCT_CLK(mcspi1_fck
, fshostusb_fck_parent_names
, aes2_ick_ops
);
2214 static struct clk mcspi1_ick
;
2216 static struct clk_hw_omap mcspi1_ick_hw
= {
2220 .ops
= &clkhwops_iclk_wait
,
2221 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2222 .enable_bit
= OMAP3430_EN_MCSPI1_SHIFT
,
2223 .clkdm_name
= "core_l4_clkdm",
2226 DEFINE_STRUCT_CLK(mcspi1_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2228 static struct clk mcspi2_fck
;
2230 static struct clk_hw_omap mcspi2_fck_hw
= {
2234 .ops
= &clkhwops_wait
,
2235 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2236 .enable_bit
= OMAP3430_EN_MCSPI2_SHIFT
,
2237 .clkdm_name
= "core_l4_clkdm",
2240 DEFINE_STRUCT_CLK(mcspi2_fck
, fshostusb_fck_parent_names
, aes2_ick_ops
);
2242 static struct clk mcspi2_ick
;
2244 static struct clk_hw_omap mcspi2_ick_hw
= {
2248 .ops
= &clkhwops_iclk_wait
,
2249 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2250 .enable_bit
= OMAP3430_EN_MCSPI2_SHIFT
,
2251 .clkdm_name
= "core_l4_clkdm",
2254 DEFINE_STRUCT_CLK(mcspi2_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2256 static struct clk mcspi3_fck
;
2258 static struct clk_hw_omap mcspi3_fck_hw
= {
2262 .ops
= &clkhwops_wait
,
2263 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2264 .enable_bit
= OMAP3430_EN_MCSPI3_SHIFT
,
2265 .clkdm_name
= "core_l4_clkdm",
2268 DEFINE_STRUCT_CLK(mcspi3_fck
, fshostusb_fck_parent_names
, aes2_ick_ops
);
2270 static struct clk mcspi3_ick
;
2272 static struct clk_hw_omap mcspi3_ick_hw
= {
2276 .ops
= &clkhwops_iclk_wait
,
2277 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2278 .enable_bit
= OMAP3430_EN_MCSPI3_SHIFT
,
2279 .clkdm_name
= "core_l4_clkdm",
2282 DEFINE_STRUCT_CLK(mcspi3_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2284 static struct clk mcspi4_fck
;
2286 static struct clk_hw_omap mcspi4_fck_hw
= {
2290 .ops
= &clkhwops_wait
,
2291 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2292 .enable_bit
= OMAP3430_EN_MCSPI4_SHIFT
,
2293 .clkdm_name
= "core_l4_clkdm",
2296 DEFINE_STRUCT_CLK(mcspi4_fck
, fshostusb_fck_parent_names
, aes2_ick_ops
);
2298 static struct clk mcspi4_ick
;
2300 static struct clk_hw_omap mcspi4_ick_hw
= {
2304 .ops
= &clkhwops_iclk_wait
,
2305 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2306 .enable_bit
= OMAP3430_EN_MCSPI4_SHIFT
,
2307 .clkdm_name
= "core_l4_clkdm",
2310 DEFINE_STRUCT_CLK(mcspi4_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2312 static struct clk mmchs1_fck
;
2314 static struct clk_hw_omap mmchs1_fck_hw
= {
2318 .ops
= &clkhwops_wait
,
2319 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2320 .enable_bit
= OMAP3430_EN_MMC1_SHIFT
,
2321 .clkdm_name
= "core_l4_clkdm",
2324 DEFINE_STRUCT_CLK(mmchs1_fck
, csi2_96m_fck_parent_names
, aes2_ick_ops
);
2326 static struct clk mmchs1_ick
;
2328 static struct clk_hw_omap mmchs1_ick_hw
= {
2332 .ops
= &clkhwops_iclk_wait
,
2333 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2334 .enable_bit
= OMAP3430_EN_MMC1_SHIFT
,
2335 .clkdm_name
= "core_l4_clkdm",
2338 DEFINE_STRUCT_CLK(mmchs1_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2340 static struct clk mmchs2_fck
;
2342 static struct clk_hw_omap mmchs2_fck_hw
= {
2346 .ops
= &clkhwops_wait
,
2347 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2348 .enable_bit
= OMAP3430_EN_MMC2_SHIFT
,
2349 .clkdm_name
= "core_l4_clkdm",
2352 DEFINE_STRUCT_CLK(mmchs2_fck
, csi2_96m_fck_parent_names
, aes2_ick_ops
);
2354 static struct clk mmchs2_ick
;
2356 static struct clk_hw_omap mmchs2_ick_hw
= {
2360 .ops
= &clkhwops_iclk_wait
,
2361 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2362 .enable_bit
= OMAP3430_EN_MMC2_SHIFT
,
2363 .clkdm_name
= "core_l4_clkdm",
2366 DEFINE_STRUCT_CLK(mmchs2_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2368 static struct clk mmchs3_fck
;
2370 static struct clk_hw_omap mmchs3_fck_hw
= {
2374 .ops
= &clkhwops_wait
,
2375 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2376 .enable_bit
= OMAP3430ES2_EN_MMC3_SHIFT
,
2377 .clkdm_name
= "core_l4_clkdm",
2380 DEFINE_STRUCT_CLK(mmchs3_fck
, csi2_96m_fck_parent_names
, aes2_ick_ops
);
2382 static struct clk mmchs3_ick
;
2384 static struct clk_hw_omap mmchs3_ick_hw
= {
2388 .ops
= &clkhwops_iclk_wait
,
2389 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2390 .enable_bit
= OMAP3430ES2_EN_MMC3_SHIFT
,
2391 .clkdm_name
= "core_l4_clkdm",
2394 DEFINE_STRUCT_CLK(mmchs3_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2396 static struct clk modem_fck
;
2398 static struct clk_hw_omap modem_fck_hw
= {
2402 .ops
= &clkhwops_iclk_wait
,
2403 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2404 .enable_bit
= OMAP3430_EN_MODEM_SHIFT
,
2405 .clkdm_name
= "d2d_clkdm",
2408 DEFINE_STRUCT_CLK(modem_fck
, dpll3_ck_parent_names
, aes2_ick_ops
);
2410 static struct clk mspro_fck
;
2412 static struct clk_hw_omap mspro_fck_hw
= {
2416 .ops
= &clkhwops_wait
,
2417 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2418 .enable_bit
= OMAP3430_EN_MSPRO_SHIFT
,
2419 .clkdm_name
= "core_l4_clkdm",
2422 DEFINE_STRUCT_CLK(mspro_fck
, csi2_96m_fck_parent_names
, aes2_ick_ops
);
2424 static struct clk mspro_ick
;
2426 static struct clk_hw_omap mspro_ick_hw
= {
2430 .ops
= &clkhwops_iclk_wait
,
2431 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2432 .enable_bit
= OMAP3430_EN_MSPRO_SHIFT
,
2433 .clkdm_name
= "core_l4_clkdm",
2436 DEFINE_STRUCT_CLK(mspro_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2438 static struct clk omap_192m_alwon_fck
;
2440 DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck
, NULL
);
2441 DEFINE_STRUCT_CLK(omap_192m_alwon_fck
, omap_96m_alwon_fck_parent_names
,
2444 static struct clk omap_32ksync_ick
;
2446 static struct clk_hw_omap omap_32ksync_ick_hw
= {
2448 .clk
= &omap_32ksync_ick
,
2450 .ops
= &clkhwops_iclk_wait
,
2451 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2452 .enable_bit
= OMAP3430_EN_32KSYNC_SHIFT
,
2453 .clkdm_name
= "wkup_clkdm",
2456 DEFINE_STRUCT_CLK(omap_32ksync_ick
, gpio1_ick_parent_names
, aes2_ick_ops
);
2458 static const struct clksel_rate omap_96m_alwon_fck_rates
[] = {
2459 { .div
= 1, .val
= 1, .flags
= RATE_IN_36XX
},
2460 { .div
= 2, .val
= 2, .flags
= RATE_IN_36XX
},
2464 static const struct clksel omap_96m_alwon_fck_clksel
[] = {
2465 { .parent
= &omap_192m_alwon_fck
, .rates
= omap_96m_alwon_fck_rates
},
2469 static struct clk omap_96m_alwon_fck_3630
;
2471 static const char *omap_96m_alwon_fck_3630_parent_names
[] = {
2472 "omap_192m_alwon_fck",
2475 static const struct clk_ops omap_96m_alwon_fck_3630_ops
= {
2476 .set_rate
= &omap2_clksel_set_rate
,
2477 .recalc_rate
= &omap2_clksel_recalc
,
2478 .round_rate
= &omap2_clksel_round_rate
,
2481 static struct clk_hw_omap omap_96m_alwon_fck_3630_hw
= {
2483 .clk
= &omap_96m_alwon_fck_3630
,
2485 .clksel
= omap_96m_alwon_fck_clksel
,
2486 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
2487 .clksel_mask
= OMAP3630_CLKSEL_96M_MASK
,
2490 static struct clk omap_96m_alwon_fck_3630
= {
2491 .name
= "omap_96m_alwon_fck",
2492 .hw
= &omap_96m_alwon_fck_3630_hw
.hw
,
2493 .parent_names
= omap_96m_alwon_fck_3630_parent_names
,
2494 .num_parents
= ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names
),
2495 .ops
= &omap_96m_alwon_fck_3630_ops
,
2498 static struct clk omapctrl_ick
;
2500 static struct clk_hw_omap omapctrl_ick_hw
= {
2502 .clk
= &omapctrl_ick
,
2504 .ops
= &clkhwops_iclk_wait
,
2505 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2506 .enable_bit
= OMAP3430_EN_OMAPCTRL_SHIFT
,
2507 .flags
= ENABLE_ON_INIT
,
2508 .clkdm_name
= "core_l4_clkdm",
2511 DEFINE_STRUCT_CLK(omapctrl_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2513 DEFINE_CLK_DIVIDER(pclk_fck
, "emu_src_ck", &emu_src_ck
, 0x0,
2514 OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2515 OMAP3430_CLKSEL_PCLK_SHIFT
, OMAP3430_CLKSEL_PCLK_WIDTH
,
2516 CLK_DIVIDER_ONE_BASED
, NULL
);
2518 DEFINE_CLK_DIVIDER(pclkx2_fck
, "emu_src_ck", &emu_src_ck
, 0x0,
2519 OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2520 OMAP3430_CLKSEL_PCLKX2_SHIFT
, OMAP3430_CLKSEL_PCLKX2_WIDTH
,
2521 CLK_DIVIDER_ONE_BASED
, NULL
);
2523 static struct clk per_48m_fck
;
2525 DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck
, "per_clkdm");
2526 DEFINE_STRUCT_CLK(per_48m_fck
, core_48m_fck_parent_names
, core_l4_ick_ops
);
2528 static struct clk security_l3_ick
;
2530 DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick
, NULL
);
2531 DEFINE_STRUCT_CLK(security_l3_ick
, core_l3_ick_parent_names
, core_ck_ops
);
2533 static struct clk pka_ick
;
2535 static const char *pka_ick_parent_names
[] = {
2539 static struct clk_hw_omap pka_ick_hw
= {
2543 .ops
= &clkhwops_iclk_wait
,
2544 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
2545 .enable_bit
= OMAP3430_EN_PKA_SHIFT
,
2548 DEFINE_STRUCT_CLK(pka_ick
, pka_ick_parent_names
, aes1_ick_ops
);
2550 DEFINE_CLK_DIVIDER(rm_ick
, "l4_ick", &l4_ick
, 0x0,
2551 OMAP_CM_REGADDR(WKUP_MOD
, CM_CLKSEL
),
2552 OMAP3430_CLKSEL_RM_SHIFT
, OMAP3430_CLKSEL_RM_WIDTH
,
2553 CLK_DIVIDER_ONE_BASED
, NULL
);
2555 static struct clk rng_ick
;
2557 static struct clk_hw_omap rng_ick_hw
= {
2561 .ops
= &clkhwops_iclk_wait
,
2562 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
2563 .enable_bit
= OMAP3430_EN_RNG_SHIFT
,
2566 DEFINE_STRUCT_CLK(rng_ick
, aes1_ick_parent_names
, aes1_ick_ops
);
2568 static struct clk sad2d_ick
;
2570 static struct clk_hw_omap sad2d_ick_hw
= {
2574 .ops
= &clkhwops_iclk_wait
,
2575 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2576 .enable_bit
= OMAP3430_EN_SAD2D_SHIFT
,
2577 .clkdm_name
= "d2d_clkdm",
2580 DEFINE_STRUCT_CLK(sad2d_ick
, core_l3_ick_parent_names
, aes2_ick_ops
);
2582 static struct clk sdrc_ick
;
2584 static struct clk_hw_omap sdrc_ick_hw
= {
2588 .ops
= &clkhwops_wait
,
2589 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2590 .enable_bit
= OMAP3430_EN_SDRC_SHIFT
,
2591 .flags
= ENABLE_ON_INIT
,
2592 .clkdm_name
= "core_l3_clkdm",
2595 DEFINE_STRUCT_CLK(sdrc_ick
, ipss_ick_parent_names
, aes2_ick_ops
);
2597 static const struct clksel_rate sgx_core_rates
[] = {
2598 { .div
= 2, .val
= 5, .flags
= RATE_IN_36XX
},
2599 { .div
= 3, .val
= 0, .flags
= RATE_IN_3XXX
},
2600 { .div
= 4, .val
= 1, .flags
= RATE_IN_3XXX
},
2601 { .div
= 6, .val
= 2, .flags
= RATE_IN_3XXX
},
2605 static const struct clksel_rate sgx_96m_rates
[] = {
2606 { .div
= 1, .val
= 3, .flags
= RATE_IN_3XXX
},
2610 static const struct clksel_rate sgx_192m_rates
[] = {
2611 { .div
= 1, .val
= 4, .flags
= RATE_IN_36XX
},
2615 static const struct clksel_rate sgx_corex2_rates
[] = {
2616 { .div
= 3, .val
= 6, .flags
= RATE_IN_36XX
},
2617 { .div
= 5, .val
= 7, .flags
= RATE_IN_36XX
},
2621 static const struct clksel sgx_clksel
[] = {
2622 { .parent
= &core_ck
, .rates
= sgx_core_rates
},
2623 { .parent
= &cm_96m_fck
, .rates
= sgx_96m_rates
},
2624 { .parent
= &omap_192m_alwon_fck
, .rates
= sgx_192m_rates
},
2625 { .parent
= &corex2_fck
, .rates
= sgx_corex2_rates
},
2629 static const char *sgx_fck_parent_names
[] = {
2630 "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck",
2633 static struct clk sgx_fck
;
2635 static const struct clk_ops sgx_fck_ops
= {
2636 .init
= &omap2_init_clk_clkdm
,
2637 .enable
= &omap2_dflt_clk_enable
,
2638 .disable
= &omap2_dflt_clk_disable
,
2639 .is_enabled
= &omap2_dflt_clk_is_enabled
,
2640 .recalc_rate
= &omap2_clksel_recalc
,
2641 .set_rate
= &omap2_clksel_set_rate
,
2642 .round_rate
= &omap2_clksel_round_rate
,
2643 .get_parent
= &omap2_clksel_find_parent_index
,
2644 .set_parent
= &omap2_clksel_set_parent
,
2647 DEFINE_CLK_OMAP_MUX_GATE(sgx_fck
, "sgx_clkdm", sgx_clksel
,
2648 OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD
, CM_CLKSEL
),
2649 OMAP3430ES2_CLKSEL_SGX_MASK
,
2650 OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD
, CM_FCLKEN
),
2651 OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT
,
2652 &clkhwops_wait
, sgx_fck_parent_names
, sgx_fck_ops
);
2654 static struct clk sgx_ick
;
2656 static struct clk_hw_omap sgx_ick_hw
= {
2660 .ops
= &clkhwops_wait
,
2661 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD
, CM_ICLKEN
),
2662 .enable_bit
= OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT
,
2663 .clkdm_name
= "sgx_clkdm",
2666 DEFINE_STRUCT_CLK(sgx_ick
, core_l3_ick_parent_names
, aes2_ick_ops
);
2668 static struct clk sha11_ick
;
2670 static struct clk_hw_omap sha11_ick_hw
= {
2674 .ops
= &clkhwops_iclk_wait
,
2675 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
2676 .enable_bit
= OMAP3430_EN_SHA11_SHIFT
,
2679 DEFINE_STRUCT_CLK(sha11_ick
, aes1_ick_parent_names
, aes1_ick_ops
);
2681 static struct clk sha12_ick
;
2683 static struct clk_hw_omap sha12_ick_hw
= {
2687 .ops
= &clkhwops_iclk_wait
,
2688 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2689 .enable_bit
= OMAP3430_EN_SHA12_SHIFT
,
2690 .clkdm_name
= "core_l4_clkdm",
2693 DEFINE_STRUCT_CLK(sha12_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2695 static struct clk sr1_fck
;
2697 static struct clk_hw_omap sr1_fck_hw
= {
2701 .ops
= &clkhwops_wait
,
2702 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
2703 .enable_bit
= OMAP3430_EN_SR1_SHIFT
,
2704 .clkdm_name
= "wkup_clkdm",
2707 DEFINE_STRUCT_CLK(sr1_fck
, dpll3_ck_parent_names
, aes2_ick_ops
);
2709 static struct clk sr2_fck
;
2711 static struct clk_hw_omap sr2_fck_hw
= {
2715 .ops
= &clkhwops_wait
,
2716 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
2717 .enable_bit
= OMAP3430_EN_SR2_SHIFT
,
2718 .clkdm_name
= "wkup_clkdm",
2721 DEFINE_STRUCT_CLK(sr2_fck
, dpll3_ck_parent_names
, aes2_ick_ops
);
2723 static struct clk sr_l4_ick
;
2725 DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick
, "core_l4_clkdm");
2726 DEFINE_STRUCT_CLK(sr_l4_ick
, security_l4_ick2_parent_names
, core_l4_ick_ops
);
2728 static struct clk ssi_l4_ick
;
2730 DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick
, "core_l4_clkdm");
2731 DEFINE_STRUCT_CLK(ssi_l4_ick
, security_l4_ick2_parent_names
, core_l4_ick_ops
);
2733 static struct clk ssi_ick_3430es1
;
2735 static const char *ssi_ick_3430es1_parent_names
[] = {
2739 static struct clk_hw_omap ssi_ick_3430es1_hw
= {
2741 .clk
= &ssi_ick_3430es1
,
2743 .ops
= &clkhwops_iclk
,
2744 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2745 .enable_bit
= OMAP3430_EN_SSI_SHIFT
,
2746 .clkdm_name
= "core_l4_clkdm",
2749 DEFINE_STRUCT_CLK(ssi_ick_3430es1
, ssi_ick_3430es1_parent_names
, aes2_ick_ops
);
2751 static struct clk ssi_ick_3430es2
;
2753 static struct clk_hw_omap ssi_ick_3430es2_hw
= {
2755 .clk
= &ssi_ick_3430es2
,
2757 .ops
= &clkhwops_omap3430es2_iclk_ssi_wait
,
2758 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2759 .enable_bit
= OMAP3430_EN_SSI_SHIFT
,
2760 .clkdm_name
= "core_l4_clkdm",
2763 DEFINE_STRUCT_CLK(ssi_ick_3430es2
, ssi_ick_3430es1_parent_names
, aes2_ick_ops
);
2765 static const struct clksel_rate ssi_ssr_corex2_rates
[] = {
2766 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
2767 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
2768 { .div
= 3, .val
= 3, .flags
= RATE_IN_3XXX
},
2769 { .div
= 4, .val
= 4, .flags
= RATE_IN_3XXX
},
2770 { .div
= 6, .val
= 6, .flags
= RATE_IN_3XXX
},
2771 { .div
= 8, .val
= 8, .flags
= RATE_IN_3XXX
},
2775 static const struct clksel ssi_ssr_clksel
[] = {
2776 { .parent
= &corex2_fck
, .rates
= ssi_ssr_corex2_rates
},
2780 static const char *ssi_ssr_fck_3430es1_parent_names
[] = {
2784 static const struct clk_ops ssi_ssr_fck_3430es1_ops
= {
2785 .init
= &omap2_init_clk_clkdm
,
2786 .enable
= &omap2_dflt_clk_enable
,
2787 .disable
= &omap2_dflt_clk_disable
,
2788 .is_enabled
= &omap2_dflt_clk_is_enabled
,
2789 .recalc_rate
= &omap2_clksel_recalc
,
2790 .set_rate
= &omap2_clksel_set_rate
,
2791 .round_rate
= &omap2_clksel_round_rate
,
2794 DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es1
, "core_l4_clkdm",
2795 ssi_ssr_clksel
, OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
2796 OMAP3430_CLKSEL_SSI_MASK
,
2797 OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2798 OMAP3430_EN_SSI_SHIFT
,
2799 NULL
, ssi_ssr_fck_3430es1_parent_names
,
2800 ssi_ssr_fck_3430es1_ops
);
2802 DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2
, "core_l4_clkdm",
2803 ssi_ssr_clksel
, OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
2804 OMAP3430_CLKSEL_SSI_MASK
,
2805 OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2806 OMAP3430_EN_SSI_SHIFT
,
2807 NULL
, ssi_ssr_fck_3430es1_parent_names
,
2808 ssi_ssr_fck_3430es1_ops
);
2810 DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1
, "ssi_ssr_fck_3430es1",
2811 &ssi_ssr_fck_3430es1
, 0x0, 1, 2);
2813 DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2
, "ssi_ssr_fck_3430es2",
2814 &ssi_ssr_fck_3430es2
, 0x0, 1, 2);
2816 static struct clk sys_clkout1
;
2818 static const char *sys_clkout1_parent_names
[] = {
2822 static struct clk_hw_omap sys_clkout1_hw
= {
2824 .clk
= &sys_clkout1
,
2826 .enable_reg
= OMAP3430_PRM_CLKOUT_CTRL
,
2827 .enable_bit
= OMAP3430_CLKOUT_EN_SHIFT
,
2830 DEFINE_STRUCT_CLK(sys_clkout1
, sys_clkout1_parent_names
, aes1_ick_ops
);
2832 DEFINE_CLK_DIVIDER(sys_clkout2
, "clkout2_src_ck", &clkout2_src_ck
, 0x0,
2833 OMAP3430_CM_CLKOUT_CTRL
, OMAP3430_CLKOUT2_DIV_SHIFT
,
2834 OMAP3430_CLKOUT2_DIV_WIDTH
, CLK_DIVIDER_POWER_OF_TWO
, NULL
);
2836 DEFINE_CLK_MUX(traceclk_src_fck
, emu_src_ck_parent_names
, NULL
, 0x0,
2837 OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2838 OMAP3430_TRACE_MUX_CTRL_SHIFT
, OMAP3430_TRACE_MUX_CTRL_WIDTH
,
2841 DEFINE_CLK_DIVIDER(traceclk_fck
, "traceclk_src_fck", &traceclk_src_fck
, 0x0,
2842 OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2843 OMAP3430_CLKSEL_TRACECLK_SHIFT
,
2844 OMAP3430_CLKSEL_TRACECLK_WIDTH
, CLK_DIVIDER_ONE_BASED
, NULL
);
2846 static struct clk ts_fck
;
2848 static struct clk_hw_omap ts_fck_hw
= {
2852 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP3430ES2_CM_FCLKEN3
),
2853 .enable_bit
= OMAP3430ES2_EN_TS_SHIFT
,
2854 .clkdm_name
= "core_l4_clkdm",
2857 DEFINE_STRUCT_CLK(ts_fck
, wkup_32k_fck_parent_names
, aes2_ick_ops
);
2859 static struct clk uart1_fck
;
2861 static struct clk_hw_omap uart1_fck_hw
= {
2865 .ops
= &clkhwops_wait
,
2866 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2867 .enable_bit
= OMAP3430_EN_UART1_SHIFT
,
2868 .clkdm_name
= "core_l4_clkdm",
2871 DEFINE_STRUCT_CLK(uart1_fck
, fshostusb_fck_parent_names
, aes2_ick_ops
);
2873 static struct clk uart1_ick
;
2875 static struct clk_hw_omap uart1_ick_hw
= {
2879 .ops
= &clkhwops_iclk_wait
,
2880 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2881 .enable_bit
= OMAP3430_EN_UART1_SHIFT
,
2882 .clkdm_name
= "core_l4_clkdm",
2885 DEFINE_STRUCT_CLK(uart1_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2887 static struct clk uart2_fck
;
2889 static struct clk_hw_omap uart2_fck_hw
= {
2893 .ops
= &clkhwops_wait
,
2894 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2895 .enable_bit
= OMAP3430_EN_UART2_SHIFT
,
2896 .clkdm_name
= "core_l4_clkdm",
2899 DEFINE_STRUCT_CLK(uart2_fck
, fshostusb_fck_parent_names
, aes2_ick_ops
);
2901 static struct clk uart2_ick
;
2903 static struct clk_hw_omap uart2_ick_hw
= {
2907 .ops
= &clkhwops_iclk_wait
,
2908 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2909 .enable_bit
= OMAP3430_EN_UART2_SHIFT
,
2910 .clkdm_name
= "core_l4_clkdm",
2913 DEFINE_STRUCT_CLK(uart2_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2915 static struct clk uart3_fck
;
2917 static const char *uart3_fck_parent_names
[] = {
2921 static struct clk_hw_omap uart3_fck_hw
= {
2925 .ops
= &clkhwops_wait
,
2926 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2927 .enable_bit
= OMAP3430_EN_UART3_SHIFT
,
2928 .clkdm_name
= "per_clkdm",
2931 DEFINE_STRUCT_CLK(uart3_fck
, uart3_fck_parent_names
, aes2_ick_ops
);
2933 static struct clk uart3_ick
;
2935 static struct clk_hw_omap uart3_ick_hw
= {
2939 .ops
= &clkhwops_iclk_wait
,
2940 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2941 .enable_bit
= OMAP3430_EN_UART3_SHIFT
,
2942 .clkdm_name
= "per_clkdm",
2945 DEFINE_STRUCT_CLK(uart3_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
2947 static struct clk uart4_fck
;
2949 static struct clk_hw_omap uart4_fck_hw
= {
2953 .ops
= &clkhwops_wait
,
2954 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2955 .enable_bit
= OMAP3630_EN_UART4_SHIFT
,
2956 .clkdm_name
= "per_clkdm",
2959 DEFINE_STRUCT_CLK(uart4_fck
, uart3_fck_parent_names
, aes2_ick_ops
);
2961 static struct clk uart4_fck_am35xx
;
2963 static struct clk_hw_omap uart4_fck_am35xx_hw
= {
2965 .clk
= &uart4_fck_am35xx
,
2967 .ops
= &clkhwops_wait
,
2968 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2969 .enable_bit
= AM35XX_EN_UART4_SHIFT
,
2970 .clkdm_name
= "core_l4_clkdm",
2973 DEFINE_STRUCT_CLK(uart4_fck_am35xx
, fshostusb_fck_parent_names
, aes2_ick_ops
);
2975 static struct clk uart4_ick
;
2977 static struct clk_hw_omap uart4_ick_hw
= {
2981 .ops
= &clkhwops_iclk_wait
,
2982 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2983 .enable_bit
= OMAP3630_EN_UART4_SHIFT
,
2984 .clkdm_name
= "per_clkdm",
2987 DEFINE_STRUCT_CLK(uart4_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
2989 static struct clk uart4_ick_am35xx
;
2991 static struct clk_hw_omap uart4_ick_am35xx_hw
= {
2993 .clk
= &uart4_ick_am35xx
,
2995 .ops
= &clkhwops_iclk_wait
,
2996 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2997 .enable_bit
= AM35XX_EN_UART4_SHIFT
,
2998 .clkdm_name
= "core_l4_clkdm",
3001 DEFINE_STRUCT_CLK(uart4_ick_am35xx
, aes2_ick_parent_names
, aes2_ick_ops
);
3003 static const struct clksel_rate div2_rates
[] = {
3004 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
3005 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
3009 static const struct clksel usb_l4_clksel
[] = {
3010 { .parent
= &l4_ick
, .rates
= div2_rates
},
3014 static const char *usb_l4_ick_parent_names
[] = {
3018 DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick
, "core_l4_clkdm", usb_l4_clksel
,
3019 OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
3020 OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK
,
3021 OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
3022 OMAP3430ES1_EN_FSHOSTUSB_SHIFT
,
3023 &clkhwops_iclk_wait
, usb_l4_ick_parent_names
,
3024 ssi_ssr_fck_3430es1_ops
);
3026 static struct clk usbhost_120m_fck
;
3028 static const char *usbhost_120m_fck_parent_names
[] = {
3032 static struct clk_hw_omap usbhost_120m_fck_hw
= {
3034 .clk
= &usbhost_120m_fck
,
3036 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD
, CM_FCLKEN
),
3037 .enable_bit
= OMAP3430ES2_EN_USBHOST2_SHIFT
,
3038 .clkdm_name
= "usbhost_clkdm",
3041 DEFINE_STRUCT_CLK(usbhost_120m_fck
, usbhost_120m_fck_parent_names
,
3044 static struct clk usbhost_48m_fck
;
3046 static struct clk_hw_omap usbhost_48m_fck_hw
= {
3048 .clk
= &usbhost_48m_fck
,
3050 .ops
= &clkhwops_omap3430es2_dss_usbhost_wait
,
3051 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD
, CM_FCLKEN
),
3052 .enable_bit
= OMAP3430ES2_EN_USBHOST1_SHIFT
,
3053 .clkdm_name
= "usbhost_clkdm",
3056 DEFINE_STRUCT_CLK(usbhost_48m_fck
, core_48m_fck_parent_names
, aes2_ick_ops
);
3058 static struct clk usbhost_ick
;
3060 static struct clk_hw_omap usbhost_ick_hw
= {
3062 .clk
= &usbhost_ick
,
3064 .ops
= &clkhwops_omap3430es2_iclk_dss_usbhost_wait
,
3065 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD
, CM_ICLKEN
),
3066 .enable_bit
= OMAP3430ES2_EN_USBHOST_SHIFT
,
3067 .clkdm_name
= "usbhost_clkdm",
3070 DEFINE_STRUCT_CLK(usbhost_ick
, security_l4_ick2_parent_names
, aes2_ick_ops
);
3072 static struct clk usbtll_fck
;
3074 static struct clk_hw_omap usbtll_fck_hw
= {
3078 .ops
= &clkhwops_wait
,
3079 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP3430ES2_CM_FCLKEN3
),
3080 .enable_bit
= OMAP3430ES2_EN_USBTLL_SHIFT
,
3081 .clkdm_name
= "core_l4_clkdm",
3084 DEFINE_STRUCT_CLK(usbtll_fck
, usbhost_120m_fck_parent_names
, aes2_ick_ops
);
3086 static struct clk usbtll_ick
;
3088 static struct clk_hw_omap usbtll_ick_hw
= {
3092 .ops
= &clkhwops_iclk_wait
,
3093 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN3
),
3094 .enable_bit
= OMAP3430ES2_EN_USBTLL_SHIFT
,
3095 .clkdm_name
= "core_l4_clkdm",
3098 DEFINE_STRUCT_CLK(usbtll_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
3100 static const struct clksel_rate usim_96m_rates
[] = {
3101 { .div
= 2, .val
= 3, .flags
= RATE_IN_3XXX
},
3102 { .div
= 4, .val
= 4, .flags
= RATE_IN_3XXX
},
3103 { .div
= 8, .val
= 5, .flags
= RATE_IN_3XXX
},
3104 { .div
= 10, .val
= 6, .flags
= RATE_IN_3XXX
},
3108 static const struct clksel_rate usim_120m_rates
[] = {
3109 { .div
= 4, .val
= 7, .flags
= RATE_IN_3XXX
},
3110 { .div
= 8, .val
= 8, .flags
= RATE_IN_3XXX
},
3111 { .div
= 16, .val
= 9, .flags
= RATE_IN_3XXX
},
3112 { .div
= 20, .val
= 10, .flags
= RATE_IN_3XXX
},
3116 static const struct clksel usim_clksel
[] = {
3117 { .parent
= &omap_96m_fck
, .rates
= usim_96m_rates
},
3118 { .parent
= &dpll5_m2_ck
, .rates
= usim_120m_rates
},
3119 { .parent
= &sys_ck
, .rates
= div2_rates
},
3123 static const char *usim_fck_parent_names
[] = {
3124 "omap_96m_fck", "dpll5_m2_ck", "sys_ck",
3127 static struct clk usim_fck
;
3129 static const struct clk_ops usim_fck_ops
= {
3130 .enable
= &omap2_dflt_clk_enable
,
3131 .disable
= &omap2_dflt_clk_disable
,
3132 .is_enabled
= &omap2_dflt_clk_is_enabled
,
3133 .recalc_rate
= &omap2_clksel_recalc
,
3134 .get_parent
= &omap2_clksel_find_parent_index
,
3135 .set_parent
= &omap2_clksel_set_parent
,
3138 DEFINE_CLK_OMAP_MUX_GATE(usim_fck
, NULL
, usim_clksel
,
3139 OMAP_CM_REGADDR(WKUP_MOD
, CM_CLKSEL
),
3140 OMAP3430ES2_CLKSEL_USIMOCP_MASK
,
3141 OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
3142 OMAP3430ES2_EN_USIMOCP_SHIFT
, &clkhwops_wait
,
3143 usim_fck_parent_names
, usim_fck_ops
);
3145 static struct clk usim_ick
;
3147 static struct clk_hw_omap usim_ick_hw
= {
3151 .ops
= &clkhwops_iclk_wait
,
3152 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
3153 .enable_bit
= OMAP3430ES2_EN_USIMOCP_SHIFT
,
3154 .clkdm_name
= "wkup_clkdm",
3157 DEFINE_STRUCT_CLK(usim_ick
, gpio1_ick_parent_names
, aes2_ick_ops
);
3159 static struct clk vpfe_fck
;
3161 static const char *vpfe_fck_parent_names
[] = {
3165 static struct clk_hw_omap vpfe_fck_hw
= {
3169 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
3170 .enable_bit
= AM35XX_VPFE_FCLK_SHIFT
,
3173 DEFINE_STRUCT_CLK(vpfe_fck
, vpfe_fck_parent_names
, aes1_ick_ops
);
3175 static struct clk vpfe_ick
;
3177 static struct clk_hw_omap vpfe_ick_hw
= {
3181 .ops
= &clkhwops_am35xx_ipss_module_wait
,
3182 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
3183 .enable_bit
= AM35XX_VPFE_VBUSP_CLK_SHIFT
,
3184 .clkdm_name
= "core_l3_clkdm",
3187 DEFINE_STRUCT_CLK(vpfe_ick
, emac_ick_parent_names
, aes2_ick_ops
);
3189 static struct clk wdt1_fck
;
3191 DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck
, "wkup_clkdm");
3192 DEFINE_STRUCT_CLK(wdt1_fck
, gpt12_fck_parent_names
, core_l4_ick_ops
);
3194 static struct clk wdt1_ick
;
3196 static struct clk_hw_omap wdt1_ick_hw
= {
3200 .ops
= &clkhwops_iclk_wait
,
3201 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
3202 .enable_bit
= OMAP3430_EN_WDT1_SHIFT
,
3203 .clkdm_name
= "wkup_clkdm",
3206 DEFINE_STRUCT_CLK(wdt1_ick
, gpio1_ick_parent_names
, aes2_ick_ops
);
3208 static struct clk wdt2_fck
;
3210 static struct clk_hw_omap wdt2_fck_hw
= {
3214 .ops
= &clkhwops_wait
,
3215 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
3216 .enable_bit
= OMAP3430_EN_WDT2_SHIFT
,
3217 .clkdm_name
= "wkup_clkdm",
3220 DEFINE_STRUCT_CLK(wdt2_fck
, gpio1_dbck_parent_names
, aes2_ick_ops
);
3222 static struct clk wdt2_ick
;
3224 static struct clk_hw_omap wdt2_ick_hw
= {
3228 .ops
= &clkhwops_iclk_wait
,
3229 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
3230 .enable_bit
= OMAP3430_EN_WDT2_SHIFT
,
3231 .clkdm_name
= "wkup_clkdm",
3234 DEFINE_STRUCT_CLK(wdt2_ick
, gpio1_ick_parent_names
, aes2_ick_ops
);
3236 static struct clk wdt3_fck
;
3238 static struct clk_hw_omap wdt3_fck_hw
= {
3242 .ops
= &clkhwops_wait
,
3243 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
3244 .enable_bit
= OMAP3430_EN_WDT3_SHIFT
,
3245 .clkdm_name
= "per_clkdm",
3248 DEFINE_STRUCT_CLK(wdt3_fck
, gpio2_dbck_parent_names
, aes2_ick_ops
);
3250 static struct clk wdt3_ick
;
3252 static struct clk_hw_omap wdt3_ick_hw
= {
3256 .ops
= &clkhwops_iclk_wait
,
3257 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
3258 .enable_bit
= OMAP3430_EN_WDT3_SHIFT
,
3259 .clkdm_name
= "per_clkdm",
3262 DEFINE_STRUCT_CLK(wdt3_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
3265 * clocks specific to omap3430es1
3267 static struct omap_clk omap3430es1_clks
[] = {
3268 CLK(NULL
, "gfx_l3_ck", &gfx_l3_ck
),
3269 CLK(NULL
, "gfx_l3_fck", &gfx_l3_fck
),
3270 CLK(NULL
, "gfx_l3_ick", &gfx_l3_ick
),
3271 CLK(NULL
, "gfx_cg1_ck", &gfx_cg1_ck
),
3272 CLK(NULL
, "gfx_cg2_ck", &gfx_cg2_ck
),
3273 CLK(NULL
, "d2d_26m_fck", &d2d_26m_fck
),
3274 CLK(NULL
, "fshostusb_fck", &fshostusb_fck
),
3275 CLK(NULL
, "ssi_ssr_fck", &ssi_ssr_fck_3430es1
),
3276 CLK(NULL
, "ssi_sst_fck", &ssi_sst_fck_3430es1
),
3277 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1
),
3278 CLK(NULL
, "hsotgusb_ick", &hsotgusb_ick_3430es1
),
3279 CLK(NULL
, "fac_ick", &fac_ick
),
3280 CLK(NULL
, "ssi_ick", &ssi_ick_3430es1
),
3281 CLK(NULL
, "usb_l4_ick", &usb_l4_ick
),
3282 CLK(NULL
, "dss1_alwon_fck", &dss1_alwon_fck_3430es1
),
3283 CLK("omapdss_dss", "ick", &dss_ick_3430es1
),
3284 CLK(NULL
, "dss_ick", &dss_ick_3430es1
),
3288 * clocks specific to am35xx
3290 static struct omap_clk am35xx_clks
[] = {
3291 CLK(NULL
, "ipss_ick", &ipss_ick
),
3292 CLK(NULL
, "rmii_ck", &rmii_ck
),
3293 CLK(NULL
, "pclk_ck", &pclk_ck
),
3294 CLK(NULL
, "emac_ick", &emac_ick
),
3295 CLK(NULL
, "emac_fck", &emac_fck
),
3296 CLK("davinci_emac.0", NULL
, &emac_ick
),
3297 CLK("davinci_mdio.0", NULL
, &emac_fck
),
3298 CLK("vpfe-capture", "master", &vpfe_ick
),
3299 CLK("vpfe-capture", "slave", &vpfe_fck
),
3300 CLK(NULL
, "hsotgusb_ick", &hsotgusb_ick_am35xx
),
3301 CLK(NULL
, "hsotgusb_fck", &hsotgusb_fck_am35xx
),
3302 CLK(NULL
, "hecc_ck", &hecc_ck
),
3303 CLK(NULL
, "uart4_ick", &uart4_ick_am35xx
),
3304 CLK(NULL
, "uart4_fck", &uart4_fck_am35xx
),
3308 * clocks specific to omap36xx
3310 static struct omap_clk omap36xx_clks
[] = {
3311 CLK(NULL
, "omap_192m_alwon_fck", &omap_192m_alwon_fck
),
3312 CLK(NULL
, "uart4_fck", &uart4_fck
),
3316 * clocks common to omap36xx omap34xx
3318 static struct omap_clk omap34xx_omap36xx_clks
[] = {
3319 CLK(NULL
, "aes1_ick", &aes1_ick
),
3320 CLK("omap_rng", "ick", &rng_ick
),
3321 CLK("omap3-rom-rng", "ick", &rng_ick
),
3322 CLK(NULL
, "sha11_ick", &sha11_ick
),
3323 CLK(NULL
, "des1_ick", &des1_ick
),
3324 CLK(NULL
, "cam_mclk", &cam_mclk
),
3325 CLK(NULL
, "cam_ick", &cam_ick
),
3326 CLK(NULL
, "csi2_96m_fck", &csi2_96m_fck
),
3327 CLK(NULL
, "security_l3_ick", &security_l3_ick
),
3328 CLK(NULL
, "pka_ick", &pka_ick
),
3329 CLK(NULL
, "icr_ick", &icr_ick
),
3330 CLK("omap-aes", "ick", &aes2_ick
),
3331 CLK("omap-sham", "ick", &sha12_ick
),
3332 CLK(NULL
, "des2_ick", &des2_ick
),
3333 CLK(NULL
, "mspro_ick", &mspro_ick
),
3334 CLK(NULL
, "mailboxes_ick", &mailboxes_ick
),
3335 CLK(NULL
, "ssi_l4_ick", &ssi_l4_ick
),
3336 CLK(NULL
, "sr1_fck", &sr1_fck
),
3337 CLK(NULL
, "sr2_fck", &sr2_fck
),
3338 CLK(NULL
, "sr_l4_ick", &sr_l4_ick
),
3339 CLK(NULL
, "security_l4_ick2", &security_l4_ick2
),
3340 CLK(NULL
, "wkup_l4_ick", &wkup_l4_ick
),
3341 CLK(NULL
, "dpll2_fck", &dpll2_fck
),
3342 CLK(NULL
, "iva2_ck", &iva2_ck
),
3343 CLK(NULL
, "modem_fck", &modem_fck
),
3344 CLK(NULL
, "sad2d_ick", &sad2d_ick
),
3345 CLK(NULL
, "mad2d_ick", &mad2d_ick
),
3346 CLK(NULL
, "mspro_fck", &mspro_fck
),
3347 CLK(NULL
, "dpll2_ck", &dpll2_ck
),
3348 CLK(NULL
, "dpll2_m2_ck", &dpll2_m2_ck
),
3352 * clocks common to omap36xx and omap3430es2plus
3354 static struct omap_clk omap36xx_omap3430es2plus_clks
[] = {
3355 CLK(NULL
, "ssi_ssr_fck", &ssi_ssr_fck_3430es2
),
3356 CLK(NULL
, "ssi_sst_fck", &ssi_sst_fck_3430es2
),
3357 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2
),
3358 CLK(NULL
, "hsotgusb_ick", &hsotgusb_ick_3430es2
),
3359 CLK(NULL
, "ssi_ick", &ssi_ick_3430es2
),
3360 CLK(NULL
, "usim_fck", &usim_fck
),
3361 CLK(NULL
, "usim_ick", &usim_ick
),
3365 * clocks common to am35xx omap36xx and omap3430es2plus
3367 static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks
[] = {
3368 CLK(NULL
, "virt_16_8m_ck", &virt_16_8m_ck
),
3369 CLK(NULL
, "dpll5_ck", &dpll5_ck
),
3370 CLK(NULL
, "dpll5_m2_ck", &dpll5_m2_ck
),
3371 CLK(NULL
, "sgx_fck", &sgx_fck
),
3372 CLK(NULL
, "sgx_ick", &sgx_ick
),
3373 CLK(NULL
, "cpefuse_fck", &cpefuse_fck
),
3374 CLK(NULL
, "ts_fck", &ts_fck
),
3375 CLK(NULL
, "usbtll_fck", &usbtll_fck
),
3376 CLK(NULL
, "usbtll_ick", &usbtll_ick
),
3377 CLK("omap_hsmmc.2", "ick", &mmchs3_ick
),
3378 CLK(NULL
, "mmchs3_ick", &mmchs3_ick
),
3379 CLK(NULL
, "mmchs3_fck", &mmchs3_fck
),
3380 CLK(NULL
, "dss1_alwon_fck", &dss1_alwon_fck_3430es2
),
3381 CLK("omapdss_dss", "ick", &dss_ick_3430es2
),
3382 CLK(NULL
, "dss_ick", &dss_ick_3430es2
),
3383 CLK(NULL
, "usbhost_120m_fck", &usbhost_120m_fck
),
3384 CLK(NULL
, "usbhost_48m_fck", &usbhost_48m_fck
),
3385 CLK(NULL
, "usbhost_ick", &usbhost_ick
),
3391 static struct omap_clk omap3xxx_clks
[] = {
3392 CLK(NULL
, "apb_pclk", &dummy_apb_pclk
),
3393 CLK(NULL
, "omap_32k_fck", &omap_32k_fck
),
3394 CLK(NULL
, "virt_12m_ck", &virt_12m_ck
),
3395 CLK(NULL
, "virt_13m_ck", &virt_13m_ck
),
3396 CLK(NULL
, "virt_19200000_ck", &virt_19200000_ck
),
3397 CLK(NULL
, "virt_26000000_ck", &virt_26000000_ck
),
3398 CLK(NULL
, "virt_38_4m_ck", &virt_38_4m_ck
),
3399 CLK(NULL
, "osc_sys_ck", &osc_sys_ck
),
3400 CLK("twl", "fck", &osc_sys_ck
),
3401 CLK(NULL
, "sys_ck", &sys_ck
),
3402 CLK(NULL
, "omap_96m_alwon_fck", &omap_96m_alwon_fck
),
3403 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck
),
3404 CLK(NULL
, "sys_altclk", &sys_altclk
),
3405 CLK(NULL
, "mcbsp_clks", &mcbsp_clks
),
3406 CLK(NULL
, "sys_clkout1", &sys_clkout1
),
3407 CLK(NULL
, "dpll1_ck", &dpll1_ck
),
3408 CLK(NULL
, "dpll1_x2_ck", &dpll1_x2_ck
),
3409 CLK(NULL
, "dpll1_x2m2_ck", &dpll1_x2m2_ck
),
3410 CLK(NULL
, "dpll3_ck", &dpll3_ck
),
3411 CLK(NULL
, "core_ck", &core_ck
),
3412 CLK(NULL
, "dpll3_x2_ck", &dpll3_x2_ck
),
3413 CLK(NULL
, "dpll3_m2_ck", &dpll3_m2_ck
),
3414 CLK(NULL
, "dpll3_m2x2_ck", &dpll3_m2x2_ck
),
3415 CLK(NULL
, "dpll3_m3_ck", &dpll3_m3_ck
),
3416 CLK(NULL
, "dpll3_m3x2_ck", &dpll3_m3x2_ck
),
3417 CLK(NULL
, "dpll4_ck", &dpll4_ck
),
3418 CLK(NULL
, "dpll4_x2_ck", &dpll4_x2_ck
),
3419 CLK(NULL
, "omap_96m_fck", &omap_96m_fck
),
3420 CLK(NULL
, "cm_96m_fck", &cm_96m_fck
),
3421 CLK(NULL
, "omap_54m_fck", &omap_54m_fck
),
3422 CLK(NULL
, "omap_48m_fck", &omap_48m_fck
),
3423 CLK(NULL
, "omap_12m_fck", &omap_12m_fck
),
3424 CLK(NULL
, "dpll4_m2_ck", &dpll4_m2_ck
),
3425 CLK(NULL
, "dpll4_m2x2_ck", &dpll4_m2x2_ck
),
3426 CLK(NULL
, "dpll4_m3_ck", &dpll4_m3_ck
),
3427 CLK(NULL
, "dpll4_m3x2_ck", &dpll4_m3x2_ck
),
3428 CLK(NULL
, "dpll4_m4_ck", &dpll4_m4_ck
),
3429 CLK(NULL
, "dpll4_m4x2_ck", &dpll4_m4x2_ck
),
3430 CLK(NULL
, "dpll4_m5_ck", &dpll4_m5_ck
),
3431 CLK(NULL
, "dpll4_m5x2_ck", &dpll4_m5x2_ck
),
3432 CLK(NULL
, "dpll4_m6_ck", &dpll4_m6_ck
),
3433 CLK(NULL
, "dpll4_m6x2_ck", &dpll4_m6x2_ck
),
3434 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck
),
3435 CLK(NULL
, "clkout2_src_ck", &clkout2_src_ck
),
3436 CLK(NULL
, "sys_clkout2", &sys_clkout2
),
3437 CLK(NULL
, "corex2_fck", &corex2_fck
),
3438 CLK(NULL
, "dpll1_fck", &dpll1_fck
),
3439 CLK(NULL
, "mpu_ck", &mpu_ck
),
3440 CLK(NULL
, "arm_fck", &arm_fck
),
3441 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck
),
3442 CLK(NULL
, "l3_ick", &l3_ick
),
3443 CLK(NULL
, "l4_ick", &l4_ick
),
3444 CLK(NULL
, "rm_ick", &rm_ick
),
3445 CLK(NULL
, "gpt10_fck", &gpt10_fck
),
3446 CLK(NULL
, "gpt11_fck", &gpt11_fck
),
3447 CLK(NULL
, "core_96m_fck", &core_96m_fck
),
3448 CLK(NULL
, "mmchs2_fck", &mmchs2_fck
),
3449 CLK(NULL
, "mmchs1_fck", &mmchs1_fck
),
3450 CLK(NULL
, "i2c3_fck", &i2c3_fck
),
3451 CLK(NULL
, "i2c2_fck", &i2c2_fck
),
3452 CLK(NULL
, "i2c1_fck", &i2c1_fck
),
3453 CLK(NULL
, "mcbsp5_fck", &mcbsp5_fck
),
3454 CLK(NULL
, "mcbsp1_fck", &mcbsp1_fck
),
3455 CLK(NULL
, "core_48m_fck", &core_48m_fck
),
3456 CLK(NULL
, "mcspi4_fck", &mcspi4_fck
),
3457 CLK(NULL
, "mcspi3_fck", &mcspi3_fck
),
3458 CLK(NULL
, "mcspi2_fck", &mcspi2_fck
),
3459 CLK(NULL
, "mcspi1_fck", &mcspi1_fck
),
3460 CLK(NULL
, "uart2_fck", &uart2_fck
),
3461 CLK(NULL
, "uart1_fck", &uart1_fck
),
3462 CLK(NULL
, "core_12m_fck", &core_12m_fck
),
3463 CLK("omap_hdq.0", "fck", &hdq_fck
),
3464 CLK(NULL
, "hdq_fck", &hdq_fck
),
3465 CLK(NULL
, "core_l3_ick", &core_l3_ick
),
3466 CLK(NULL
, "sdrc_ick", &sdrc_ick
),
3467 CLK(NULL
, "gpmc_fck", &gpmc_fck
),
3468 CLK(NULL
, "core_l4_ick", &core_l4_ick
),
3469 CLK("omap_hsmmc.1", "ick", &mmchs2_ick
),
3470 CLK("omap_hsmmc.0", "ick", &mmchs1_ick
),
3471 CLK(NULL
, "mmchs2_ick", &mmchs2_ick
),
3472 CLK(NULL
, "mmchs1_ick", &mmchs1_ick
),
3473 CLK("omap_hdq.0", "ick", &hdq_ick
),
3474 CLK(NULL
, "hdq_ick", &hdq_ick
),
3475 CLK("omap2_mcspi.4", "ick", &mcspi4_ick
),
3476 CLK("omap2_mcspi.3", "ick", &mcspi3_ick
),
3477 CLK("omap2_mcspi.2", "ick", &mcspi2_ick
),
3478 CLK("omap2_mcspi.1", "ick", &mcspi1_ick
),
3479 CLK(NULL
, "mcspi4_ick", &mcspi4_ick
),
3480 CLK(NULL
, "mcspi3_ick", &mcspi3_ick
),
3481 CLK(NULL
, "mcspi2_ick", &mcspi2_ick
),
3482 CLK(NULL
, "mcspi1_ick", &mcspi1_ick
),
3483 CLK("omap_i2c.3", "ick", &i2c3_ick
),
3484 CLK("omap_i2c.2", "ick", &i2c2_ick
),
3485 CLK("omap_i2c.1", "ick", &i2c1_ick
),
3486 CLK(NULL
, "i2c3_ick", &i2c3_ick
),
3487 CLK(NULL
, "i2c2_ick", &i2c2_ick
),
3488 CLK(NULL
, "i2c1_ick", &i2c1_ick
),
3489 CLK(NULL
, "uart2_ick", &uart2_ick
),
3490 CLK(NULL
, "uart1_ick", &uart1_ick
),
3491 CLK(NULL
, "gpt11_ick", &gpt11_ick
),
3492 CLK(NULL
, "gpt10_ick", &gpt10_ick
),
3493 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick
),
3494 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick
),
3495 CLK(NULL
, "mcbsp5_ick", &mcbsp5_ick
),
3496 CLK(NULL
, "mcbsp1_ick", &mcbsp1_ick
),
3497 CLK(NULL
, "omapctrl_ick", &omapctrl_ick
),
3498 CLK(NULL
, "dss_tv_fck", &dss_tv_fck
),
3499 CLK(NULL
, "dss_96m_fck", &dss_96m_fck
),
3500 CLK(NULL
, "dss2_alwon_fck", &dss2_alwon_fck
),
3501 CLK(NULL
, "init_60m_fclk", &dummy_ck
),
3502 CLK(NULL
, "gpt1_fck", &gpt1_fck
),
3503 CLK(NULL
, "aes2_ick", &aes2_ick
),
3504 CLK(NULL
, "wkup_32k_fck", &wkup_32k_fck
),
3505 CLK(NULL
, "gpio1_dbck", &gpio1_dbck
),
3506 CLK(NULL
, "sha12_ick", &sha12_ick
),
3507 CLK(NULL
, "wdt2_fck", &wdt2_fck
),
3508 CLK("omap_wdt", "ick", &wdt2_ick
),
3509 CLK(NULL
, "wdt2_ick", &wdt2_ick
),
3510 CLK(NULL
, "wdt1_ick", &wdt1_ick
),
3511 CLK(NULL
, "gpio1_ick", &gpio1_ick
),
3512 CLK(NULL
, "omap_32ksync_ick", &omap_32ksync_ick
),
3513 CLK(NULL
, "gpt12_ick", &gpt12_ick
),
3514 CLK(NULL
, "gpt1_ick", &gpt1_ick
),
3515 CLK(NULL
, "per_96m_fck", &per_96m_fck
),
3516 CLK(NULL
, "per_48m_fck", &per_48m_fck
),
3517 CLK(NULL
, "uart3_fck", &uart3_fck
),
3518 CLK(NULL
, "gpt2_fck", &gpt2_fck
),
3519 CLK(NULL
, "gpt3_fck", &gpt3_fck
),
3520 CLK(NULL
, "gpt4_fck", &gpt4_fck
),
3521 CLK(NULL
, "gpt5_fck", &gpt5_fck
),
3522 CLK(NULL
, "gpt6_fck", &gpt6_fck
),
3523 CLK(NULL
, "gpt7_fck", &gpt7_fck
),
3524 CLK(NULL
, "gpt8_fck", &gpt8_fck
),
3525 CLK(NULL
, "gpt9_fck", &gpt9_fck
),
3526 CLK(NULL
, "per_32k_alwon_fck", &per_32k_alwon_fck
),
3527 CLK(NULL
, "gpio6_dbck", &gpio6_dbck
),
3528 CLK(NULL
, "gpio5_dbck", &gpio5_dbck
),
3529 CLK(NULL
, "gpio4_dbck", &gpio4_dbck
),
3530 CLK(NULL
, "gpio3_dbck", &gpio3_dbck
),
3531 CLK(NULL
, "gpio2_dbck", &gpio2_dbck
),
3532 CLK(NULL
, "wdt3_fck", &wdt3_fck
),
3533 CLK(NULL
, "per_l4_ick", &per_l4_ick
),
3534 CLK(NULL
, "gpio6_ick", &gpio6_ick
),
3535 CLK(NULL
, "gpio5_ick", &gpio5_ick
),
3536 CLK(NULL
, "gpio4_ick", &gpio4_ick
),
3537 CLK(NULL
, "gpio3_ick", &gpio3_ick
),
3538 CLK(NULL
, "gpio2_ick", &gpio2_ick
),
3539 CLK(NULL
, "wdt3_ick", &wdt3_ick
),
3540 CLK(NULL
, "uart3_ick", &uart3_ick
),
3541 CLK(NULL
, "uart4_ick", &uart4_ick
),
3542 CLK(NULL
, "gpt9_ick", &gpt9_ick
),
3543 CLK(NULL
, "gpt8_ick", &gpt8_ick
),
3544 CLK(NULL
, "gpt7_ick", &gpt7_ick
),
3545 CLK(NULL
, "gpt6_ick", &gpt6_ick
),
3546 CLK(NULL
, "gpt5_ick", &gpt5_ick
),
3547 CLK(NULL
, "gpt4_ick", &gpt4_ick
),
3548 CLK(NULL
, "gpt3_ick", &gpt3_ick
),
3549 CLK(NULL
, "gpt2_ick", &gpt2_ick
),
3550 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick
),
3551 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick
),
3552 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick
),
3553 CLK(NULL
, "mcbsp4_ick", &mcbsp2_ick
),
3554 CLK(NULL
, "mcbsp3_ick", &mcbsp3_ick
),
3555 CLK(NULL
, "mcbsp2_ick", &mcbsp4_ick
),
3556 CLK(NULL
, "mcbsp2_fck", &mcbsp2_fck
),
3557 CLK(NULL
, "mcbsp3_fck", &mcbsp3_fck
),
3558 CLK(NULL
, "mcbsp4_fck", &mcbsp4_fck
),
3559 CLK("etb", "emu_src_ck", &emu_src_ck
),
3560 CLK(NULL
, "emu_src_ck", &emu_src_ck
),
3561 CLK(NULL
, "pclk_fck", &pclk_fck
),
3562 CLK(NULL
, "pclkx2_fck", &pclkx2_fck
),
3563 CLK(NULL
, "atclk_fck", &atclk_fck
),
3564 CLK(NULL
, "traceclk_src_fck", &traceclk_src_fck
),
3565 CLK(NULL
, "traceclk_fck", &traceclk_fck
),
3566 CLK(NULL
, "secure_32k_fck", &secure_32k_fck
),
3567 CLK(NULL
, "gpt12_fck", &gpt12_fck
),
3568 CLK(NULL
, "wdt1_fck", &wdt1_fck
),
3569 CLK(NULL
, "timer_32k_ck", &omap_32k_fck
),
3570 CLK(NULL
, "timer_sys_ck", &sys_ck
),
3571 CLK(NULL
, "cpufreq_ck", &dpll1_ck
),
3574 static const char *enable_init_clks
[] = {
3580 int __init
omap3xxx_clk_init(void)
3582 if (omap3_has_192mhz_clk())
3583 omap_96m_alwon_fck
= omap_96m_alwon_fck_3630
;
3585 if (cpu_is_omap3630()) {
3586 dpll3_m3x2_ck
= dpll3_m3x2_ck_3630
;
3587 dpll4_m2x2_ck
= dpll4_m2x2_ck_3630
;
3588 dpll4_m3x2_ck
= dpll4_m3x2_ck_3630
;
3589 dpll4_m4x2_ck
= dpll4_m4x2_ck_3630
;
3590 dpll4_m5x2_ck
= dpll4_m5x2_ck_3630
;
3591 dpll4_m6x2_ck
= dpll4_m6x2_ck_3630
;
3595 * XXX This type of dynamic rewriting of the clock tree is
3596 * deprecated and should be revised soon.
3598 if (cpu_is_omap3630())
3599 dpll4_dd
= dpll4_dd_3630
;
3601 dpll4_dd
= dpll4_dd_34xx
;
3605 * 3505 must be tested before 3517, since 3517 returns true
3606 * for both AM3517 chips and AM3517 family chips, which
3607 * includes 3505. Unfortunately there's no obvious family
3608 * test for 3517/3505 :-(
3610 if (soc_is_am35xx()) {
3611 cpu_mask
= RATE_IN_34XX
;
3612 omap_clocks_register(am35xx_clks
, ARRAY_SIZE(am35xx_clks
));
3613 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks
,
3614 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks
));
3615 omap_clocks_register(omap3xxx_clks
, ARRAY_SIZE(omap3xxx_clks
));
3616 } else if (cpu_is_omap3630()) {
3617 cpu_mask
= (RATE_IN_34XX
| RATE_IN_36XX
);
3618 omap_clocks_register(omap36xx_clks
, ARRAY_SIZE(omap36xx_clks
));
3619 omap_clocks_register(omap36xx_omap3430es2plus_clks
,
3620 ARRAY_SIZE(omap36xx_omap3430es2plus_clks
));
3621 omap_clocks_register(omap34xx_omap36xx_clks
,
3622 ARRAY_SIZE(omap34xx_omap36xx_clks
));
3623 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks
,
3624 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks
));
3625 omap_clocks_register(omap3xxx_clks
, ARRAY_SIZE(omap3xxx_clks
));
3626 } else if (soc_is_am33xx()) {
3627 cpu_mask
= RATE_IN_AM33XX
;
3628 } else if (cpu_is_ti814x()) {
3629 cpu_mask
= RATE_IN_TI814X
;
3630 } else if (cpu_is_omap34xx()) {
3631 if (omap_rev() == OMAP3430_REV_ES1_0
) {
3632 cpu_mask
= RATE_IN_3430ES1
;
3633 omap_clocks_register(omap3430es1_clks
,
3634 ARRAY_SIZE(omap3430es1_clks
));
3635 omap_clocks_register(omap34xx_omap36xx_clks
,
3636 ARRAY_SIZE(omap34xx_omap36xx_clks
));
3637 omap_clocks_register(omap3xxx_clks
,
3638 ARRAY_SIZE(omap3xxx_clks
));
3641 * Assume that anything that we haven't matched yet
3642 * has 3430ES2-type clocks.
3644 cpu_mask
= RATE_IN_3430ES2PLUS
;
3645 omap_clocks_register(omap34xx_omap36xx_clks
,
3646 ARRAY_SIZE(omap34xx_omap36xx_clks
));
3647 omap_clocks_register(omap36xx_omap3430es2plus_clks
,
3648 ARRAY_SIZE(omap36xx_omap3430es2plus_clks
));
3649 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks
,
3650 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks
));
3651 omap_clocks_register(omap3xxx_clks
,
3652 ARRAY_SIZE(omap3xxx_clks
));
3655 WARN(1, "clock: could not identify OMAP3 variant\n");
3658 omap2_clk_disable_autoidle_all();
3660 omap2_clk_enable_init_clocks(enable_init_clks
,
3661 ARRAY_SIZE(enable_init_clks
));
3663 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3664 (clk_get_rate(&osc_sys_ck
) / 1000000),
3665 (clk_get_rate(&osc_sys_ck
) / 100000) % 10,
3666 (clk_get_rate(&core_ck
) / 1000000),
3667 (clk_get_rate(&arm_fck
) / 1000000));
3670 * Lock DPLL5 -- here only until other device init code can
3673 if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0
))
3674 omap3_clk_lock_dpll5();
3676 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3677 sdrc_ick_p
= clk_get(NULL
, "sdrc_ick");
3678 arm_fck_p
= clk_get(NULL
, "arm_fck");