arch/arm/mach-omap2/clkt34xx_dpll3m2.c

   1 /*
   2  * OMAP34xx M2 divider clock code
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Jouni Högander
   9  *
  10  * Parts of this code are based on code written by
  11  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17 #undef DEBUG
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/clk.h>
  22 #include <linux/io.h>
  23
  24 #include "clock.h"
  25 #include "clock3xxx.h"
  26 #include "clock34xx.h"
  27 #include "sdrc.h"
  28 #include "sram.h"
  29
  30 #define CYCLES_PER_MHZ                  1000000
  31
  32 /*
  33  * CORE DPLL (DPLL3) M2 divider rate programming functions
  34  *
  35  * These call into SRAM code to do the actual CM writes, since the SDRAM
  36  * is clocked from DPLL3.
  37  */
  38
  39 /**
  40  * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
  41  * @clk: struct clk * of DPLL to set
  42  * @rate: rounded target rate
  43  *
  44  * Program the DPLL M2 divider with the rounded target rate.  Returns
  45  * -EINVAL upon error, or 0 upon success.
  46  */
  47 int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate,
  48                                         unsigned long parent_rate)
  49 {
  50         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  51         u32 new_div = 0;
  52         u32 unlock_dll = 0;
  53         u32 c;
  54         unsigned long validrate, sdrcrate, _mpurate;
  55         struct omap_sdrc_params *sdrc_cs0;
  56         struct omap_sdrc_params *sdrc_cs1;
  57         int ret;
  58         unsigned long clkrate;
  59
  60         if (!clk || !rate)
  61                 return -EINVAL;
  62
  63         validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
  64         if (validrate != rate)
  65                 return -EINVAL;
  66
  67         sdrcrate = __clk_get_rate(sdrc_ick_p);
  68         clkrate = __clk_get_rate(hw->clk);
  69         if (rate > clkrate)
  70                 sdrcrate <<= ((rate / clkrate) >> 1);
  71         else
  72                 sdrcrate >>= ((clkrate / rate) >> 1);
  73
  74         ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
  75         if (ret)
  76                 return -EINVAL;
  77
  78         if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
  79                 pr_debug("clock: will unlock SDRC DLL\n");
  80                 unlock_dll = 1;
  81         }
  82
  83         /*
  84          * XXX This only needs to be done when the CPU frequency changes
  85          */
  86         _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
  87         c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
  88         c += 1;  /* for safety */
  89         c *= SDRC_MPURATE_LOOPS;
  90         c >>= SDRC_MPURATE_SCALE;
  91         if (c == 0)
  92                 c = 1;
  93
  94         pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
  95                  clkrate, validrate);
  96         pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
  97                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
  98                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
  99         if (sdrc_cs1)
 100                 pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
 101                          sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
 102                          sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
 103
 104         if (sdrc_cs1)
 105                 omap3_configure_core_dpll(
 106                                   new_div, unlock_dll, c, rate > clkrate,
 107                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
 108                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
 109                                   sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
 110                                   sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
 111         else
 112                 omap3_configure_core_dpll(
 113                                   new_div, unlock_dll, c, rate > clkrate,
 114                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
 115                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
 116                                   0, 0, 0, 0);
 117         return 0;
 118 }
 119