| blob | 04dab2fcf862fd39705323941eeb560aa6d3ca85 |
1 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
2 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
4 /*
5 * OMAP3430 Clock Management register bits
6 *
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
17 #define OMAP3430ES2_EN_MMC3_SHIFT 30
18 #define OMAP3430_EN_MSPRO_SHIFT 23
19 #define OMAP3430_EN_HDQ_SHIFT 22
20 #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
21 #define OMAP3430ES1_EN_D2D_SHIFT 3
22 #define OMAP3430_EN_SSI_SHIFT 0
23 #define OMAP3430ES2_EN_USBTLL_SHIFT 2
24 #define OMAP3430_EN_WDT2_SHIFT 5
25 #define OMAP3430_EN_CAM_SHIFT 0
26 #define OMAP3430_EN_WDT3_SHIFT 12
27 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0)
28 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0
29 #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
30 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
31 #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
32 #define OMAP3430_ST_IVA2_SHIFT 0
33 #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
34 #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
35 #define OMAP3430_IVA2_CLK_SRC_SHIFT 19
36 #define OMAP3430_IVA2_CLK_SRC_WIDTH 3
37 #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
38 #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0)
39 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0
40 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5
41 #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
42 #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)
43 #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4)
44 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3
45 #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)
46 #define OMAP3430_ST_MPU_CLK_SHIFT 0
47 #define OMAP3430_ST_MPU_CLK_MASK (1 << 0)
48 #define OMAP3430_ST_MPU_CLK_WIDTH 1
49 #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0)
50 #define OMAP3430_MPU_CLK_SRC_SHIFT 19
51 #define OMAP3430_MPU_CLK_SRC_WIDTH 3
52 #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
53 #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0)
54 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0
55 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5
56 #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
57 #define OMAP3430_EN_MODEM_SHIFT 31
58 #define OMAP3430_EN_ICR_SHIFT 29
59 #define OMAP3430_EN_AES2_SHIFT 28
60 #define OMAP3430_EN_SHA12_SHIFT 27
61 #define OMAP3430_EN_DES2_SHIFT 26
62 #define OMAP3430ES1_EN_FAC_SHIFT 8
63 #define OMAP3430_EN_MAILBOXES_SHIFT 7
64 #define OMAP3430_EN_OMAPCTRL_SHIFT 6
65 #define OMAP3430_EN_SAD2D_SHIFT 3
66 #define OMAP3430_EN_SDRC_SHIFT 1
67 #define AM35XX_EN_IPSS_SHIFT 4
68 #define OMAP3430_EN_PKA_SHIFT 4
69 #define OMAP3430_EN_AES1_SHIFT 3
70 #define OMAP3430_EN_RNG_SHIFT 2
71 #define OMAP3430_EN_SHA11_SHIFT 1
72 #define OMAP3430_EN_DES1_SHIFT 0
73 #define OMAP3430_EN_MAD2D_SHIFT 3
74 #define OMAP3430ES2_EN_TS_SHIFT 1
75 #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0
76 #define OMAP3430_ST_AES2_SHIFT 28
77 #define OMAP3430_ST_SHA12_SHIFT 27
78 #define AM35XX_ST_UART4_SHIFT 23
79 #define OMAP3430_ST_HDQ_SHIFT 22
80 #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8
81 #define OMAP3430_ST_MAILBOXES_SHIFT 7
82 #define OMAP3430_ST_SAD2D_SHIFT 3
83 #define OMAP3430_ST_SDMA_SHIFT 2
84 #define AM35XX_ST_IPSS_SHIFT 5
85 #define OMAP3430ES2_ST_USBTLL_SHIFT 2
86 #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8)
87 #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7)
88 #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6)
89 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
90 #define OMAP3430_CLKSEL_L4_SHIFT 2
91 #define OMAP3430_CLKSEL_L4_WIDTH 2
92 #define OMAP3430_CLKSEL_L3_SHIFT 0
93 #define OMAP3430_CLKSEL_L3_WIDTH 2
94 #define OMAP3630_CLKSEL_96M_MASK (0x3 << 12)
95 #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)
96 #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)
97 #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
98 #define OMAP3430ES1_EN_3D_SHIFT 2
99 #define OMAP3430ES1_EN_2D_SHIFT 1
100 #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
101 #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1
102 #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0
103 #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
104 #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)
105 #define OMAP3430ES2_EN_USIMOCP_SHIFT 9
106 #define OMAP3430_EN_WDT1_SHIFT 4
107 #define OMAP3430_EN_32KSYNC_SHIFT 2
108 #define OMAP3430_ST_WDT2_SHIFT 5
109 #define OMAP3430_ST_32KSYNC_SHIFT 2
110 #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)
111 #define OMAP3430_CLKSEL_RM_SHIFT 1
112 #define OMAP3430_CLKSEL_RM_WIDTH 2
113 #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)
114 #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31
115 #define OMAP3430_PWRDN_CAM_SHIFT 30
116 #define OMAP3430_PWRDN_DSS1_SHIFT 29
117 #define OMAP3430_PWRDN_TV_SHIFT 28
118 #define OMAP3430_PWRDN_96M_SHIFT 27
119 #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20)
120 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19
121 #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16)
122 #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12
123 #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4)
124 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3
125 #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)
126 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)
127 #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3
128 #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)
129 #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1)
130 #define OMAP3430_ST_CORE_CLK_MASK (1 << 0)
131 #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0)
132 #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3)
133 #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)
134 #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0)
135 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
136 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5
137 #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
138 #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
139 #define OMAP3430_SOURCE_96M_SHIFT 6
140 #define OMAP3430_SOURCE_96M_WIDTH 1
141 #define OMAP3430_SOURCE_54M_SHIFT 5
142 #define OMAP3430_SOURCE_54M_WIDTH 1
143 #define OMAP3430_SOURCE_48M_MASK (1 << 3)
144 #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)
145 #define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8)
146 #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)
147 #define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21)
148 #define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24)
149 #define OMAP3430_DIV_96M_SHIFT 0
150 #define OMAP3630_DIV_96M_WIDTH 6
151 #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8)
152 #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0)
153 #define OMAP3430ES2_DIV_120M_SHIFT 0
154 #define OMAP3430ES2_DIV_120M_WIDTH 5
155 #define OMAP3430_CLKOUT2_EN_SHIFT 7
156 #define OMAP3430_CLKOUT2_DIV_SHIFT 3
157 #define OMAP3430_CLKOUT2_DIV_WIDTH 3
158 #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
159 #define OMAP3430_EN_TV_SHIFT 2
160 #define OMAP3430_EN_DSS2_SHIFT 1
161 #define OMAP3430_EN_DSS1_SHIFT 0
162 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
163 #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1
164 #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0
165 #define OMAP3430ES1_ST_DSS_SHIFT 0
166 #define OMAP3430_CLKSEL_TV_SHIFT 8
167 #define OMAP3630_CLKSEL_TV_WIDTH 6
168 #define OMAP3430_CLKSEL_DSS1_SHIFT 0
169 #define OMAP3630_CLKSEL_DSS1_WIDTH 6
170 #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
171 #define OMAP3430_EN_CSI2_SHIFT 1
172 #define OMAP3430_CLKSEL_CAM_SHIFT 0
173 #define OMAP3630_CLKSEL_CAM_WIDTH 6
174 #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
175 #define OMAP3430_ST_MCBSP4_SHIFT 2
176 #define OMAP3430_ST_MCBSP3_SHIFT 1
177 #define OMAP3430_ST_MCBSP2_SHIFT 0
178 #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7)
179 #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6)
180 #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5)
181 #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4)
182 #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3)
183 #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2)
184 #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1)
185 #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0)
186 #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
187 #define OMAP3430_DIV_DPLL4_SHIFT 24
188 #define OMAP3630_DIV_DPLL4_WIDTH 6
189 #define OMAP3430_DIV_DPLL3_SHIFT 16
190 #define OMAP3430_DIV_DPLL3_WIDTH 5
191 #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
192 #define OMAP3430_CLKSEL_TRACECLK_WIDTH 3
193 #define OMAP3430_CLKSEL_PCLK_SHIFT 8
194 #define OMAP3430_CLKSEL_PCLK_WIDTH 3
195 #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6
196 #define OMAP3430_CLKSEL_PCLKX2_WIDTH 2
197 #define OMAP3430_CLKSEL_ATCLK_SHIFT 4
198 #define OMAP3430_CLKSEL_ATCLK_WIDTH 2
199 #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2
200 #define OMAP3430_TRACE_MUX_CTRL_WIDTH 2
201 #define OMAP3430_MUX_CTRL_MASK (0x3 << 0)
202 #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
203 #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0)
204 #define OMAP3430ES2_EN_USBHOST2_SHIFT 1
205 #define OMAP3430ES2_EN_USBHOST1_SHIFT 0
206 #define OMAP3430ES2_EN_USBHOST_SHIFT 0
207 #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1
208 #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0
209 #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
210 #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
211 #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
212 #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2
213 #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3
214 #endif