arch/arm/mach-omap2/cm2xxx.h

   1 /*
   2  * OMAP2xxx Clock Management (CM) register definitions
   3  *
   4  * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2010 Nokia Corporation
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The CM hardware modules on the OMAP2/3 are quite similar to each
  13  * other.  The CM modules/instances on OMAP4 are quite different, so
  14  * they are handled in a separate file.
  15  */
  16 #ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_H
  17 #define __ARCH_ASM_MACH_OMAP2_CM2XXX_H
  18
  19 #include "prcm-common.h"
  20 #include "cm2xxx_3xxx.h"
  21
  22 #define OMAP2420_CM_REGADDR(module, reg)                                \
  23                         OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
  24 #define OMAP2430_CM_REGADDR(module, reg)                                \
  25                         OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
  26
  27 /*
  28  * Module specific CM register offsets from CM_BASE + domain offset
  29  * Use cm_{read,write}_mod_reg() with these registers.
  30  * These register offsets generally appear in more than one PRCM submodule.
  31  */
  32
  33 /* OMAP2-specific register offsets */
  34
  35 #define OMAP24XX_CM_FCLKEN2                             0x0004
  36 #define OMAP24XX_CM_ICLKEN4                             0x001c
  37 #define OMAP24XX_CM_AUTOIDLE4                           0x003c
  38 #define OMAP24XX_CM_IDLEST4                             0x002c
  39
  40 /* CM_IDLEST bit field values to indicate deasserted IdleReq */
  41
  42 #define OMAP24XX_CM_IDLEST_VAL                          0
  43
  44
  45 /* Clock management domain register get/set */
  46
  47 #ifndef __ASSEMBLER__
  48
  49 extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
  50 extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
  51
  52 extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
  53 extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
  54
  55 extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
  56 extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
  57 extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
  58 extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
  59
  60 extern bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
  61 extern int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
  62                                          u8 idlest_shift);
  63 extern int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
  64                                         s16 *prcm_inst, u8 *idlest_reg_id);
  65 extern int omap2xxx_cm_fclks_active(void);
  66 extern int omap2xxx_cm_mpu_retention_allowed(void);
  67 extern u32 omap2xxx_cm_get_core_clk_src(void);
  68 extern u32 omap2xxx_cm_get_core_pll_config(void);
  69 extern u32 omap2xxx_cm_get_pll_config(void);
  70 extern u32 omap2xxx_cm_get_pll_status(void);
  71 extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
  72                                          u32 mdm);
  73
  74 extern int __init omap2xxx_cm_init(void);
  75
  76 #endif
  77
  78 #endif