Merge tag 'locks-v3.16-2' of git://git.samba.org/jlayton/linux
[linux/fpc-iii.git] / arch / arm / mach-omap2 / io.c
blob8f559450c876292f7b1a381cc2b15ba193389612
1 /*
2 * linux/arch/arm/mach-omap2/io.c
4 * OMAP2 I/O mapping code
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/clk.h>
25 #include <asm/tlb.h>
26 #include <asm/mach/map.h>
28 #include <linux/omap-dma.h>
30 #include "omap_hwmod.h"
31 #include "soc.h"
32 #include "iomap.h"
33 #include "voltage.h"
34 #include "powerdomain.h"
35 #include "clockdomain.h"
36 #include "common.h"
37 #include "clock.h"
38 #include "clock2xxx.h"
39 #include "clock3xxx.h"
40 #include "clock44xx.h"
41 #include "omap-pm.h"
42 #include "sdrc.h"
43 #include "control.h"
44 #include "serial.h"
45 #include "sram.h"
46 #include "cm2xxx.h"
47 #include "cm3xxx.h"
48 #include "prm.h"
49 #include "cm.h"
50 #include "prcm_mpu44xx.h"
51 #include "prminst44xx.h"
52 #include "cminst44xx.h"
53 #include "prm2xxx.h"
54 #include "prm3xxx.h"
55 #include "prm44xx.h"
58 * omap_clk_soc_init: points to a function that does the SoC-specific
59 * clock initializations
61 static int (*omap_clk_soc_init)(void);
64 * The machine specific code may provide the extra mapping besides the
65 * default mapping provided here.
68 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
69 static struct map_desc omap24xx_io_desc[] __initdata = {
71 .virtual = L3_24XX_VIRT,
72 .pfn = __phys_to_pfn(L3_24XX_PHYS),
73 .length = L3_24XX_SIZE,
74 .type = MT_DEVICE
77 .virtual = L4_24XX_VIRT,
78 .pfn = __phys_to_pfn(L4_24XX_PHYS),
79 .length = L4_24XX_SIZE,
80 .type = MT_DEVICE
84 #ifdef CONFIG_SOC_OMAP2420
85 static struct map_desc omap242x_io_desc[] __initdata = {
87 .virtual = DSP_MEM_2420_VIRT,
88 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
89 .length = DSP_MEM_2420_SIZE,
90 .type = MT_DEVICE
93 .virtual = DSP_IPI_2420_VIRT,
94 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
95 .length = DSP_IPI_2420_SIZE,
96 .type = MT_DEVICE
99 .virtual = DSP_MMU_2420_VIRT,
100 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
101 .length = DSP_MMU_2420_SIZE,
102 .type = MT_DEVICE
106 #endif
108 #ifdef CONFIG_SOC_OMAP2430
109 static struct map_desc omap243x_io_desc[] __initdata = {
111 .virtual = L4_WK_243X_VIRT,
112 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
113 .length = L4_WK_243X_SIZE,
114 .type = MT_DEVICE
117 .virtual = OMAP243X_GPMC_VIRT,
118 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
119 .length = OMAP243X_GPMC_SIZE,
120 .type = MT_DEVICE
123 .virtual = OMAP243X_SDRC_VIRT,
124 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
125 .length = OMAP243X_SDRC_SIZE,
126 .type = MT_DEVICE
129 .virtual = OMAP243X_SMS_VIRT,
130 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
131 .length = OMAP243X_SMS_SIZE,
132 .type = MT_DEVICE
135 #endif
136 #endif
138 #ifdef CONFIG_ARCH_OMAP3
139 static struct map_desc omap34xx_io_desc[] __initdata = {
141 .virtual = L3_34XX_VIRT,
142 .pfn = __phys_to_pfn(L3_34XX_PHYS),
143 .length = L3_34XX_SIZE,
144 .type = MT_DEVICE
147 .virtual = L4_34XX_VIRT,
148 .pfn = __phys_to_pfn(L4_34XX_PHYS),
149 .length = L4_34XX_SIZE,
150 .type = MT_DEVICE
153 .virtual = OMAP34XX_GPMC_VIRT,
154 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
155 .length = OMAP34XX_GPMC_SIZE,
156 .type = MT_DEVICE
159 .virtual = OMAP343X_SMS_VIRT,
160 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
161 .length = OMAP343X_SMS_SIZE,
162 .type = MT_DEVICE
165 .virtual = OMAP343X_SDRC_VIRT,
166 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
167 .length = OMAP343X_SDRC_SIZE,
168 .type = MT_DEVICE
171 .virtual = L4_PER_34XX_VIRT,
172 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
173 .length = L4_PER_34XX_SIZE,
174 .type = MT_DEVICE
177 .virtual = L4_EMU_34XX_VIRT,
178 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
179 .length = L4_EMU_34XX_SIZE,
180 .type = MT_DEVICE
183 #endif
185 #ifdef CONFIG_SOC_TI81XX
186 static struct map_desc omapti81xx_io_desc[] __initdata = {
188 .virtual = L4_34XX_VIRT,
189 .pfn = __phys_to_pfn(L4_34XX_PHYS),
190 .length = L4_34XX_SIZE,
191 .type = MT_DEVICE
194 #endif
196 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
197 static struct map_desc omapam33xx_io_desc[] __initdata = {
199 .virtual = L4_34XX_VIRT,
200 .pfn = __phys_to_pfn(L4_34XX_PHYS),
201 .length = L4_34XX_SIZE,
202 .type = MT_DEVICE
205 .virtual = L4_WK_AM33XX_VIRT,
206 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
207 .length = L4_WK_AM33XX_SIZE,
208 .type = MT_DEVICE
211 #endif
213 #ifdef CONFIG_ARCH_OMAP4
214 static struct map_desc omap44xx_io_desc[] __initdata = {
216 .virtual = L3_44XX_VIRT,
217 .pfn = __phys_to_pfn(L3_44XX_PHYS),
218 .length = L3_44XX_SIZE,
219 .type = MT_DEVICE,
222 .virtual = L4_44XX_VIRT,
223 .pfn = __phys_to_pfn(L4_44XX_PHYS),
224 .length = L4_44XX_SIZE,
225 .type = MT_DEVICE,
228 .virtual = L4_PER_44XX_VIRT,
229 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
230 .length = L4_PER_44XX_SIZE,
231 .type = MT_DEVICE,
233 #ifdef CONFIG_OMAP4_ERRATA_I688
235 .virtual = OMAP4_SRAM_VA,
236 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
237 .length = PAGE_SIZE,
238 .type = MT_MEMORY_RW_SO,
240 #endif
243 #endif
245 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
246 static struct map_desc omap54xx_io_desc[] __initdata = {
248 .virtual = L3_54XX_VIRT,
249 .pfn = __phys_to_pfn(L3_54XX_PHYS),
250 .length = L3_54XX_SIZE,
251 .type = MT_DEVICE,
254 .virtual = L4_54XX_VIRT,
255 .pfn = __phys_to_pfn(L4_54XX_PHYS),
256 .length = L4_54XX_SIZE,
257 .type = MT_DEVICE,
260 .virtual = L4_WK_54XX_VIRT,
261 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
262 .length = L4_WK_54XX_SIZE,
263 .type = MT_DEVICE,
266 .virtual = L4_PER_54XX_VIRT,
267 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
268 .length = L4_PER_54XX_SIZE,
269 .type = MT_DEVICE,
271 #ifdef CONFIG_OMAP4_ERRATA_I688
273 .virtual = OMAP4_SRAM_VA,
274 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
275 .length = PAGE_SIZE,
276 .type = MT_MEMORY_RW_SO,
278 #endif
280 #endif
282 #ifdef CONFIG_SOC_OMAP2420
283 void __init omap242x_map_io(void)
285 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
286 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
288 #endif
290 #ifdef CONFIG_SOC_OMAP2430
291 void __init omap243x_map_io(void)
293 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
294 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
296 #endif
298 #ifdef CONFIG_ARCH_OMAP3
299 void __init omap3_map_io(void)
301 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
303 #endif
305 #ifdef CONFIG_SOC_TI81XX
306 void __init ti81xx_map_io(void)
308 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
310 #endif
312 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
313 void __init am33xx_map_io(void)
315 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
317 #endif
319 #ifdef CONFIG_ARCH_OMAP4
320 void __init omap4_map_io(void)
322 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
323 omap_barriers_init();
325 #endif
327 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
328 void __init omap5_map_io(void)
330 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
331 omap_barriers_init();
333 #endif
335 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
337 * Sets the CORE DPLL3 M2 divider to the same value that it's at
338 * currently. This has the effect of setting the SDRC SDRAM AC timing
339 * registers to the values currently defined by the kernel. Currently
340 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
341 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
342 * or passes along the return value of clk_set_rate().
344 static int __init _omap2_init_reprogram_sdrc(void)
346 struct clk *dpll3_m2_ck;
347 int v = -EINVAL;
348 long rate;
350 if (!cpu_is_omap34xx())
351 return 0;
353 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
354 if (IS_ERR(dpll3_m2_ck))
355 return -EINVAL;
357 rate = clk_get_rate(dpll3_m2_ck);
358 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
359 v = clk_set_rate(dpll3_m2_ck, rate);
360 if (v)
361 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
363 clk_put(dpll3_m2_ck);
365 return v;
368 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
370 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
373 static void __init omap_hwmod_init_postsetup(void)
375 u8 postsetup_state;
377 /* Set the default postsetup state for all hwmods */
378 #ifdef CONFIG_PM_RUNTIME
379 postsetup_state = _HWMOD_STATE_IDLE;
380 #else
381 postsetup_state = _HWMOD_STATE_ENABLED;
382 #endif
383 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
385 omap_pm_if_early_init();
388 static void __init __maybe_unused omap_common_late_init(void)
390 omap_mux_late_init();
391 omap2_common_pm_late_init();
392 omap_soc_device_init();
395 #ifdef CONFIG_SOC_OMAP2420
396 void __init omap2420_init_early(void)
398 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
399 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
400 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
401 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
402 NULL);
403 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
404 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
405 omap2xxx_check_revision();
406 omap2xxx_prm_init();
407 omap2xxx_cm_init();
408 omap2xxx_voltagedomains_init();
409 omap242x_powerdomains_init();
410 omap242x_clockdomains_init();
411 omap2420_hwmod_init();
412 omap_hwmod_init_postsetup();
413 omap_clk_soc_init = omap2420_clk_init;
416 void __init omap2420_init_late(void)
418 omap_common_late_init();
419 omap2_pm_init();
420 omap2_clk_enable_autoidle_all();
422 #endif
424 #ifdef CONFIG_SOC_OMAP2430
425 void __init omap2430_init_early(void)
427 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
428 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
429 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
430 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
431 NULL);
432 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
433 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
434 omap2xxx_check_revision();
435 omap2xxx_prm_init();
436 omap2xxx_cm_init();
437 omap2xxx_voltagedomains_init();
438 omap243x_powerdomains_init();
439 omap243x_clockdomains_init();
440 omap2430_hwmod_init();
441 omap_hwmod_init_postsetup();
442 omap_clk_soc_init = omap2430_clk_init;
445 void __init omap2430_init_late(void)
447 omap_common_late_init();
448 omap2_pm_init();
449 omap2_clk_enable_autoidle_all();
451 #endif
454 * Currently only board-omap3beagle.c should call this because of the
455 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
457 #ifdef CONFIG_ARCH_OMAP3
458 void __init omap3_init_early(void)
460 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
461 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
462 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
463 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
464 NULL);
465 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
466 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
467 omap3xxx_check_revision();
468 omap3xxx_check_features();
469 omap3xxx_prm_init();
470 omap3xxx_cm_init();
471 omap3xxx_voltagedomains_init();
472 omap3xxx_powerdomains_init();
473 omap3xxx_clockdomains_init();
474 omap3xxx_hwmod_init();
475 omap_hwmod_init_postsetup();
476 omap_clk_soc_init = omap3xxx_clk_init;
479 void __init omap3430_init_early(void)
481 omap3_init_early();
482 if (of_have_populated_dt())
483 omap_clk_soc_init = omap3430_dt_clk_init;
486 void __init omap35xx_init_early(void)
488 omap3_init_early();
489 if (of_have_populated_dt())
490 omap_clk_soc_init = omap3430_dt_clk_init;
493 void __init omap3630_init_early(void)
495 omap3_init_early();
496 if (of_have_populated_dt())
497 omap_clk_soc_init = omap3630_dt_clk_init;
500 void __init am35xx_init_early(void)
502 omap3_init_early();
503 if (of_have_populated_dt())
504 omap_clk_soc_init = am35xx_dt_clk_init;
507 void __init ti81xx_init_early(void)
509 omap2_set_globals_tap(OMAP343X_CLASS,
510 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
511 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
512 NULL);
513 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
514 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
515 omap3xxx_check_revision();
516 ti81xx_check_features();
517 omap3xxx_voltagedomains_init();
518 omap3xxx_powerdomains_init();
519 omap3xxx_clockdomains_init();
520 omap3xxx_hwmod_init();
521 omap_hwmod_init_postsetup();
522 if (of_have_populated_dt())
523 omap_clk_soc_init = ti81xx_dt_clk_init;
524 else
525 omap_clk_soc_init = omap3xxx_clk_init;
528 void __init omap3_init_late(void)
530 omap_common_late_init();
531 omap3_pm_init();
532 omap2_clk_enable_autoidle_all();
535 void __init omap3430_init_late(void)
537 omap_common_late_init();
538 omap3_pm_init();
539 omap2_clk_enable_autoidle_all();
542 void __init omap35xx_init_late(void)
544 omap_common_late_init();
545 omap3_pm_init();
546 omap2_clk_enable_autoidle_all();
549 void __init omap3630_init_late(void)
551 omap_common_late_init();
552 omap3_pm_init();
553 omap2_clk_enable_autoidle_all();
556 void __init am35xx_init_late(void)
558 omap_common_late_init();
559 omap3_pm_init();
560 omap2_clk_enable_autoidle_all();
563 void __init ti81xx_init_late(void)
565 omap_common_late_init();
566 omap3_pm_init();
567 omap2_clk_enable_autoidle_all();
569 #endif
571 #ifdef CONFIG_SOC_AM33XX
572 void __init am33xx_init_early(void)
574 omap2_set_globals_tap(AM335X_CLASS,
575 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
576 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
577 NULL);
578 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
579 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
580 omap3xxx_check_revision();
581 am33xx_check_features();
582 am33xx_powerdomains_init();
583 am33xx_clockdomains_init();
584 am33xx_hwmod_init();
585 omap_hwmod_init_postsetup();
586 omap_clk_soc_init = am33xx_dt_clk_init;
589 void __init am33xx_init_late(void)
591 omap_common_late_init();
593 #endif
595 #ifdef CONFIG_SOC_AM43XX
596 void __init am43xx_init_early(void)
598 omap2_set_globals_tap(AM335X_CLASS,
599 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
600 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
601 NULL);
602 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
603 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
604 omap_prm_base_init();
605 omap_cm_base_init();
606 omap3xxx_check_revision();
607 am33xx_check_features();
608 am43xx_powerdomains_init();
609 am43xx_clockdomains_init();
610 am43xx_hwmod_init();
611 omap_hwmod_init_postsetup();
612 omap_l2_cache_init();
613 omap_clk_soc_init = am43xx_dt_clk_init;
616 void __init am43xx_init_late(void)
618 omap_common_late_init();
620 #endif
622 #ifdef CONFIG_ARCH_OMAP4
623 void __init omap4430_init_early(void)
625 omap2_set_globals_tap(OMAP443X_CLASS,
626 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
627 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
628 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
629 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
630 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
631 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
632 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
633 omap_prm_base_init();
634 omap_cm_base_init();
635 omap4xxx_check_revision();
636 omap4xxx_check_features();
637 omap4_pm_init_early();
638 omap44xx_prm_init();
639 omap44xx_voltagedomains_init();
640 omap44xx_powerdomains_init();
641 omap44xx_clockdomains_init();
642 omap44xx_hwmod_init();
643 omap_hwmod_init_postsetup();
644 omap_l2_cache_init();
645 omap_clk_soc_init = omap4xxx_dt_clk_init;
648 void __init omap4430_init_late(void)
650 omap_common_late_init();
651 omap4_pm_init();
652 omap2_clk_enable_autoidle_all();
654 #endif
656 #ifdef CONFIG_SOC_OMAP5
657 void __init omap5_init_early(void)
659 omap2_set_globals_tap(OMAP54XX_CLASS,
660 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
661 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
662 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
663 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
664 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
665 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
666 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
667 omap_prm_base_init();
668 omap_cm_base_init();
669 omap44xx_prm_init();
670 omap5xxx_check_revision();
671 omap54xx_voltagedomains_init();
672 omap54xx_powerdomains_init();
673 omap54xx_clockdomains_init();
674 omap54xx_hwmod_init();
675 omap_hwmod_init_postsetup();
676 omap_clk_soc_init = omap5xxx_dt_clk_init;
679 void __init omap5_init_late(void)
681 omap_common_late_init();
683 #endif
685 #ifdef CONFIG_SOC_DRA7XX
686 void __init dra7xx_init_early(void)
688 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
689 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
690 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
691 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
692 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
693 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
694 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
695 omap_prm_base_init();
696 omap_cm_base_init();
697 omap44xx_prm_init();
698 dra7xxx_check_revision();
699 dra7xx_powerdomains_init();
700 dra7xx_clockdomains_init();
701 dra7xx_hwmod_init();
702 omap_hwmod_init_postsetup();
703 omap_clk_soc_init = dra7xx_dt_clk_init;
706 void __init dra7xx_init_late(void)
708 omap_common_late_init();
710 #endif
713 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
714 struct omap_sdrc_params *sdrc_cs1)
716 omap_sram_init();
718 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
719 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
720 _omap2_init_reprogram_sdrc();
724 int __init omap_clk_init(void)
726 int ret = 0;
728 if (!omap_clk_soc_init)
729 return 0;
731 ret = of_prcm_init();
732 if (!ret)
733 ret = omap_clk_soc_init();
735 return ret;