2 * linux/arch/arm/mach-omap2/irq.c
4 * Interrupt handler for OMAP2 boards.
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
19 #include <asm/exception.h>
20 #include <asm/mach/irq.h>
21 #include <linux/irqdomain.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
30 /* selected INTC register offsets */
32 #define INTC_REVISION 0x0000
33 #define INTC_SYSCONFIG 0x0010
34 #define INTC_SYSSTATUS 0x0014
35 #define INTC_SIR 0x0040
36 #define INTC_CONTROL 0x0048
37 #define INTC_PROTECTION 0x004C
38 #define INTC_IDLE 0x0050
39 #define INTC_THRESHOLD 0x0068
40 #define INTC_MIR0 0x0084
41 #define INTC_MIR_CLEAR0 0x0088
42 #define INTC_MIR_SET0 0x008c
43 #define INTC_PENDING_IRQ0 0x0098
44 /* Number of IRQ state bits in each MIR register */
45 #define IRQ_BITS_PER_REG 32
47 #define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
48 #define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
49 #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
50 #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
51 #define INTCPS_NR_MIR_REGS 3
52 #define INTCPS_NR_IRQS 96
55 * OMAP2 has a number of different interrupt controllers, each interrupt
56 * controller is identified as its own "bank". Register definitions are
57 * fairly consistent for each bank, but not all registers are implemented
58 * for each bank.. when in doubt, consult the TRM.
60 static struct omap_irq_bank
{
61 void __iomem
*base_reg
;
63 } __attribute__ ((aligned(4))) irq_banks
[] = {
70 static struct irq_domain
*domain
;
72 /* Structure to save interrupt controller context */
73 struct omap3_intc_regs
{
78 u32 ilr
[INTCPS_NR_IRQS
];
79 u32 mir
[INTCPS_NR_MIR_REGS
];
82 /* INTC bank register get/set */
84 static void intc_bank_write_reg(u32 val
, struct omap_irq_bank
*bank
, u16 reg
)
86 writel_relaxed(val
, bank
->base_reg
+ reg
);
89 static u32
intc_bank_read_reg(struct omap_irq_bank
*bank
, u16 reg
)
91 return readl_relaxed(bank
->base_reg
+ reg
);
94 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
95 static void omap_ack_irq(struct irq_data
*d
)
97 intc_bank_write_reg(0x1, &irq_banks
[0], INTC_CONTROL
);
100 static void omap_mask_ack_irq(struct irq_data
*d
)
102 irq_gc_mask_disable_reg(d
);
106 static void __init
omap_irq_bank_init_one(struct omap_irq_bank
*bank
)
110 tmp
= intc_bank_read_reg(bank
, INTC_REVISION
) & 0xff;
111 pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
112 bank
->base_reg
, tmp
>> 4, tmp
& 0xf, bank
->nr_irqs
);
114 tmp
= intc_bank_read_reg(bank
, INTC_SYSCONFIG
);
115 tmp
|= 1 << 1; /* soft reset */
116 intc_bank_write_reg(tmp
, bank
, INTC_SYSCONFIG
);
118 while (!(intc_bank_read_reg(bank
, INTC_SYSSTATUS
) & 0x1))
119 /* Wait for reset to complete */;
121 /* Enable autoidle */
122 intc_bank_write_reg(1 << 0, bank
, INTC_SYSCONFIG
);
125 int omap_irq_pending(void)
129 for (i
= 0; i
< ARRAY_SIZE(irq_banks
); i
++) {
130 struct omap_irq_bank
*bank
= irq_banks
+ i
;
133 for (irq
= 0; irq
< bank
->nr_irqs
; irq
+= 32)
134 if (intc_bank_read_reg(bank
, INTC_PENDING_IRQ0
+
142 omap_alloc_gc(void __iomem
*base
, unsigned int irq_start
, unsigned int num
)
144 struct irq_chip_generic
*gc
;
145 struct irq_chip_type
*ct
;
147 gc
= irq_alloc_generic_chip("INTC", 1, irq_start
, base
,
150 ct
->chip
.irq_ack
= omap_mask_ack_irq
;
151 ct
->chip
.irq_mask
= irq_gc_mask_disable_reg
;
152 ct
->chip
.irq_unmask
= irq_gc_unmask_enable_reg
;
153 ct
->chip
.flags
|= IRQCHIP_SKIP_SET_WAKE
;
155 ct
->regs
.enable
= INTC_MIR_CLEAR0
;
156 ct
->regs
.disable
= INTC_MIR_SET0
;
157 irq_setup_generic_chip(gc
, IRQ_MSK(num
), IRQ_GC_INIT_MASK_CACHE
,
158 IRQ_NOREQUEST
| IRQ_NOPROBE
, 0);
161 static void __init
omap_init_irq(u32 base
, int nr_irqs
,
162 struct device_node
*node
)
164 void __iomem
*omap_irq_base
;
165 unsigned long nr_of_irqs
= 0;
166 unsigned int nr_banks
= 0;
169 omap_irq_base
= ioremap(base
, SZ_4K
);
170 if (WARN_ON(!omap_irq_base
))
173 irq_base
= irq_alloc_descs(-1, 0, nr_irqs
, 0);
175 pr_warn("Couldn't allocate IRQ numbers\n");
179 domain
= irq_domain_add_legacy(node
, nr_irqs
, irq_base
, 0,
180 &irq_domain_simple_ops
, NULL
);
182 for (i
= 0; i
< ARRAY_SIZE(irq_banks
); i
++) {
183 struct omap_irq_bank
*bank
= irq_banks
+ i
;
185 bank
->nr_irqs
= nr_irqs
;
187 /* Static mapping, never released */
188 bank
->base_reg
= ioremap(base
, SZ_4K
);
189 if (!bank
->base_reg
) {
190 pr_err("Could not ioremap irq bank%i\n", i
);
194 omap_irq_bank_init_one(bank
);
196 for (j
= 0; j
< bank
->nr_irqs
; j
+= 32)
197 omap_alloc_gc(bank
->base_reg
+ j
, j
+ irq_base
, 32);
199 nr_of_irqs
+= bank
->nr_irqs
;
203 pr_info("Total of %ld interrupts on %d active controller%s\n",
204 nr_of_irqs
, nr_banks
, nr_banks
> 1 ? "s" : "");
207 void __init
omap2_init_irq(void)
209 omap_init_irq(OMAP24XX_IC_BASE
, 96, NULL
);
212 void __init
omap3_init_irq(void)
214 omap_init_irq(OMAP34XX_IC_BASE
, 96, NULL
);
217 void __init
ti81xx_init_irq(void)
219 omap_init_irq(OMAP34XX_IC_BASE
, 128, NULL
);
222 static inline void omap_intc_handle_irq(void __iomem
*base_addr
, struct pt_regs
*regs
)
228 irqnr
= readl_relaxed(base_addr
+ 0x98);
232 irqnr
= readl_relaxed(base_addr
+ 0xb8);
236 irqnr
= readl_relaxed(base_addr
+ 0xd8);
237 #if IS_ENABLED(CONFIG_SOC_TI81XX) || IS_ENABLED(CONFIG_SOC_AM33XX)
240 irqnr
= readl_relaxed(base_addr
+ 0xf8);
247 irqnr
= readl_relaxed(base_addr
+ INTCPS_SIR_IRQ_OFFSET
);
248 irqnr
&= ACTIVEIRQ_MASK
;
251 irqnr
= irq_find_mapping(domain
, irqnr
);
252 handle_IRQ(irqnr
, regs
);
257 /* If an irq is masked or deasserted while active, we will
258 * keep ending up here with no irq handled. So remove it from
259 * the INTC with an ack.*/
264 asmlinkage
void __exception_irq_entry
omap2_intc_handle_irq(struct pt_regs
*regs
)
266 void __iomem
*base_addr
= OMAP2_IRQ_BASE
;
267 omap_intc_handle_irq(base_addr
, regs
);
270 int __init
intc_of_init(struct device_node
*node
,
271 struct device_node
*parent
)
279 if (of_address_to_resource(node
, 0, &res
)) {
280 WARN(1, "unable to get intc registers\n");
284 if (of_property_read_u32(node
, "ti,intc-size", &nr_irq
))
285 pr_warn("unable to get intc-size, default to %d\n", nr_irq
);
287 omap_init_irq(res
.start
, nr_irq
, of_node_get(node
));
292 static struct of_device_id irq_match
[] __initdata
= {
293 { .compatible
= "ti,omap2-intc", .data
= intc_of_init
, },
297 void __init
omap_intc_of_init(void)
299 of_irq_init(irq_match
);
302 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
303 static struct omap3_intc_regs intc_context
[ARRAY_SIZE(irq_banks
)];
305 void omap_intc_save_context(void)
308 for (ind
= 0; ind
< ARRAY_SIZE(irq_banks
); ind
++) {
309 struct omap_irq_bank
*bank
= irq_banks
+ ind
;
310 intc_context
[ind
].sysconfig
=
311 intc_bank_read_reg(bank
, INTC_SYSCONFIG
);
312 intc_context
[ind
].protection
=
313 intc_bank_read_reg(bank
, INTC_PROTECTION
);
314 intc_context
[ind
].idle
=
315 intc_bank_read_reg(bank
, INTC_IDLE
);
316 intc_context
[ind
].threshold
=
317 intc_bank_read_reg(bank
, INTC_THRESHOLD
);
318 for (i
= 0; i
< INTCPS_NR_IRQS
; i
++)
319 intc_context
[ind
].ilr
[i
] =
320 intc_bank_read_reg(bank
, (0x100 + 0x4*i
));
321 for (i
= 0; i
< INTCPS_NR_MIR_REGS
; i
++)
322 intc_context
[ind
].mir
[i
] =
323 intc_bank_read_reg(&irq_banks
[0], INTC_MIR0
+
328 void omap_intc_restore_context(void)
332 for (ind
= 0; ind
< ARRAY_SIZE(irq_banks
); ind
++) {
333 struct omap_irq_bank
*bank
= irq_banks
+ ind
;
334 intc_bank_write_reg(intc_context
[ind
].sysconfig
,
335 bank
, INTC_SYSCONFIG
);
336 intc_bank_write_reg(intc_context
[ind
].sysconfig
,
337 bank
, INTC_SYSCONFIG
);
338 intc_bank_write_reg(intc_context
[ind
].protection
,
339 bank
, INTC_PROTECTION
);
340 intc_bank_write_reg(intc_context
[ind
].idle
,
342 intc_bank_write_reg(intc_context
[ind
].threshold
,
343 bank
, INTC_THRESHOLD
);
344 for (i
= 0; i
< INTCPS_NR_IRQS
; i
++)
345 intc_bank_write_reg(intc_context
[ind
].ilr
[i
],
346 bank
, (0x100 + 0x4*i
));
347 for (i
= 0; i
< INTCPS_NR_MIR_REGS
; i
++)
348 intc_bank_write_reg(intc_context
[ind
].mir
[i
],
349 &irq_banks
[0], INTC_MIR0
+ (0x20 * i
));
351 /* MIRs are saved and restore with other PRCM registers */
354 void omap3_intc_suspend(void)
356 /* A pending interrupt would prevent OMAP from entering suspend */
360 void omap3_intc_prepare_idle(void)
363 * Disable autoidle as it can stall interrupt controller,
364 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
366 intc_bank_write_reg(0, &irq_banks
[0], INTC_SYSCONFIG
);
369 void omap3_intc_resume_idle(void)
371 /* Re-enable autoidle */
372 intc_bank_write_reg(1, &irq_banks
[0], INTC_SYSCONFIG
);
375 asmlinkage
void __exception_irq_entry
omap3_intc_handle_irq(struct pt_regs
*regs
)
377 void __iomem
*base_addr
= OMAP3_IRQ_BASE
;
378 omap_intc_handle_irq(base_addr
, regs
);
380 #endif /* CONFIG_ARCH_OMAP3 */