arch/arm/mach-omap2/omap_hwmod_43xx_data.c

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated
   3  *
   4  * Hwmod present only in AM43x and those that differ other than register
   5  * offsets as compared to AM335x.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/platform_data/gpio-omap.h>
  18 #include <linux/platform_data/spi-omap2-mcspi.h>
  19 #include "omap_hwmod.h"
  20 #include "omap_hwmod_33xx_43xx_common_data.h"
  21 #include "prcm43xx.h"
  22
  23 /* IP blocks */
  24 static struct omap_hwmod am43xx_l4_hs_hwmod = {
  25         .name           = "l4_hs",
  26         .class          = &am33xx_l4_hwmod_class,
  27         .clkdm_name     = "l3_clkdm",
  28         .flags          = HWMOD_INIT_NO_IDLE,
  29         .main_clk       = "l4hs_gclk",
  30         .prcm           = {
  31                 .omap4  = {
  32                         .clkctrl_offs   = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
  33                         .modulemode     = MODULEMODE_SWCTRL,
  34                 },
  35         },
  36 };
  37
  38 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
  39         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
  40 };
  41
  42 static struct omap_hwmod am43xx_wkup_m3_hwmod = {
  43         .name           = "wkup_m3",
  44         .class          = &am33xx_wkup_m3_hwmod_class,
  45         .clkdm_name     = "l4_wkup_aon_clkdm",
  46         /* Keep hardreset asserted */
  47         .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
  48         .main_clk       = "sys_clkin_ck",
  49         .prcm           = {
  50                 .omap4  = {
  51                         .clkctrl_offs   = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
  52                         .rstctrl_offs   = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
  53                         .rstst_offs     = AM43XX_RM_WKUP_RSTST_OFFSET,
  54                         .modulemode     = MODULEMODE_SWCTRL,
  55                 },
  56         },
  57         .rst_lines      = am33xx_wkup_m3_resets,
  58         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
  59 };
  60
  61 static struct omap_hwmod am43xx_control_hwmod = {
  62         .name           = "control",
  63         .class          = &am33xx_control_hwmod_class,
  64         .clkdm_name     = "l4_wkup_clkdm",
  65         .flags          = HWMOD_INIT_NO_IDLE,
  66         .main_clk       = "sys_clkin_ck",
  67         .prcm           = {
  68                 .omap4  = {
  69                         .clkctrl_offs   = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
  70                         .modulemode     = MODULEMODE_SWCTRL,
  71                 },
  72         },
  73 };
  74
  75 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
  76         { .role = "dbclk", .clk = "gpio0_dbclk" },
  77 };
  78
  79 static struct omap_hwmod am43xx_gpio0_hwmod = {
  80         .name           = "gpio1",
  81         .class          = &am33xx_gpio_hwmod_class,
  82         .clkdm_name     = "l4_wkup_clkdm",
  83         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  84         .main_clk       = "sys_clkin_ck",
  85         .prcm           = {
  86                 .omap4  = {
  87                         .clkctrl_offs   = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
  88                         .modulemode     = MODULEMODE_SWCTRL,
  89                 },
  90         },
  91         .opt_clks       = gpio0_opt_clks,
  92         .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
  93         .dev_attr       = &gpio_dev_attr,
  94 };
  95
  96 static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
  97         .rev_offs       = 0x0,
  98         .sysc_offs      = 0x4,
  99         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 100         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 101         .sysc_fields    = &omap_hwmod_sysc_type1,
 102 };
 103
 104 static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
 105         .name   = "synctimer",
 106         .sysc   = &am43xx_synctimer_sysc,
 107 };
 108
 109 static struct omap_hwmod am43xx_synctimer_hwmod = {
 110         .name           = "counter_32k",
 111         .class          = &am43xx_synctimer_hwmod_class,
 112         .clkdm_name     = "l4_wkup_aon_clkdm",
 113         .flags          = HWMOD_SWSUP_SIDLE,
 114         .main_clk       = "synctimer_32kclk",
 115         .prcm = {
 116                 .omap4 = {
 117                         .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 118                         .modulemode   = MODULEMODE_SWCTRL,
 119                 },
 120         },
 121 };
 122
 123 static struct omap_hwmod am43xx_timer8_hwmod = {
 124         .name           = "timer8",
 125         .class          = &am33xx_timer_hwmod_class,
 126         .clkdm_name     = "l4ls_clkdm",
 127         .main_clk       = "timer8_fck",
 128         .prcm           = {
 129                 .omap4  = {
 130                         .clkctrl_offs   = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
 131                         .modulemode     = MODULEMODE_SWCTRL,
 132                 },
 133         },
 134 };
 135
 136 static struct omap_hwmod am43xx_timer9_hwmod = {
 137         .name           = "timer9",
 138         .class          = &am33xx_timer_hwmod_class,
 139         .clkdm_name     = "l4ls_clkdm",
 140         .main_clk       = "timer9_fck",
 141         .prcm           = {
 142                 .omap4  = {
 143                         .clkctrl_offs   = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
 144                         .modulemode     = MODULEMODE_SWCTRL,
 145                 },
 146         },
 147 };
 148
 149 static struct omap_hwmod am43xx_timer10_hwmod = {
 150         .name           = "timer10",
 151         .class          = &am33xx_timer_hwmod_class,
 152         .clkdm_name     = "l4ls_clkdm",
 153         .main_clk       = "timer10_fck",
 154         .prcm           = {
 155                 .omap4  = {
 156                         .clkctrl_offs   = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
 157                         .modulemode     = MODULEMODE_SWCTRL,
 158                 },
 159         },
 160 };
 161
 162 static struct omap_hwmod am43xx_timer11_hwmod = {
 163         .name           = "timer11",
 164         .class          = &am33xx_timer_hwmod_class,
 165         .clkdm_name     = "l4ls_clkdm",
 166         .main_clk       = "timer11_fck",
 167         .prcm           = {
 168                 .omap4  = {
 169                         .clkctrl_offs   = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
 170                         .modulemode     = MODULEMODE_SWCTRL,
 171                 },
 172         },
 173 };
 174
 175 static struct omap_hwmod am43xx_epwmss3_hwmod = {
 176         .name           = "epwmss3",
 177         .class          = &am33xx_epwmss_hwmod_class,
 178         .clkdm_name     = "l4ls_clkdm",
 179         .main_clk       = "l4ls_gclk",
 180         .prcm           = {
 181                 .omap4  = {
 182                         .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
 183                         .modulemode   = MODULEMODE_SWCTRL,
 184                 },
 185         },
 186 };
 187
 188 static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
 189         .name           = "ehrpwm3",
 190         .class          = &am33xx_ehrpwm_hwmod_class,
 191         .clkdm_name     = "l4ls_clkdm",
 192         .main_clk       = "l4ls_gclk",
 193 };
 194
 195 static struct omap_hwmod am43xx_epwmss4_hwmod = {
 196         .name           = "epwmss4",
 197         .class          = &am33xx_epwmss_hwmod_class,
 198         .clkdm_name     = "l4ls_clkdm",
 199         .main_clk       = "l4ls_gclk",
 200         .prcm           = {
 201                 .omap4  = {
 202                         .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
 203                         .modulemode   = MODULEMODE_SWCTRL,
 204                 },
 205         },
 206 };
 207
 208 static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
 209         .name           = "ehrpwm4",
 210         .class          = &am33xx_ehrpwm_hwmod_class,
 211         .clkdm_name     = "l4ls_clkdm",
 212         .main_clk       = "l4ls_gclk",
 213 };
 214
 215 static struct omap_hwmod am43xx_epwmss5_hwmod = {
 216         .name           = "epwmss5",
 217         .class          = &am33xx_epwmss_hwmod_class,
 218         .clkdm_name     = "l4ls_clkdm",
 219         .main_clk       = "l4ls_gclk",
 220         .prcm           = {
 221                 .omap4  = {
 222                         .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
 223                         .modulemode   = MODULEMODE_SWCTRL,
 224                 },
 225         },
 226 };
 227
 228 static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
 229         .name           = "ehrpwm5",
 230         .class          = &am33xx_ehrpwm_hwmod_class,
 231         .clkdm_name     = "l4ls_clkdm",
 232         .main_clk       = "l4ls_gclk",
 233 };
 234
 235 static struct omap_hwmod am43xx_spi2_hwmod = {
 236         .name           = "spi2",
 237         .class          = &am33xx_spi_hwmod_class,
 238         .clkdm_name     = "l4ls_clkdm",
 239         .main_clk       = "dpll_per_m2_div4_ck",
 240         .prcm           = {
 241                 .omap4  = {
 242                         .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
 243                         .modulemode   = MODULEMODE_SWCTRL,
 244                 },
 245         },
 246         .dev_attr       = &mcspi_attrib,
 247 };
 248
 249 static struct omap_hwmod am43xx_spi3_hwmod = {
 250         .name           = "spi3",
 251         .class          = &am33xx_spi_hwmod_class,
 252         .clkdm_name     = "l4ls_clkdm",
 253         .main_clk       = "dpll_per_m2_div4_ck",
 254         .prcm           = {
 255                 .omap4  = {
 256                         .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
 257                         .modulemode   = MODULEMODE_SWCTRL,
 258                 },
 259         },
 260         .dev_attr       = &mcspi_attrib,
 261 };
 262
 263 static struct omap_hwmod am43xx_spi4_hwmod = {
 264         .name           = "spi4",
 265         .class          = &am33xx_spi_hwmod_class,
 266         .clkdm_name     = "l4ls_clkdm",
 267         .main_clk       = "dpll_per_m2_div4_ck",
 268         .prcm           = {
 269                 .omap4  = {
 270                         .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
 271                         .modulemode   = MODULEMODE_SWCTRL,
 272                 },
 273         },
 274         .dev_attr       = &mcspi_attrib,
 275 };
 276
 277 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 278         { .role = "dbclk", .clk = "gpio4_dbclk" },
 279 };
 280
 281 static struct omap_hwmod am43xx_gpio4_hwmod = {
 282         .name           = "gpio5",
 283         .class          = &am33xx_gpio_hwmod_class,
 284         .clkdm_name     = "l4ls_clkdm",
 285         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 286         .main_clk       = "l4ls_gclk",
 287         .prcm           = {
 288                 .omap4  = {
 289                         .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
 290                         .modulemode   = MODULEMODE_SWCTRL,
 291                 },
 292         },
 293         .opt_clks       = gpio4_opt_clks,
 294         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 295         .dev_attr       = &gpio_dev_attr,
 296 };
 297
 298 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 299         { .role = "dbclk", .clk = "gpio5_dbclk" },
 300 };
 301
 302 static struct omap_hwmod am43xx_gpio5_hwmod = {
 303         .name           = "gpio6",
 304         .class          = &am33xx_gpio_hwmod_class,
 305         .clkdm_name     = "l4ls_clkdm",
 306         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 307         .main_clk       = "l4ls_gclk",
 308         .prcm           = {
 309                 .omap4  = {
 310                         .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
 311                         .modulemode   = MODULEMODE_SWCTRL,
 312                 },
 313         },
 314         .opt_clks       = gpio5_opt_clks,
 315         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 316         .dev_attr       = &gpio_dev_attr,
 317 };
 318
 319 static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
 320         .name   = "ocp2scp",
 321 };
 322
 323 static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
 324         .name           = "ocp2scp0",
 325         .class          = &am43xx_ocp2scp_hwmod_class,
 326         .clkdm_name     = "l4ls_clkdm",
 327         .main_clk       = "l4ls_gclk",
 328         .prcm = {
 329                 .omap4 = {
 330                         .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
 331                         .modulemode   = MODULEMODE_SWCTRL,
 332                 },
 333         },
 334 };
 335
 336 static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
 337         .name           = "ocp2scp1",
 338         .class          = &am43xx_ocp2scp_hwmod_class,
 339         .clkdm_name     = "l4ls_clkdm",
 340         .main_clk       = "l4ls_gclk",
 341         .prcm = {
 342                 .omap4 = {
 343                         .clkctrl_offs   = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
 344                         .modulemode     = MODULEMODE_SWCTRL,
 345                 },
 346         },
 347 };
 348
 349 static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
 350         .rev_offs       = 0x0000,
 351         .sysc_offs      = 0x0010,
 352         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
 353                                 SYSC_HAS_SIDLEMODE),
 354         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 355                                 SIDLE_SMART_WKUP | MSTANDBY_FORCE |
 356                                 MSTANDBY_NO | MSTANDBY_SMART |
 357                                 MSTANDBY_SMART_WKUP),
 358         .sysc_fields    = &omap_hwmod_sysc_type2,
 359 };
 360
 361 static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
 362         .name   = "usb_otg_ss",
 363         .sysc   = &am43xx_usb_otg_ss_sysc,
 364 };
 365
 366 static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
 367         .name           = "usb_otg_ss0",
 368         .class          = &am43xx_usb_otg_ss_hwmod_class,
 369         .clkdm_name     = "l3s_clkdm",
 370         .main_clk       = "l3s_gclk",
 371         .prcm = {
 372                 .omap4 = {
 373                         .clkctrl_offs   = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
 374                         .modulemode     = MODULEMODE_SWCTRL,
 375                 },
 376         },
 377 };
 378
 379 static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
 380         .name           = "usb_otg_ss1",
 381         .class          = &am43xx_usb_otg_ss_hwmod_class,
 382         .clkdm_name     = "l3s_clkdm",
 383         .main_clk       = "l3s_gclk",
 384         .prcm = {
 385                 .omap4 = {
 386                         .clkctrl_offs   = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
 387                         .modulemode     = MODULEMODE_SWCTRL,
 388                 },
 389         },
 390 };
 391
 392 static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
 393         .sysc_offs      = 0x0010,
 394         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 395         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 396                                 SIDLE_SMART_WKUP),
 397         .sysc_fields    = &omap_hwmod_sysc_type2,
 398 };
 399
 400 static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
 401         .name   = "qspi",
 402         .sysc   = &am43xx_qspi_sysc,
 403 };
 404
 405 static struct omap_hwmod am43xx_qspi_hwmod = {
 406         .name           = "qspi",
 407         .class          = &am43xx_qspi_hwmod_class,
 408         .clkdm_name     = "l3s_clkdm",
 409         .main_clk       = "l3s_gclk",
 410         .prcm = {
 411                 .omap4 = {
 412                         .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
 413                         .modulemode   = MODULEMODE_SWCTRL,
 414                 },
 415         },
 416 };
 417
 418 /* Interfaces */
 419 static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
 420         .master         = &am33xx_l3_main_hwmod,
 421         .slave          = &am43xx_l4_hs_hwmod,
 422         .clk            = "l3s_gclk",
 423         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 424 };
 425
 426 static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
 427         .master         = &am43xx_wkup_m3_hwmod,
 428         .slave          = &am33xx_l4_wkup_hwmod,
 429         .clk            = "sys_clkin_ck",
 430         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 431 };
 432
 433 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
 434         .master         = &am33xx_l4_wkup_hwmod,
 435         .slave          = &am43xx_wkup_m3_hwmod,
 436         .clk            = "sys_clkin_ck",
 437         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 438 };
 439
 440 static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
 441         .master         = &am33xx_l3_main_hwmod,
 442         .slave          = &am33xx_pruss_hwmod,
 443         .clk            = "dpll_core_m4_ck",
 444         .user           = OCP_USER_MPU,
 445 };
 446
 447 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
 448         .master         = &am33xx_l4_wkup_hwmod,
 449         .slave          = &am33xx_smartreflex0_hwmod,
 450         .clk            = "sys_clkin_ck",
 451         .user           = OCP_USER_MPU,
 452 };
 453
 454 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
 455         .master         = &am33xx_l4_wkup_hwmod,
 456         .slave          = &am33xx_smartreflex1_hwmod,
 457         .clk            = "sys_clkin_ck",
 458         .user           = OCP_USER_MPU,
 459 };
 460
 461 static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
 462         .master         = &am33xx_l4_wkup_hwmod,
 463         .slave          = &am43xx_control_hwmod,
 464         .clk            = "sys_clkin_ck",
 465         .user           = OCP_USER_MPU,
 466 };
 467
 468 static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
 469         .master         = &am33xx_l4_wkup_hwmod,
 470         .slave          = &am33xx_i2c1_hwmod,
 471         .clk            = "sys_clkin_ck",
 472         .user           = OCP_USER_MPU,
 473 };
 474
 475 static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
 476         .master         = &am33xx_l4_wkup_hwmod,
 477         .slave          = &am43xx_gpio0_hwmod,
 478         .clk            = "sys_clkin_ck",
 479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 480 };
 481
 482 static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
 483         .master         = &am43xx_l4_hs_hwmod,
 484         .slave          = &am33xx_cpgmac0_hwmod,
 485         .clk            = "cpsw_125mhz_gclk",
 486         .user           = OCP_USER_MPU,
 487 };
 488
 489 static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
 490         .master         = &am33xx_l4_wkup_hwmod,
 491         .slave          = &am33xx_timer1_hwmod,
 492         .clk            = "sys_clkin_ck",
 493         .user           = OCP_USER_MPU,
 494 };
 495
 496 static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
 497         .master         = &am33xx_l4_wkup_hwmod,
 498         .slave          = &am33xx_uart1_hwmod,
 499         .clk            = "sys_clkin_ck",
 500         .user           = OCP_USER_MPU,
 501 };
 502
 503 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
 504         .master         = &am33xx_l4_wkup_hwmod,
 505         .slave          = &am33xx_wd_timer1_hwmod,
 506         .clk            = "sys_clkin_ck",
 507         .user           = OCP_USER_MPU,
 508 };
 509
 510 static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
 511         .master         = &am33xx_l4_wkup_hwmod,
 512         .slave          = &am43xx_synctimer_hwmod,
 513         .clk            = "sys_clkin_ck",
 514         .user           = OCP_USER_MPU,
 515 };
 516
 517 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
 518         .master         = &am33xx_l4_ls_hwmod,
 519         .slave          = &am43xx_timer8_hwmod,
 520         .clk            = "l4ls_gclk",
 521         .user           = OCP_USER_MPU,
 522 };
 523
 524 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
 525         .master         = &am33xx_l4_ls_hwmod,
 526         .slave          = &am43xx_timer9_hwmod,
 527         .clk            = "l4ls_gclk",
 528         .user           = OCP_USER_MPU,
 529 };
 530
 531 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
 532         .master         = &am33xx_l4_ls_hwmod,
 533         .slave          = &am43xx_timer10_hwmod,
 534         .clk            = "l4ls_gclk",
 535         .user           = OCP_USER_MPU,
 536 };
 537
 538 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
 539         .master         = &am33xx_l4_ls_hwmod,
 540         .slave          = &am43xx_timer11_hwmod,
 541         .clk            = "l4ls_gclk",
 542         .user           = OCP_USER_MPU,
 543 };
 544
 545 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
 546         .master         = &am33xx_l4_ls_hwmod,
 547         .slave          = &am43xx_epwmss3_hwmod,
 548         .clk            = "l4ls_gclk",
 549         .user           = OCP_USER_MPU,
 550 };
 551
 552 static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
 553         .master         = &am43xx_epwmss3_hwmod,
 554         .slave          = &am43xx_ehrpwm3_hwmod,
 555         .clk            = "l4ls_gclk",
 556         .user           = OCP_USER_MPU,
 557 };
 558
 559 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
 560         .master         = &am33xx_l4_ls_hwmod,
 561         .slave          = &am43xx_epwmss4_hwmod,
 562         .clk            = "l4ls_gclk",
 563         .user           = OCP_USER_MPU,
 564 };
 565
 566 static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
 567         .master         = &am43xx_epwmss4_hwmod,
 568         .slave          = &am43xx_ehrpwm4_hwmod,
 569         .clk            = "l4ls_gclk",
 570         .user           = OCP_USER_MPU,
 571 };
 572
 573 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
 574         .master         = &am33xx_l4_ls_hwmod,
 575         .slave          = &am43xx_epwmss5_hwmod,
 576         .clk            = "l4ls_gclk",
 577         .user           = OCP_USER_MPU,
 578 };
 579
 580 static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
 581         .master         = &am43xx_epwmss5_hwmod,
 582         .slave          = &am43xx_ehrpwm5_hwmod,
 583         .clk            = "l4ls_gclk",
 584         .user           = OCP_USER_MPU,
 585 };
 586
 587 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
 588         .master         = &am33xx_l4_ls_hwmod,
 589         .slave          = &am43xx_spi2_hwmod,
 590         .clk            = "l4ls_gclk",
 591         .user           = OCP_USER_MPU,
 592 };
 593
 594 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
 595         .master         = &am33xx_l4_ls_hwmod,
 596         .slave          = &am43xx_spi3_hwmod,
 597         .clk            = "l4ls_gclk",
 598         .user           = OCP_USER_MPU,
 599 };
 600
 601 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
 602         .master         = &am33xx_l4_ls_hwmod,
 603         .slave          = &am43xx_spi4_hwmod,
 604         .clk            = "l4ls_gclk",
 605         .user           = OCP_USER_MPU,
 606 };
 607
 608 static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
 609         .master         = &am33xx_l4_ls_hwmod,
 610         .slave          = &am43xx_gpio4_hwmod,
 611         .clk            = "l4ls_gclk",
 612         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 613 };
 614
 615 static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
 616         .master         = &am33xx_l4_ls_hwmod,
 617         .slave          = &am43xx_gpio5_hwmod,
 618         .clk            = "l4ls_gclk",
 619         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 620 };
 621
 622 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
 623         .master         = &am33xx_l4_ls_hwmod,
 624         .slave          = &am43xx_ocp2scp0_hwmod,
 625         .clk            = "l4ls_gclk",
 626         .user           = OCP_USER_MPU,
 627 };
 628
 629 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
 630         .master         = &am33xx_l4_ls_hwmod,
 631         .slave          = &am43xx_ocp2scp1_hwmod,
 632         .clk            = "l4ls_gclk",
 633         .user           = OCP_USER_MPU,
 634 };
 635
 636 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
 637         .master         = &am33xx_l3_s_hwmod,
 638         .slave          = &am43xx_usb_otg_ss0_hwmod,
 639         .clk            = "l3s_gclk",
 640         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 641 };
 642
 643 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
 644         .master         = &am33xx_l3_s_hwmod,
 645         .slave          = &am43xx_usb_otg_ss1_hwmod,
 646         .clk            = "l3s_gclk",
 647         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 648 };
 649
 650 static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
 651         .master         = &am33xx_l3_s_hwmod,
 652         .slave          = &am43xx_qspi_hwmod,
 653         .clk            = "l3s_gclk",
 654         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 655 };
 656
 657 static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
 658         &am33xx_l4_wkup__synctimer,
 659         &am43xx_l4_ls__timer8,
 660         &am43xx_l4_ls__timer9,
 661         &am43xx_l4_ls__timer10,
 662         &am43xx_l4_ls__timer11,
 663         &am43xx_l4_ls__epwmss3,
 664         &am43xx_epwmss3__ehrpwm3,
 665         &am43xx_l4_ls__epwmss4,
 666         &am43xx_epwmss4__ehrpwm4,
 667         &am43xx_l4_ls__epwmss5,
 668         &am43xx_epwmss5__ehrpwm5,
 669         &am43xx_l4_ls__mcspi2,
 670         &am43xx_l4_ls__mcspi3,
 671         &am43xx_l4_ls__mcspi4,
 672         &am43xx_l4_ls__gpio4,
 673         &am43xx_l4_ls__gpio5,
 674         &am43xx_l3_main__pruss,
 675         &am33xx_mpu__l3_main,
 676         &am33xx_mpu__prcm,
 677         &am33xx_l3_s__l4_ls,
 678         &am33xx_l3_s__l4_wkup,
 679         &am43xx_l3_main__l4_hs,
 680         &am33xx_l3_main__l3_s,
 681         &am33xx_l3_main__l3_instr,
 682         &am33xx_l3_main__gfx,
 683         &am33xx_l3_s__l3_main,
 684         &am33xx_pruss__l3_main,
 685         &am43xx_wkup_m3__l4_wkup,
 686         &am33xx_gfx__l3_main,
 687         &am43xx_l4_wkup__wkup_m3,
 688         &am43xx_l4_wkup__control,
 689         &am43xx_l4_wkup__smartreflex0,
 690         &am43xx_l4_wkup__smartreflex1,
 691         &am43xx_l4_wkup__uart1,
 692         &am43xx_l4_wkup__timer1,
 693         &am43xx_l4_wkup__i2c1,
 694         &am43xx_l4_wkup__gpio0,
 695         &am43xx_l4_wkup__wd_timer1,
 696         &am43xx_l3_s__qspi,
 697         &am33xx_l4_per__dcan0,
 698         &am33xx_l4_per__dcan1,
 699         &am33xx_l4_per__gpio1,
 700         &am33xx_l4_per__gpio2,
 701         &am33xx_l4_per__gpio3,
 702         &am33xx_l4_per__i2c2,
 703         &am33xx_l4_per__i2c3,
 704         &am33xx_l4_per__mailbox,
 705         &am33xx_l4_ls__mcasp0,
 706         &am33xx_l4_ls__mcasp1,
 707         &am33xx_l4_ls__mmc0,
 708         &am33xx_l4_ls__mmc1,
 709         &am33xx_l3_s__mmc2,
 710         &am33xx_l4_ls__timer2,
 711         &am33xx_l4_ls__timer3,
 712         &am33xx_l4_ls__timer4,
 713         &am33xx_l4_ls__timer5,
 714         &am33xx_l4_ls__timer6,
 715         &am33xx_l4_ls__timer7,
 716         &am33xx_l3_main__tpcc,
 717         &am33xx_l4_ls__uart2,
 718         &am33xx_l4_ls__uart3,
 719         &am33xx_l4_ls__uart4,
 720         &am33xx_l4_ls__uart5,
 721         &am33xx_l4_ls__uart6,
 722         &am33xx_l4_ls__spinlock,
 723         &am33xx_l4_ls__elm,
 724         &am33xx_l4_ls__epwmss0,
 725         &am33xx_epwmss0__ecap0,
 726         &am33xx_epwmss0__eqep0,
 727         &am33xx_epwmss0__ehrpwm0,
 728         &am33xx_l4_ls__epwmss1,
 729         &am33xx_epwmss1__ecap1,
 730         &am33xx_epwmss1__eqep1,
 731         &am33xx_epwmss1__ehrpwm1,
 732         &am33xx_l4_ls__epwmss2,
 733         &am33xx_epwmss2__ecap2,
 734         &am33xx_epwmss2__eqep2,
 735         &am33xx_epwmss2__ehrpwm2,
 736         &am33xx_l3_s__gpmc,
 737         &am33xx_l4_ls__mcspi0,
 738         &am33xx_l4_ls__mcspi1,
 739         &am33xx_l3_main__tptc0,
 740         &am33xx_l3_main__tptc1,
 741         &am33xx_l3_main__tptc2,
 742         &am33xx_l3_main__ocmc,
 743         &am43xx_l4_hs__cpgmac0,
 744         &am33xx_cpgmac0__mdio,
 745         &am33xx_l3_main__sha0,
 746         &am33xx_l3_main__aes0,
 747         &am43xx_l4_ls__ocp2scp0,
 748         &am43xx_l4_ls__ocp2scp1,
 749         &am43xx_l3_s__usbotgss0,
 750         &am43xx_l3_s__usbotgss1,
 751         NULL,
 752 };
 753
 754 int __init am43xx_hwmod_init(void)
 755 {
 756         omap_hwmod_am43xx_reg();
 757         omap_hwmod_init();
 758         return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
 759 }