2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 * Note that this file is currently not in sync with autogeneration scripts.
16 * The above note to be removed, once it is synced up.
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
24 #include <linux/platform_data/gpio-omap.h>
25 #include <linux/power/smartreflex.h>
26 #include <linux/i2c-omap.h>
28 #include <linux/omap-dma.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
31 #include <linux/platform_data/asoc-ti-mcbsp.h>
32 #include <linux/platform_data/iommu-omap.h>
33 #include <plat/dmtimer.h>
35 #include "omap_hwmod.h"
36 #include "omap_hwmod_common_data.h"
40 #include "prm-regbits-44xx.h"
45 /* Base offset for all OMAP4 interrupts external to MPUSS */
46 #define OMAP44XX_IRQ_GIC_START 32
48 /* Base offset for all OMAP4 dma requests */
49 #define OMAP44XX_DMA_REQ_START 1
59 static struct omap_hwmod_class omap44xx_dmm_hwmod_class
= {
64 static struct omap_hwmod omap44xx_dmm_hwmod
= {
66 .class = &omap44xx_dmm_hwmod_class
,
67 .clkdm_name
= "l3_emif_clkdm",
70 .clkctrl_offs
= OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET
,
71 .context_offs
= OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET
,
78 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
80 static struct omap_hwmod_class omap44xx_l3_hwmod_class
= {
85 static struct omap_hwmod omap44xx_l3_instr_hwmod
= {
87 .class = &omap44xx_l3_hwmod_class
,
88 .clkdm_name
= "l3_instr_clkdm",
91 .clkctrl_offs
= OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET
,
92 .context_offs
= OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET
,
93 .modulemode
= MODULEMODE_HWCTRL
,
99 static struct omap_hwmod omap44xx_l3_main_1_hwmod
= {
101 .class = &omap44xx_l3_hwmod_class
,
102 .clkdm_name
= "l3_1_clkdm",
105 .clkctrl_offs
= OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET
,
106 .context_offs
= OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET
,
112 static struct omap_hwmod omap44xx_l3_main_2_hwmod
= {
114 .class = &omap44xx_l3_hwmod_class
,
115 .clkdm_name
= "l3_2_clkdm",
118 .clkctrl_offs
= OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET
,
119 .context_offs
= OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET
,
125 static struct omap_hwmod omap44xx_l3_main_3_hwmod
= {
127 .class = &omap44xx_l3_hwmod_class
,
128 .clkdm_name
= "l3_instr_clkdm",
131 .clkctrl_offs
= OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET
,
132 .context_offs
= OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET
,
133 .modulemode
= MODULEMODE_HWCTRL
,
140 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
142 static struct omap_hwmod_class omap44xx_l4_hwmod_class
= {
147 static struct omap_hwmod omap44xx_l4_abe_hwmod
= {
149 .class = &omap44xx_l4_hwmod_class
,
150 .clkdm_name
= "abe_clkdm",
153 .clkctrl_offs
= OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET
,
154 .context_offs
= OMAP4_RM_ABE_AESS_CONTEXT_OFFSET
,
155 .lostcontext_mask
= OMAP4430_LOSTMEM_AESSMEM_MASK
,
156 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
162 static struct omap_hwmod omap44xx_l4_cfg_hwmod
= {
164 .class = &omap44xx_l4_hwmod_class
,
165 .clkdm_name
= "l4_cfg_clkdm",
168 .clkctrl_offs
= OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET
,
169 .context_offs
= OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET
,
175 static struct omap_hwmod omap44xx_l4_per_hwmod
= {
177 .class = &omap44xx_l4_hwmod_class
,
178 .clkdm_name
= "l4_per_clkdm",
181 .clkctrl_offs
= OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET
,
182 .context_offs
= OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET
,
188 static struct omap_hwmod omap44xx_l4_wkup_hwmod
= {
190 .class = &omap44xx_l4_hwmod_class
,
191 .clkdm_name
= "l4_wkup_clkdm",
194 .clkctrl_offs
= OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET
,
195 .context_offs
= OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET
,
202 * instance(s): mpu_private
204 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class
= {
209 static struct omap_hwmod omap44xx_mpu_private_hwmod
= {
210 .name
= "mpu_private",
211 .class = &omap44xx_mpu_bus_hwmod_class
,
212 .clkdm_name
= "mpuss_clkdm",
215 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
222 * instance(s): ocp_wp_noc
224 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class
= {
225 .name
= "ocp_wp_noc",
229 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod
= {
230 .name
= "ocp_wp_noc",
231 .class = &omap44xx_ocp_wp_noc_hwmod_class
,
232 .clkdm_name
= "l3_instr_clkdm",
235 .clkctrl_offs
= OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET
,
236 .context_offs
= OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET
,
237 .modulemode
= MODULEMODE_HWCTRL
,
243 * Modules omap_hwmod structures
245 * The following IPs are excluded for the moment because:
246 * - They do not need an explicit SW control using omap_hwmod API.
247 * - They still need to be validated with the driver
248 * properly adapted to omap_hwmod / omap_device
255 * audio engine sub system
258 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc
= {
261 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
262 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
263 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
|
264 MSTANDBY_SMART_WKUP
),
265 .sysc_fields
= &omap_hwmod_sysc_type2
,
268 static struct omap_hwmod_class omap44xx_aess_hwmod_class
= {
270 .sysc
= &omap44xx_aess_sysc
,
271 .enable_preprogram
= omap_hwmod_aess_preprogram
,
275 static struct omap_hwmod omap44xx_aess_hwmod
= {
277 .class = &omap44xx_aess_hwmod_class
,
278 .clkdm_name
= "abe_clkdm",
279 .main_clk
= "aess_fclk",
282 .clkctrl_offs
= OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET
,
283 .context_offs
= OMAP4_RM_ABE_AESS_CONTEXT_OFFSET
,
284 .lostcontext_mask
= OMAP4430_LOSTCONTEXT_DFF_MASK
,
285 .modulemode
= MODULEMODE_SWCTRL
,
292 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
296 static struct omap_hwmod_class omap44xx_c2c_hwmod_class
= {
301 static struct omap_hwmod omap44xx_c2c_hwmod
= {
303 .class = &omap44xx_c2c_hwmod_class
,
304 .clkdm_name
= "d2d_clkdm",
307 .clkctrl_offs
= OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET
,
308 .context_offs
= OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET
,
315 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
318 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc
= {
321 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
322 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
),
323 .sysc_fields
= &omap_hwmod_sysc_type1
,
326 static struct omap_hwmod_class omap44xx_counter_hwmod_class
= {
328 .sysc
= &omap44xx_counter_sysc
,
332 static struct omap_hwmod omap44xx_counter_32k_hwmod
= {
333 .name
= "counter_32k",
334 .class = &omap44xx_counter_hwmod_class
,
335 .clkdm_name
= "l4_wkup_clkdm",
336 .flags
= HWMOD_SWSUP_SIDLE
,
337 .main_clk
= "sys_32k_ck",
340 .clkctrl_offs
= OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET
,
341 .context_offs
= OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET
,
347 * 'ctrl_module' class
348 * attila core control module + core pad control module + wkup pad control
349 * module + attila wkup control module
352 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc
= {
355 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
356 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
358 .sysc_fields
= &omap_hwmod_sysc_type2
,
361 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class
= {
362 .name
= "ctrl_module",
363 .sysc
= &omap44xx_ctrl_module_sysc
,
366 /* ctrl_module_core */
367 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod
= {
368 .name
= "ctrl_module_core",
369 .class = &omap44xx_ctrl_module_hwmod_class
,
370 .clkdm_name
= "l4_cfg_clkdm",
373 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
378 /* ctrl_module_pad_core */
379 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod
= {
380 .name
= "ctrl_module_pad_core",
381 .class = &omap44xx_ctrl_module_hwmod_class
,
382 .clkdm_name
= "l4_cfg_clkdm",
385 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
390 /* ctrl_module_wkup */
391 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod
= {
392 .name
= "ctrl_module_wkup",
393 .class = &omap44xx_ctrl_module_hwmod_class
,
394 .clkdm_name
= "l4_wkup_clkdm",
397 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
402 /* ctrl_module_pad_wkup */
403 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod
= {
404 .name
= "ctrl_module_pad_wkup",
405 .class = &omap44xx_ctrl_module_hwmod_class
,
406 .clkdm_name
= "l4_wkup_clkdm",
409 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
416 * debug and emulation sub system
419 static struct omap_hwmod_class omap44xx_debugss_hwmod_class
= {
424 static struct omap_hwmod omap44xx_debugss_hwmod
= {
426 .class = &omap44xx_debugss_hwmod_class
,
427 .clkdm_name
= "emu_sys_clkdm",
428 .main_clk
= "trace_clk_div_ck",
431 .clkctrl_offs
= OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET
,
432 .context_offs
= OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET
,
439 * dma controller for data exchange between memory to memory (i.e. internal or
440 * external memory) and gp peripherals to memory or memory to gp peripherals
443 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc
= {
447 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
448 SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
449 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
450 SYSS_HAS_RESET_STATUS
),
451 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
452 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
453 .sysc_fields
= &omap_hwmod_sysc_type1
,
456 static struct omap_hwmod_class omap44xx_dma_hwmod_class
= {
458 .sysc
= &omap44xx_dma_sysc
,
462 static struct omap_dma_dev_attr dma_dev_attr
= {
463 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
464 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
469 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs
[] = {
470 { .name
= "0", .irq
= 12 + OMAP44XX_IRQ_GIC_START
},
471 { .name
= "1", .irq
= 13 + OMAP44XX_IRQ_GIC_START
},
472 { .name
= "2", .irq
= 14 + OMAP44XX_IRQ_GIC_START
},
473 { .name
= "3", .irq
= 15 + OMAP44XX_IRQ_GIC_START
},
477 static struct omap_hwmod omap44xx_dma_system_hwmod
= {
478 .name
= "dma_system",
479 .class = &omap44xx_dma_hwmod_class
,
480 .clkdm_name
= "l3_dma_clkdm",
481 .mpu_irqs
= omap44xx_dma_system_irqs
,
482 .main_clk
= "l3_div_ck",
485 .clkctrl_offs
= OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET
,
486 .context_offs
= OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET
,
489 .dev_attr
= &dma_dev_attr
,
494 * digital microphone controller
497 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc
= {
500 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
501 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
502 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
504 .sysc_fields
= &omap_hwmod_sysc_type2
,
507 static struct omap_hwmod_class omap44xx_dmic_hwmod_class
= {
509 .sysc
= &omap44xx_dmic_sysc
,
513 static struct omap_hwmod omap44xx_dmic_hwmod
= {
515 .class = &omap44xx_dmic_hwmod_class
,
516 .clkdm_name
= "abe_clkdm",
517 .main_clk
= "func_dmic_abe_gfclk",
520 .clkctrl_offs
= OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET
,
521 .context_offs
= OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET
,
522 .modulemode
= MODULEMODE_SWCTRL
,
532 static struct omap_hwmod_class omap44xx_dsp_hwmod_class
= {
537 static struct omap_hwmod_rst_info omap44xx_dsp_resets
[] = {
538 { .name
= "dsp", .rst_shift
= 0 },
541 static struct omap_hwmod omap44xx_dsp_hwmod
= {
543 .class = &omap44xx_dsp_hwmod_class
,
544 .clkdm_name
= "tesla_clkdm",
545 .rst_lines
= omap44xx_dsp_resets
,
546 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_dsp_resets
),
547 .main_clk
= "dpll_iva_m4x2_ck",
550 .clkctrl_offs
= OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET
,
551 .rstctrl_offs
= OMAP4_RM_TESLA_RSTCTRL_OFFSET
,
552 .context_offs
= OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET
,
553 .modulemode
= MODULEMODE_HWCTRL
,
563 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc
= {
566 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
569 static struct omap_hwmod_class omap44xx_dss_hwmod_class
= {
571 .sysc
= &omap44xx_dss_sysc
,
572 .reset
= omap_dss_reset
,
576 static struct omap_hwmod_opt_clk dss_opt_clks
[] = {
577 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
578 { .role
= "tv_clk", .clk
= "dss_tv_clk" },
579 { .role
= "hdmi_clk", .clk
= "dss_48mhz_clk" },
582 static struct omap_hwmod omap44xx_dss_hwmod
= {
584 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
585 .class = &omap44xx_dss_hwmod_class
,
586 .clkdm_name
= "l3_dss_clkdm",
587 .main_clk
= "dss_dss_clk",
590 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
591 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
594 .opt_clks
= dss_opt_clks
,
595 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
603 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc
= {
607 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
608 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_MIDLEMODE
|
609 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
610 SYSS_HAS_RESET_STATUS
),
611 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
612 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
613 .sysc_fields
= &omap_hwmod_sysc_type1
,
616 static struct omap_hwmod_class omap44xx_dispc_hwmod_class
= {
618 .sysc
= &omap44xx_dispc_sysc
,
622 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs
[] = {
623 { .irq
= 25 + OMAP44XX_IRQ_GIC_START
},
627 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs
[] = {
628 { .dma_req
= 5 + OMAP44XX_DMA_REQ_START
},
632 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr
= {
634 .has_framedonetv_irq
= 1
637 static struct omap_hwmod omap44xx_dss_dispc_hwmod
= {
639 .class = &omap44xx_dispc_hwmod_class
,
640 .clkdm_name
= "l3_dss_clkdm",
641 .mpu_irqs
= omap44xx_dss_dispc_irqs
,
642 .sdma_reqs
= omap44xx_dss_dispc_sdma_reqs
,
643 .main_clk
= "dss_dss_clk",
646 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
647 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
650 .dev_attr
= &omap44xx_dss_dispc_dev_attr
655 * display serial interface controller
658 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc
= {
662 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
663 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
664 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
665 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
666 .sysc_fields
= &omap_hwmod_sysc_type1
,
669 static struct omap_hwmod_class omap44xx_dsi_hwmod_class
= {
671 .sysc
= &omap44xx_dsi_sysc
,
675 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs
[] = {
676 { .irq
= 53 + OMAP44XX_IRQ_GIC_START
},
680 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs
[] = {
681 { .dma_req
= 74 + OMAP44XX_DMA_REQ_START
},
685 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks
[] = {
686 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
689 static struct omap_hwmod omap44xx_dss_dsi1_hwmod
= {
691 .class = &omap44xx_dsi_hwmod_class
,
692 .clkdm_name
= "l3_dss_clkdm",
693 .mpu_irqs
= omap44xx_dss_dsi1_irqs
,
694 .sdma_reqs
= omap44xx_dss_dsi1_sdma_reqs
,
695 .main_clk
= "dss_dss_clk",
698 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
699 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
702 .opt_clks
= dss_dsi1_opt_clks
,
703 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi1_opt_clks
),
707 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs
[] = {
708 { .irq
= 84 + OMAP44XX_IRQ_GIC_START
},
712 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs
[] = {
713 { .dma_req
= 83 + OMAP44XX_DMA_REQ_START
},
717 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks
[] = {
718 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
721 static struct omap_hwmod omap44xx_dss_dsi2_hwmod
= {
723 .class = &omap44xx_dsi_hwmod_class
,
724 .clkdm_name
= "l3_dss_clkdm",
725 .mpu_irqs
= omap44xx_dss_dsi2_irqs
,
726 .sdma_reqs
= omap44xx_dss_dsi2_sdma_reqs
,
727 .main_clk
= "dss_dss_clk",
730 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
731 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
734 .opt_clks
= dss_dsi2_opt_clks
,
735 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi2_opt_clks
),
743 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc
= {
746 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
748 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
750 .sysc_fields
= &omap_hwmod_sysc_type2
,
753 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class
= {
755 .sysc
= &omap44xx_hdmi_sysc
,
759 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs
[] = {
760 { .irq
= 101 + OMAP44XX_IRQ_GIC_START
},
764 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs
[] = {
765 { .dma_req
= 75 + OMAP44XX_DMA_REQ_START
},
769 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks
[] = {
770 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
773 static struct omap_hwmod omap44xx_dss_hdmi_hwmod
= {
775 .class = &omap44xx_hdmi_hwmod_class
,
776 .clkdm_name
= "l3_dss_clkdm",
778 * HDMI audio requires to use no-idle mode. Hence,
779 * set idle mode by software.
781 .flags
= HWMOD_SWSUP_SIDLE
,
782 .mpu_irqs
= omap44xx_dss_hdmi_irqs
,
783 .sdma_reqs
= omap44xx_dss_hdmi_sdma_reqs
,
784 .main_clk
= "dss_48mhz_clk",
787 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
788 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
791 .opt_clks
= dss_hdmi_opt_clks
,
792 .opt_clks_cnt
= ARRAY_SIZE(dss_hdmi_opt_clks
),
797 * remote frame buffer interface
800 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc
= {
804 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
805 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
806 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
807 .sysc_fields
= &omap_hwmod_sysc_type1
,
810 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class
= {
812 .sysc
= &omap44xx_rfbi_sysc
,
816 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs
[] = {
817 { .dma_req
= 13 + OMAP44XX_DMA_REQ_START
},
821 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks
[] = {
822 { .role
= "ick", .clk
= "dss_fck" },
825 static struct omap_hwmod omap44xx_dss_rfbi_hwmod
= {
827 .class = &omap44xx_rfbi_hwmod_class
,
828 .clkdm_name
= "l3_dss_clkdm",
829 .sdma_reqs
= omap44xx_dss_rfbi_sdma_reqs
,
830 .main_clk
= "dss_dss_clk",
833 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
834 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
837 .opt_clks
= dss_rfbi_opt_clks
,
838 .opt_clks_cnt
= ARRAY_SIZE(dss_rfbi_opt_clks
),
846 static struct omap_hwmod_class omap44xx_venc_hwmod_class
= {
851 static struct omap_hwmod omap44xx_dss_venc_hwmod
= {
853 .class = &omap44xx_venc_hwmod_class
,
854 .clkdm_name
= "l3_dss_clkdm",
855 .main_clk
= "dss_tv_clk",
858 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
859 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
866 * bch error location module
869 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc
= {
873 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
874 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
875 SYSS_HAS_RESET_STATUS
),
876 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
877 .sysc_fields
= &omap_hwmod_sysc_type1
,
880 static struct omap_hwmod_class omap44xx_elm_hwmod_class
= {
882 .sysc
= &omap44xx_elm_sysc
,
886 static struct omap_hwmod omap44xx_elm_hwmod
= {
888 .class = &omap44xx_elm_hwmod_class
,
889 .clkdm_name
= "l4_per_clkdm",
892 .clkctrl_offs
= OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET
,
893 .context_offs
= OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET
,
900 * external memory interface no1
903 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc
= {
907 static struct omap_hwmod_class omap44xx_emif_hwmod_class
= {
909 .sysc
= &omap44xx_emif_sysc
,
913 static struct omap_hwmod omap44xx_emif1_hwmod
= {
915 .class = &omap44xx_emif_hwmod_class
,
916 .clkdm_name
= "l3_emif_clkdm",
917 .flags
= HWMOD_INIT_NO_IDLE
,
918 .main_clk
= "ddrphy_ck",
921 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET
,
922 .context_offs
= OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET
,
923 .modulemode
= MODULEMODE_HWCTRL
,
929 static struct omap_hwmod omap44xx_emif2_hwmod
= {
931 .class = &omap44xx_emif_hwmod_class
,
932 .clkdm_name
= "l3_emif_clkdm",
933 .flags
= HWMOD_INIT_NO_IDLE
,
934 .main_clk
= "ddrphy_ck",
937 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET
,
938 .context_offs
= OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET
,
939 .modulemode
= MODULEMODE_HWCTRL
,
946 * face detection hw accelerator module
949 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc
= {
953 * FDIF needs 100 OCP clk cycles delay after a softreset before
954 * accessing sysconfig again.
955 * The lowest frequency at the moment for L3 bus is 100 MHz, so
956 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
958 * TODO: Indicate errata when available.
961 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
962 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
963 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
964 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
965 .sysc_fields
= &omap_hwmod_sysc_type2
,
968 static struct omap_hwmod_class omap44xx_fdif_hwmod_class
= {
970 .sysc
= &omap44xx_fdif_sysc
,
974 static struct omap_hwmod omap44xx_fdif_hwmod
= {
976 .class = &omap44xx_fdif_hwmod_class
,
977 .clkdm_name
= "iss_clkdm",
978 .main_clk
= "fdif_fck",
981 .clkctrl_offs
= OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET
,
982 .context_offs
= OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET
,
983 .modulemode
= MODULEMODE_SWCTRL
,
990 * general purpose io module
993 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc
= {
997 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
998 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
999 SYSS_HAS_RESET_STATUS
),
1000 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1002 .sysc_fields
= &omap_hwmod_sysc_type1
,
1005 static struct omap_hwmod_class omap44xx_gpio_hwmod_class
= {
1007 .sysc
= &omap44xx_gpio_sysc
,
1012 static struct omap_gpio_dev_attr gpio_dev_attr
= {
1018 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
1019 { .role
= "dbclk", .clk
= "gpio1_dbclk" },
1022 static struct omap_hwmod omap44xx_gpio1_hwmod
= {
1024 .class = &omap44xx_gpio_hwmod_class
,
1025 .clkdm_name
= "l4_wkup_clkdm",
1026 .main_clk
= "l4_wkup_clk_mux_ck",
1029 .clkctrl_offs
= OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET
,
1030 .context_offs
= OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET
,
1031 .modulemode
= MODULEMODE_HWCTRL
,
1034 .opt_clks
= gpio1_opt_clks
,
1035 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
1036 .dev_attr
= &gpio_dev_attr
,
1040 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
1041 { .role
= "dbclk", .clk
= "gpio2_dbclk" },
1044 static struct omap_hwmod omap44xx_gpio2_hwmod
= {
1046 .class = &omap44xx_gpio_hwmod_class
,
1047 .clkdm_name
= "l4_per_clkdm",
1048 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1049 .main_clk
= "l4_div_ck",
1052 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET
,
1053 .context_offs
= OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET
,
1054 .modulemode
= MODULEMODE_HWCTRL
,
1057 .opt_clks
= gpio2_opt_clks
,
1058 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
1059 .dev_attr
= &gpio_dev_attr
,
1063 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
1064 { .role
= "dbclk", .clk
= "gpio3_dbclk" },
1067 static struct omap_hwmod omap44xx_gpio3_hwmod
= {
1069 .class = &omap44xx_gpio_hwmod_class
,
1070 .clkdm_name
= "l4_per_clkdm",
1071 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1072 .main_clk
= "l4_div_ck",
1075 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET
,
1076 .context_offs
= OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET
,
1077 .modulemode
= MODULEMODE_HWCTRL
,
1080 .opt_clks
= gpio3_opt_clks
,
1081 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
1082 .dev_attr
= &gpio_dev_attr
,
1086 static struct omap_hwmod_opt_clk gpio4_opt_clks
[] = {
1087 { .role
= "dbclk", .clk
= "gpio4_dbclk" },
1090 static struct omap_hwmod omap44xx_gpio4_hwmod
= {
1092 .class = &omap44xx_gpio_hwmod_class
,
1093 .clkdm_name
= "l4_per_clkdm",
1094 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1095 .main_clk
= "l4_div_ck",
1098 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET
,
1099 .context_offs
= OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET
,
1100 .modulemode
= MODULEMODE_HWCTRL
,
1103 .opt_clks
= gpio4_opt_clks
,
1104 .opt_clks_cnt
= ARRAY_SIZE(gpio4_opt_clks
),
1105 .dev_attr
= &gpio_dev_attr
,
1109 static struct omap_hwmod_opt_clk gpio5_opt_clks
[] = {
1110 { .role
= "dbclk", .clk
= "gpio5_dbclk" },
1113 static struct omap_hwmod omap44xx_gpio5_hwmod
= {
1115 .class = &omap44xx_gpio_hwmod_class
,
1116 .clkdm_name
= "l4_per_clkdm",
1117 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1118 .main_clk
= "l4_div_ck",
1121 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET
,
1122 .context_offs
= OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET
,
1123 .modulemode
= MODULEMODE_HWCTRL
,
1126 .opt_clks
= gpio5_opt_clks
,
1127 .opt_clks_cnt
= ARRAY_SIZE(gpio5_opt_clks
),
1128 .dev_attr
= &gpio_dev_attr
,
1132 static struct omap_hwmod_opt_clk gpio6_opt_clks
[] = {
1133 { .role
= "dbclk", .clk
= "gpio6_dbclk" },
1136 static struct omap_hwmod omap44xx_gpio6_hwmod
= {
1138 .class = &omap44xx_gpio_hwmod_class
,
1139 .clkdm_name
= "l4_per_clkdm",
1140 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1141 .main_clk
= "l4_div_ck",
1144 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET
,
1145 .context_offs
= OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET
,
1146 .modulemode
= MODULEMODE_HWCTRL
,
1149 .opt_clks
= gpio6_opt_clks
,
1150 .opt_clks_cnt
= ARRAY_SIZE(gpio6_opt_clks
),
1151 .dev_attr
= &gpio_dev_attr
,
1156 * general purpose memory controller
1159 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc
= {
1161 .sysc_offs
= 0x0010,
1162 .syss_offs
= 0x0014,
1163 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
1164 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1165 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1166 .sysc_fields
= &omap_hwmod_sysc_type1
,
1169 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class
= {
1171 .sysc
= &omap44xx_gpmc_sysc
,
1175 static struct omap_hwmod omap44xx_gpmc_hwmod
= {
1177 .class = &omap44xx_gpmc_hwmod_class
,
1178 .clkdm_name
= "l3_2_clkdm",
1180 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1181 * block. It is not being added due to any known bugs with
1182 * resetting the GPMC IP block, but rather because any timings
1183 * set by the bootloader are not being correctly programmed by
1184 * the kernel from the board file or DT data.
1185 * HWMOD_INIT_NO_RESET should be removed ASAP.
1187 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1190 .clkctrl_offs
= OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET
,
1191 .context_offs
= OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET
,
1192 .modulemode
= MODULEMODE_HWCTRL
,
1199 * 2d/3d graphics accelerator
1202 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc
= {
1203 .rev_offs
= 0x1fc00,
1204 .sysc_offs
= 0x1fc10,
1205 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
1206 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1207 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1208 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1209 .sysc_fields
= &omap_hwmod_sysc_type2
,
1212 static struct omap_hwmod_class omap44xx_gpu_hwmod_class
= {
1214 .sysc
= &omap44xx_gpu_sysc
,
1218 static struct omap_hwmod omap44xx_gpu_hwmod
= {
1220 .class = &omap44xx_gpu_hwmod_class
,
1221 .clkdm_name
= "l3_gfx_clkdm",
1222 .main_clk
= "sgx_clk_mux",
1225 .clkctrl_offs
= OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET
,
1226 .context_offs
= OMAP4_RM_GFX_GFX_CONTEXT_OFFSET
,
1227 .modulemode
= MODULEMODE_SWCTRL
,
1234 * hdq / 1-wire serial interface controller
1237 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc
= {
1239 .sysc_offs
= 0x0014,
1240 .syss_offs
= 0x0018,
1241 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SOFTRESET
|
1242 SYSS_HAS_RESET_STATUS
),
1243 .sysc_fields
= &omap_hwmod_sysc_type1
,
1246 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class
= {
1248 .sysc
= &omap44xx_hdq1w_sysc
,
1252 static struct omap_hwmod omap44xx_hdq1w_hwmod
= {
1254 .class = &omap44xx_hdq1w_hwmod_class
,
1255 .clkdm_name
= "l4_per_clkdm",
1256 .flags
= HWMOD_INIT_NO_RESET
, /* XXX temporary */
1257 .main_clk
= "func_12m_fclk",
1260 .clkctrl_offs
= OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET
,
1261 .context_offs
= OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET
,
1262 .modulemode
= MODULEMODE_SWCTRL
,
1269 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1273 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc
= {
1275 .sysc_offs
= 0x0010,
1276 .syss_offs
= 0x0014,
1277 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_EMUFREE
|
1278 SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
1279 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1280 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1281 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1282 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1283 .sysc_fields
= &omap_hwmod_sysc_type1
,
1286 static struct omap_hwmod_class omap44xx_hsi_hwmod_class
= {
1288 .sysc
= &omap44xx_hsi_sysc
,
1292 static struct omap_hwmod omap44xx_hsi_hwmod
= {
1294 .class = &omap44xx_hsi_hwmod_class
,
1295 .clkdm_name
= "l3_init_clkdm",
1296 .main_clk
= "hsi_fck",
1299 .clkctrl_offs
= OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET
,
1300 .context_offs
= OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET
,
1301 .modulemode
= MODULEMODE_HWCTRL
,
1308 * multimaster high-speed i2c controller
1311 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc
= {
1312 .sysc_offs
= 0x0010,
1313 .syss_offs
= 0x0090,
1314 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1315 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
1316 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1317 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1319 .clockact
= CLOCKACT_TEST_ICLK
,
1320 .sysc_fields
= &omap_hwmod_sysc_type1
,
1323 static struct omap_hwmod_class omap44xx_i2c_hwmod_class
= {
1325 .sysc
= &omap44xx_i2c_sysc
,
1326 .rev
= OMAP_I2C_IP_VERSION_2
,
1327 .reset
= &omap_i2c_reset
,
1330 static struct omap_i2c_dev_attr i2c_dev_attr
= {
1331 .flags
= OMAP_I2C_FLAG_BUS_SHIFT_NONE
,
1335 static struct omap_hwmod omap44xx_i2c1_hwmod
= {
1337 .class = &omap44xx_i2c_hwmod_class
,
1338 .clkdm_name
= "l4_per_clkdm",
1339 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1340 .main_clk
= "func_96m_fclk",
1343 .clkctrl_offs
= OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET
,
1344 .context_offs
= OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET
,
1345 .modulemode
= MODULEMODE_SWCTRL
,
1348 .dev_attr
= &i2c_dev_attr
,
1352 static struct omap_hwmod omap44xx_i2c2_hwmod
= {
1354 .class = &omap44xx_i2c_hwmod_class
,
1355 .clkdm_name
= "l4_per_clkdm",
1356 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1357 .main_clk
= "func_96m_fclk",
1360 .clkctrl_offs
= OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET
,
1361 .context_offs
= OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET
,
1362 .modulemode
= MODULEMODE_SWCTRL
,
1365 .dev_attr
= &i2c_dev_attr
,
1369 static struct omap_hwmod omap44xx_i2c3_hwmod
= {
1371 .class = &omap44xx_i2c_hwmod_class
,
1372 .clkdm_name
= "l4_per_clkdm",
1373 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1374 .main_clk
= "func_96m_fclk",
1377 .clkctrl_offs
= OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET
,
1378 .context_offs
= OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET
,
1379 .modulemode
= MODULEMODE_SWCTRL
,
1382 .dev_attr
= &i2c_dev_attr
,
1386 static struct omap_hwmod omap44xx_i2c4_hwmod
= {
1388 .class = &omap44xx_i2c_hwmod_class
,
1389 .clkdm_name
= "l4_per_clkdm",
1390 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1391 .main_clk
= "func_96m_fclk",
1394 .clkctrl_offs
= OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET
,
1395 .context_offs
= OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET
,
1396 .modulemode
= MODULEMODE_SWCTRL
,
1399 .dev_attr
= &i2c_dev_attr
,
1404 * imaging processor unit
1407 static struct omap_hwmod_class omap44xx_ipu_hwmod_class
= {
1412 static struct omap_hwmod_rst_info omap44xx_ipu_resets
[] = {
1413 { .name
= "cpu0", .rst_shift
= 0 },
1414 { .name
= "cpu1", .rst_shift
= 1 },
1417 static struct omap_hwmod omap44xx_ipu_hwmod
= {
1419 .class = &omap44xx_ipu_hwmod_class
,
1420 .clkdm_name
= "ducati_clkdm",
1421 .rst_lines
= omap44xx_ipu_resets
,
1422 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_ipu_resets
),
1423 .main_clk
= "ducati_clk_mux_ck",
1426 .clkctrl_offs
= OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET
,
1427 .rstctrl_offs
= OMAP4_RM_DUCATI_RSTCTRL_OFFSET
,
1428 .context_offs
= OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET
,
1429 .modulemode
= MODULEMODE_HWCTRL
,
1436 * external images sensor pixel data processor
1439 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc
= {
1441 .sysc_offs
= 0x0010,
1443 * ISS needs 100 OCP clk cycles delay after a softreset before
1444 * accessing sysconfig again.
1445 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1446 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1448 * TODO: Indicate errata when available.
1451 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
1452 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1453 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1454 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1455 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1456 .sysc_fields
= &omap_hwmod_sysc_type2
,
1459 static struct omap_hwmod_class omap44xx_iss_hwmod_class
= {
1461 .sysc
= &omap44xx_iss_sysc
,
1465 static struct omap_hwmod_opt_clk iss_opt_clks
[] = {
1466 { .role
= "ctrlclk", .clk
= "iss_ctrlclk" },
1469 static struct omap_hwmod omap44xx_iss_hwmod
= {
1471 .class = &omap44xx_iss_hwmod_class
,
1472 .clkdm_name
= "iss_clkdm",
1473 .main_clk
= "ducati_clk_mux_ck",
1476 .clkctrl_offs
= OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET
,
1477 .context_offs
= OMAP4_RM_CAM_ISS_CONTEXT_OFFSET
,
1478 .modulemode
= MODULEMODE_SWCTRL
,
1481 .opt_clks
= iss_opt_clks
,
1482 .opt_clks_cnt
= ARRAY_SIZE(iss_opt_clks
),
1487 * multi-standard video encoder/decoder hardware accelerator
1490 static struct omap_hwmod_class omap44xx_iva_hwmod_class
= {
1495 static struct omap_hwmod_rst_info omap44xx_iva_resets
[] = {
1496 { .name
= "seq0", .rst_shift
= 0 },
1497 { .name
= "seq1", .rst_shift
= 1 },
1498 { .name
= "logic", .rst_shift
= 2 },
1501 static struct omap_hwmod omap44xx_iva_hwmod
= {
1503 .class = &omap44xx_iva_hwmod_class
,
1504 .clkdm_name
= "ivahd_clkdm",
1505 .rst_lines
= omap44xx_iva_resets
,
1506 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_iva_resets
),
1507 .main_clk
= "dpll_iva_m5x2_ck",
1510 .clkctrl_offs
= OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET
,
1511 .rstctrl_offs
= OMAP4_RM_IVAHD_RSTCTRL_OFFSET
,
1512 .context_offs
= OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET
,
1513 .modulemode
= MODULEMODE_HWCTRL
,
1520 * keyboard controller
1523 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc
= {
1525 .sysc_offs
= 0x0010,
1526 .syss_offs
= 0x0014,
1527 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1528 SYSC_HAS_EMUFREE
| SYSC_HAS_ENAWAKEUP
|
1529 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1530 SYSS_HAS_RESET_STATUS
),
1531 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1532 .sysc_fields
= &omap_hwmod_sysc_type1
,
1535 static struct omap_hwmod_class omap44xx_kbd_hwmod_class
= {
1537 .sysc
= &omap44xx_kbd_sysc
,
1541 static struct omap_hwmod omap44xx_kbd_hwmod
= {
1543 .class = &omap44xx_kbd_hwmod_class
,
1544 .clkdm_name
= "l4_wkup_clkdm",
1545 .main_clk
= "sys_32k_ck",
1548 .clkctrl_offs
= OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET
,
1549 .context_offs
= OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET
,
1550 .modulemode
= MODULEMODE_SWCTRL
,
1557 * mailbox module allowing communication between the on-chip processors using a
1558 * queued mailbox-interrupt mechanism.
1561 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc
= {
1563 .sysc_offs
= 0x0010,
1564 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
1565 SYSC_HAS_SOFTRESET
),
1566 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1567 .sysc_fields
= &omap_hwmod_sysc_type2
,
1570 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class
= {
1572 .sysc
= &omap44xx_mailbox_sysc
,
1576 static struct omap_hwmod omap44xx_mailbox_hwmod
= {
1578 .class = &omap44xx_mailbox_hwmod_class
,
1579 .clkdm_name
= "l4_cfg_clkdm",
1582 .clkctrl_offs
= OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET
,
1583 .context_offs
= OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET
,
1590 * multi-channel audio serial port controller
1593 /* The IP is not compliant to type1 / type2 scheme */
1594 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp
= {
1598 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc
= {
1599 .sysc_offs
= 0x0004,
1600 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
1601 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1603 .sysc_fields
= &omap_hwmod_sysc_type_mcasp
,
1606 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class
= {
1608 .sysc
= &omap44xx_mcasp_sysc
,
1612 static struct omap_hwmod omap44xx_mcasp_hwmod
= {
1614 .class = &omap44xx_mcasp_hwmod_class
,
1615 .clkdm_name
= "abe_clkdm",
1616 .main_clk
= "func_mcasp_abe_gfclk",
1619 .clkctrl_offs
= OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET
,
1620 .context_offs
= OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET
,
1621 .modulemode
= MODULEMODE_SWCTRL
,
1628 * multi channel buffered serial port controller
1631 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc
= {
1632 .sysc_offs
= 0x008c,
1633 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_ENAWAKEUP
|
1634 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1635 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1636 .sysc_fields
= &omap_hwmod_sysc_type1
,
1639 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class
= {
1641 .sysc
= &omap44xx_mcbsp_sysc
,
1642 .rev
= MCBSP_CONFIG_TYPE4
,
1646 static struct omap_hwmod_opt_clk mcbsp1_opt_clks
[] = {
1647 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1648 { .role
= "prcm_fck", .clk
= "mcbsp1_sync_mux_ck" },
1651 static struct omap_hwmod omap44xx_mcbsp1_hwmod
= {
1653 .class = &omap44xx_mcbsp_hwmod_class
,
1654 .clkdm_name
= "abe_clkdm",
1655 .main_clk
= "func_mcbsp1_gfclk",
1658 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET
,
1659 .context_offs
= OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET
,
1660 .modulemode
= MODULEMODE_SWCTRL
,
1663 .opt_clks
= mcbsp1_opt_clks
,
1664 .opt_clks_cnt
= ARRAY_SIZE(mcbsp1_opt_clks
),
1668 static struct omap_hwmod_opt_clk mcbsp2_opt_clks
[] = {
1669 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1670 { .role
= "prcm_fck", .clk
= "mcbsp2_sync_mux_ck" },
1673 static struct omap_hwmod omap44xx_mcbsp2_hwmod
= {
1675 .class = &omap44xx_mcbsp_hwmod_class
,
1676 .clkdm_name
= "abe_clkdm",
1677 .main_clk
= "func_mcbsp2_gfclk",
1680 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET
,
1681 .context_offs
= OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET
,
1682 .modulemode
= MODULEMODE_SWCTRL
,
1685 .opt_clks
= mcbsp2_opt_clks
,
1686 .opt_clks_cnt
= ARRAY_SIZE(mcbsp2_opt_clks
),
1690 static struct omap_hwmod_opt_clk mcbsp3_opt_clks
[] = {
1691 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1692 { .role
= "prcm_fck", .clk
= "mcbsp3_sync_mux_ck" },
1695 static struct omap_hwmod omap44xx_mcbsp3_hwmod
= {
1697 .class = &omap44xx_mcbsp_hwmod_class
,
1698 .clkdm_name
= "abe_clkdm",
1699 .main_clk
= "func_mcbsp3_gfclk",
1702 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET
,
1703 .context_offs
= OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET
,
1704 .modulemode
= MODULEMODE_SWCTRL
,
1707 .opt_clks
= mcbsp3_opt_clks
,
1708 .opt_clks_cnt
= ARRAY_SIZE(mcbsp3_opt_clks
),
1712 static struct omap_hwmod_opt_clk mcbsp4_opt_clks
[] = {
1713 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1714 { .role
= "prcm_fck", .clk
= "mcbsp4_sync_mux_ck" },
1717 static struct omap_hwmod omap44xx_mcbsp4_hwmod
= {
1719 .class = &omap44xx_mcbsp_hwmod_class
,
1720 .clkdm_name
= "l4_per_clkdm",
1721 .main_clk
= "per_mcbsp4_gfclk",
1724 .clkctrl_offs
= OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET
,
1725 .context_offs
= OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET
,
1726 .modulemode
= MODULEMODE_SWCTRL
,
1729 .opt_clks
= mcbsp4_opt_clks
,
1730 .opt_clks_cnt
= ARRAY_SIZE(mcbsp4_opt_clks
),
1735 * multi channel pdm controller (proprietary interface with phoenix power
1739 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc
= {
1741 .sysc_offs
= 0x0010,
1742 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1743 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1744 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1746 .sysc_fields
= &omap_hwmod_sysc_type2
,
1749 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class
= {
1751 .sysc
= &omap44xx_mcpdm_sysc
,
1755 static struct omap_hwmod omap44xx_mcpdm_hwmod
= {
1757 .class = &omap44xx_mcpdm_hwmod_class
,
1758 .clkdm_name
= "abe_clkdm",
1760 * It's suspected that the McPDM requires an off-chip main
1761 * functional clock, controlled via I2C. This IP block is
1762 * currently reset very early during boot, before I2C is
1763 * available, so it doesn't seem that we have any choice in
1764 * the kernel other than to avoid resetting it.
1766 * Also, McPDM needs to be configured to NO_IDLE mode when it
1767 * is in used otherwise vital clocks will be gated which
1768 * results 'slow motion' audio playback.
1770 .flags
= HWMOD_EXT_OPT_MAIN_CLK
| HWMOD_SWSUP_SIDLE
,
1771 .main_clk
= "pad_clks_ck",
1774 .clkctrl_offs
= OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET
,
1775 .context_offs
= OMAP4_RM_ABE_PDM_CONTEXT_OFFSET
,
1776 .modulemode
= MODULEMODE_SWCTRL
,
1783 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1787 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc
= {
1789 .sysc_offs
= 0x0010,
1790 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1791 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1792 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1794 .sysc_fields
= &omap_hwmod_sysc_type2
,
1797 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class
= {
1799 .sysc
= &omap44xx_mcspi_sysc
,
1800 .rev
= OMAP4_MCSPI_REV
,
1804 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs
[] = {
1805 { .name
= "tx0", .dma_req
= 34 + OMAP44XX_DMA_REQ_START
},
1806 { .name
= "rx0", .dma_req
= 35 + OMAP44XX_DMA_REQ_START
},
1807 { .name
= "tx1", .dma_req
= 36 + OMAP44XX_DMA_REQ_START
},
1808 { .name
= "rx1", .dma_req
= 37 + OMAP44XX_DMA_REQ_START
},
1809 { .name
= "tx2", .dma_req
= 38 + OMAP44XX_DMA_REQ_START
},
1810 { .name
= "rx2", .dma_req
= 39 + OMAP44XX_DMA_REQ_START
},
1811 { .name
= "tx3", .dma_req
= 40 + OMAP44XX_DMA_REQ_START
},
1812 { .name
= "rx3", .dma_req
= 41 + OMAP44XX_DMA_REQ_START
},
1816 /* mcspi1 dev_attr */
1817 static struct omap2_mcspi_dev_attr mcspi1_dev_attr
= {
1818 .num_chipselect
= 4,
1821 static struct omap_hwmod omap44xx_mcspi1_hwmod
= {
1823 .class = &omap44xx_mcspi_hwmod_class
,
1824 .clkdm_name
= "l4_per_clkdm",
1825 .sdma_reqs
= omap44xx_mcspi1_sdma_reqs
,
1826 .main_clk
= "func_48m_fclk",
1829 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET
,
1830 .context_offs
= OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET
,
1831 .modulemode
= MODULEMODE_SWCTRL
,
1834 .dev_attr
= &mcspi1_dev_attr
,
1838 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs
[] = {
1839 { .name
= "tx0", .dma_req
= 42 + OMAP44XX_DMA_REQ_START
},
1840 { .name
= "rx0", .dma_req
= 43 + OMAP44XX_DMA_REQ_START
},
1841 { .name
= "tx1", .dma_req
= 44 + OMAP44XX_DMA_REQ_START
},
1842 { .name
= "rx1", .dma_req
= 45 + OMAP44XX_DMA_REQ_START
},
1846 /* mcspi2 dev_attr */
1847 static struct omap2_mcspi_dev_attr mcspi2_dev_attr
= {
1848 .num_chipselect
= 2,
1851 static struct omap_hwmod omap44xx_mcspi2_hwmod
= {
1853 .class = &omap44xx_mcspi_hwmod_class
,
1854 .clkdm_name
= "l4_per_clkdm",
1855 .sdma_reqs
= omap44xx_mcspi2_sdma_reqs
,
1856 .main_clk
= "func_48m_fclk",
1859 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET
,
1860 .context_offs
= OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET
,
1861 .modulemode
= MODULEMODE_SWCTRL
,
1864 .dev_attr
= &mcspi2_dev_attr
,
1868 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs
[] = {
1869 { .name
= "tx0", .dma_req
= 14 + OMAP44XX_DMA_REQ_START
},
1870 { .name
= "rx0", .dma_req
= 15 + OMAP44XX_DMA_REQ_START
},
1871 { .name
= "tx1", .dma_req
= 22 + OMAP44XX_DMA_REQ_START
},
1872 { .name
= "rx1", .dma_req
= 23 + OMAP44XX_DMA_REQ_START
},
1876 /* mcspi3 dev_attr */
1877 static struct omap2_mcspi_dev_attr mcspi3_dev_attr
= {
1878 .num_chipselect
= 2,
1881 static struct omap_hwmod omap44xx_mcspi3_hwmod
= {
1883 .class = &omap44xx_mcspi_hwmod_class
,
1884 .clkdm_name
= "l4_per_clkdm",
1885 .sdma_reqs
= omap44xx_mcspi3_sdma_reqs
,
1886 .main_clk
= "func_48m_fclk",
1889 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET
,
1890 .context_offs
= OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET
,
1891 .modulemode
= MODULEMODE_SWCTRL
,
1894 .dev_attr
= &mcspi3_dev_attr
,
1898 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs
[] = {
1899 { .name
= "tx0", .dma_req
= 69 + OMAP44XX_DMA_REQ_START
},
1900 { .name
= "rx0", .dma_req
= 70 + OMAP44XX_DMA_REQ_START
},
1904 /* mcspi4 dev_attr */
1905 static struct omap2_mcspi_dev_attr mcspi4_dev_attr
= {
1906 .num_chipselect
= 1,
1909 static struct omap_hwmod omap44xx_mcspi4_hwmod
= {
1911 .class = &omap44xx_mcspi_hwmod_class
,
1912 .clkdm_name
= "l4_per_clkdm",
1913 .sdma_reqs
= omap44xx_mcspi4_sdma_reqs
,
1914 .main_clk
= "func_48m_fclk",
1917 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET
,
1918 .context_offs
= OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET
,
1919 .modulemode
= MODULEMODE_SWCTRL
,
1922 .dev_attr
= &mcspi4_dev_attr
,
1927 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1930 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc
= {
1932 .sysc_offs
= 0x0010,
1933 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
1934 SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
1935 SYSC_HAS_SOFTRESET
),
1936 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1937 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1938 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1939 .sysc_fields
= &omap_hwmod_sysc_type2
,
1942 static struct omap_hwmod_class omap44xx_mmc_hwmod_class
= {
1944 .sysc
= &omap44xx_mmc_sysc
,
1948 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs
[] = {
1949 { .name
= "tx", .dma_req
= 60 + OMAP44XX_DMA_REQ_START
},
1950 { .name
= "rx", .dma_req
= 61 + OMAP44XX_DMA_REQ_START
},
1955 static struct omap_mmc_dev_attr mmc1_dev_attr
= {
1956 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
1959 static struct omap_hwmod omap44xx_mmc1_hwmod
= {
1961 .class = &omap44xx_mmc_hwmod_class
,
1962 .clkdm_name
= "l3_init_clkdm",
1963 .sdma_reqs
= omap44xx_mmc1_sdma_reqs
,
1964 .main_clk
= "hsmmc1_fclk",
1967 .clkctrl_offs
= OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET
,
1968 .context_offs
= OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET
,
1969 .modulemode
= MODULEMODE_SWCTRL
,
1972 .dev_attr
= &mmc1_dev_attr
,
1976 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs
[] = {
1977 { .name
= "tx", .dma_req
= 46 + OMAP44XX_DMA_REQ_START
},
1978 { .name
= "rx", .dma_req
= 47 + OMAP44XX_DMA_REQ_START
},
1982 static struct omap_hwmod omap44xx_mmc2_hwmod
= {
1984 .class = &omap44xx_mmc_hwmod_class
,
1985 .clkdm_name
= "l3_init_clkdm",
1986 .sdma_reqs
= omap44xx_mmc2_sdma_reqs
,
1987 .main_clk
= "hsmmc2_fclk",
1990 .clkctrl_offs
= OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET
,
1991 .context_offs
= OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET
,
1992 .modulemode
= MODULEMODE_SWCTRL
,
1998 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs
[] = {
1999 { .name
= "tx", .dma_req
= 76 + OMAP44XX_DMA_REQ_START
},
2000 { .name
= "rx", .dma_req
= 77 + OMAP44XX_DMA_REQ_START
},
2004 static struct omap_hwmod omap44xx_mmc3_hwmod
= {
2006 .class = &omap44xx_mmc_hwmod_class
,
2007 .clkdm_name
= "l4_per_clkdm",
2008 .sdma_reqs
= omap44xx_mmc3_sdma_reqs
,
2009 .main_clk
= "func_48m_fclk",
2012 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET
,
2013 .context_offs
= OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET
,
2014 .modulemode
= MODULEMODE_SWCTRL
,
2020 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs
[] = {
2021 { .name
= "tx", .dma_req
= 56 + OMAP44XX_DMA_REQ_START
},
2022 { .name
= "rx", .dma_req
= 57 + OMAP44XX_DMA_REQ_START
},
2026 static struct omap_hwmod omap44xx_mmc4_hwmod
= {
2028 .class = &omap44xx_mmc_hwmod_class
,
2029 .clkdm_name
= "l4_per_clkdm",
2030 .sdma_reqs
= omap44xx_mmc4_sdma_reqs
,
2031 .main_clk
= "func_48m_fclk",
2034 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET
,
2035 .context_offs
= OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET
,
2036 .modulemode
= MODULEMODE_SWCTRL
,
2042 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs
[] = {
2043 { .name
= "tx", .dma_req
= 58 + OMAP44XX_DMA_REQ_START
},
2044 { .name
= "rx", .dma_req
= 59 + OMAP44XX_DMA_REQ_START
},
2048 static struct omap_hwmod omap44xx_mmc5_hwmod
= {
2050 .class = &omap44xx_mmc_hwmod_class
,
2051 .clkdm_name
= "l4_per_clkdm",
2052 .sdma_reqs
= omap44xx_mmc5_sdma_reqs
,
2053 .main_clk
= "func_48m_fclk",
2056 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET
,
2057 .context_offs
= OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET
,
2058 .modulemode
= MODULEMODE_SWCTRL
,
2065 * The memory management unit performs virtual to physical address translation
2066 * for its requestors.
2069 static struct omap_hwmod_class_sysconfig mmu_sysc
= {
2073 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
2074 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
2075 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2076 .sysc_fields
= &omap_hwmod_sysc_type1
,
2079 static struct omap_hwmod_class omap44xx_mmu_hwmod_class
= {
2086 static struct omap_mmu_dev_attr mmu_ipu_dev_attr
= {
2088 .da_end
= 0xfffff000,
2089 .nr_tlb_entries
= 32,
2092 static struct omap_hwmod omap44xx_mmu_ipu_hwmod
;
2093 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets
[] = {
2094 { .name
= "mmu_cache", .rst_shift
= 2 },
2097 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs
[] = {
2099 .pa_start
= 0x55082000,
2100 .pa_end
= 0x550820ff,
2101 .flags
= ADDR_TYPE_RT
,
2106 /* l3_main_2 -> mmu_ipu */
2107 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu
= {
2108 .master
= &omap44xx_l3_main_2_hwmod
,
2109 .slave
= &omap44xx_mmu_ipu_hwmod
,
2111 .addr
= omap44xx_mmu_ipu_addrs
,
2112 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2115 static struct omap_hwmod omap44xx_mmu_ipu_hwmod
= {
2117 .class = &omap44xx_mmu_hwmod_class
,
2118 .clkdm_name
= "ducati_clkdm",
2119 .rst_lines
= omap44xx_mmu_ipu_resets
,
2120 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_mmu_ipu_resets
),
2121 .main_clk
= "ducati_clk_mux_ck",
2124 .clkctrl_offs
= OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET
,
2125 .rstctrl_offs
= OMAP4_RM_DUCATI_RSTCTRL_OFFSET
,
2126 .context_offs
= OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET
,
2127 .modulemode
= MODULEMODE_HWCTRL
,
2130 .dev_attr
= &mmu_ipu_dev_attr
,
2135 static struct omap_mmu_dev_attr mmu_dsp_dev_attr
= {
2137 .da_end
= 0xfffff000,
2138 .nr_tlb_entries
= 32,
2141 static struct omap_hwmod omap44xx_mmu_dsp_hwmod
;
2142 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets
[] = {
2143 { .name
= "mmu_cache", .rst_shift
= 1 },
2146 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs
[] = {
2148 .pa_start
= 0x4a066000,
2149 .pa_end
= 0x4a0660ff,
2150 .flags
= ADDR_TYPE_RT
,
2156 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp
= {
2157 .master
= &omap44xx_l4_cfg_hwmod
,
2158 .slave
= &omap44xx_mmu_dsp_hwmod
,
2160 .addr
= omap44xx_mmu_dsp_addrs
,
2161 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2164 static struct omap_hwmod omap44xx_mmu_dsp_hwmod
= {
2166 .class = &omap44xx_mmu_hwmod_class
,
2167 .clkdm_name
= "tesla_clkdm",
2168 .rst_lines
= omap44xx_mmu_dsp_resets
,
2169 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_mmu_dsp_resets
),
2170 .main_clk
= "dpll_iva_m4x2_ck",
2173 .clkctrl_offs
= OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET
,
2174 .rstctrl_offs
= OMAP4_RM_TESLA_RSTCTRL_OFFSET
,
2175 .context_offs
= OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET
,
2176 .modulemode
= MODULEMODE_HWCTRL
,
2179 .dev_attr
= &mmu_dsp_dev_attr
,
2187 static struct omap_hwmod_class omap44xx_mpu_hwmod_class
= {
2192 static struct omap_hwmod omap44xx_mpu_hwmod
= {
2194 .class = &omap44xx_mpu_hwmod_class
,
2195 .clkdm_name
= "mpuss_clkdm",
2196 .flags
= HWMOD_INIT_NO_IDLE
,
2197 .main_clk
= "dpll_mpu_m2_ck",
2200 .clkctrl_offs
= OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET
,
2201 .context_offs
= OMAP4_RM_MPU_MPU_CONTEXT_OFFSET
,
2208 * top-level core on-chip ram
2211 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class
= {
2216 static struct omap_hwmod omap44xx_ocmc_ram_hwmod
= {
2218 .class = &omap44xx_ocmc_ram_hwmod_class
,
2219 .clkdm_name
= "l3_2_clkdm",
2222 .clkctrl_offs
= OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET
,
2223 .context_offs
= OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET
,
2230 * bridge to transform ocp interface protocol to scp (serial control port)
2234 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc
= {
2236 .sysc_offs
= 0x0010,
2237 .syss_offs
= 0x0014,
2238 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
2239 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
2240 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2241 .sysc_fields
= &omap_hwmod_sysc_type1
,
2244 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class
= {
2246 .sysc
= &omap44xx_ocp2scp_sysc
,
2249 /* ocp2scp_usb_phy */
2250 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod
= {
2251 .name
= "ocp2scp_usb_phy",
2252 .class = &omap44xx_ocp2scp_hwmod_class
,
2253 .clkdm_name
= "l3_init_clkdm",
2255 * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2256 * block as an "optional clock," and normally should never be
2257 * specified as the main_clk for an OMAP IP block. However it
2258 * turns out that this clock is actually the main clock for
2259 * the ocp2scp_usb_phy IP block:
2260 * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2261 * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2262 * to be the best workaround.
2264 .main_clk
= "ocp2scp_usb_phy_phy_48m",
2267 .clkctrl_offs
= OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET
,
2268 .context_offs
= OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET
,
2269 .modulemode
= MODULEMODE_HWCTRL
,
2276 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2277 * + clock manager 1 (in always on power domain) + local prm in mpu
2280 static struct omap_hwmod_class omap44xx_prcm_hwmod_class
= {
2285 static struct omap_hwmod omap44xx_prcm_mpu_hwmod
= {
2287 .class = &omap44xx_prcm_hwmod_class
,
2288 .clkdm_name
= "l4_wkup_clkdm",
2289 .flags
= HWMOD_NO_IDLEST
,
2292 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2298 static struct omap_hwmod omap44xx_cm_core_aon_hwmod
= {
2299 .name
= "cm_core_aon",
2300 .class = &omap44xx_prcm_hwmod_class
,
2301 .flags
= HWMOD_NO_IDLEST
,
2304 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2310 static struct omap_hwmod omap44xx_cm_core_hwmod
= {
2312 .class = &omap44xx_prcm_hwmod_class
,
2313 .flags
= HWMOD_NO_IDLEST
,
2316 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2322 static struct omap_hwmod_rst_info omap44xx_prm_resets
[] = {
2323 { .name
= "rst_global_warm_sw", .rst_shift
= 0 },
2324 { .name
= "rst_global_cold_sw", .rst_shift
= 1 },
2327 static struct omap_hwmod omap44xx_prm_hwmod
= {
2329 .class = &omap44xx_prcm_hwmod_class
,
2330 .rst_lines
= omap44xx_prm_resets
,
2331 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_prm_resets
),
2336 * system clock and reset manager
2339 static struct omap_hwmod_class omap44xx_scrm_hwmod_class
= {
2344 static struct omap_hwmod omap44xx_scrm_hwmod
= {
2346 .class = &omap44xx_scrm_hwmod_class
,
2347 .clkdm_name
= "l4_wkup_clkdm",
2350 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2357 * shared level 2 memory interface
2360 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class
= {
2365 static struct omap_hwmod omap44xx_sl2if_hwmod
= {
2367 .class = &omap44xx_sl2if_hwmod_class
,
2368 .clkdm_name
= "ivahd_clkdm",
2371 .clkctrl_offs
= OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET
,
2372 .context_offs
= OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET
,
2373 .modulemode
= MODULEMODE_HWCTRL
,
2380 * bidirectional, multi-drop, multi-channel two-line serial interface between
2381 * the device and external components
2384 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc
= {
2386 .sysc_offs
= 0x0010,
2387 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
2388 SYSC_HAS_SOFTRESET
),
2389 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2391 .sysc_fields
= &omap_hwmod_sysc_type2
,
2394 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class
= {
2396 .sysc
= &omap44xx_slimbus_sysc
,
2400 static struct omap_hwmod_opt_clk slimbus1_opt_clks
[] = {
2401 { .role
= "fclk_1", .clk
= "slimbus1_fclk_1" },
2402 { .role
= "fclk_0", .clk
= "slimbus1_fclk_0" },
2403 { .role
= "fclk_2", .clk
= "slimbus1_fclk_2" },
2404 { .role
= "slimbus_clk", .clk
= "slimbus1_slimbus_clk" },
2407 static struct omap_hwmod omap44xx_slimbus1_hwmod
= {
2409 .class = &omap44xx_slimbus_hwmod_class
,
2410 .clkdm_name
= "abe_clkdm",
2413 .clkctrl_offs
= OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET
,
2414 .context_offs
= OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET
,
2415 .modulemode
= MODULEMODE_SWCTRL
,
2418 .opt_clks
= slimbus1_opt_clks
,
2419 .opt_clks_cnt
= ARRAY_SIZE(slimbus1_opt_clks
),
2423 static struct omap_hwmod_opt_clk slimbus2_opt_clks
[] = {
2424 { .role
= "fclk_1", .clk
= "slimbus2_fclk_1" },
2425 { .role
= "fclk_0", .clk
= "slimbus2_fclk_0" },
2426 { .role
= "slimbus_clk", .clk
= "slimbus2_slimbus_clk" },
2429 static struct omap_hwmod omap44xx_slimbus2_hwmod
= {
2431 .class = &omap44xx_slimbus_hwmod_class
,
2432 .clkdm_name
= "l4_per_clkdm",
2435 .clkctrl_offs
= OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET
,
2436 .context_offs
= OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET
,
2437 .modulemode
= MODULEMODE_SWCTRL
,
2440 .opt_clks
= slimbus2_opt_clks
,
2441 .opt_clks_cnt
= ARRAY_SIZE(slimbus2_opt_clks
),
2445 * 'smartreflex' class
2446 * smartreflex module (monitor silicon performance and outputs a measure of
2447 * performance error)
2450 /* The IP is not compliant to type1 / type2 scheme */
2451 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex
= {
2456 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc
= {
2457 .sysc_offs
= 0x0038,
2458 .sysc_flags
= (SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
),
2459 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2461 .sysc_fields
= &omap_hwmod_sysc_type_smartreflex
,
2464 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class
= {
2465 .name
= "smartreflex",
2466 .sysc
= &omap44xx_smartreflex_sysc
,
2470 /* smartreflex_core */
2471 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr
= {
2472 .sensor_voltdm_name
= "core",
2475 static struct omap_hwmod omap44xx_smartreflex_core_hwmod
= {
2476 .name
= "smartreflex_core",
2477 .class = &omap44xx_smartreflex_hwmod_class
,
2478 .clkdm_name
= "l4_ao_clkdm",
2480 .main_clk
= "smartreflex_core_fck",
2483 .clkctrl_offs
= OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET
,
2484 .context_offs
= OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET
,
2485 .modulemode
= MODULEMODE_SWCTRL
,
2488 .dev_attr
= &smartreflex_core_dev_attr
,
2491 /* smartreflex_iva */
2492 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr
= {
2493 .sensor_voltdm_name
= "iva",
2496 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod
= {
2497 .name
= "smartreflex_iva",
2498 .class = &omap44xx_smartreflex_hwmod_class
,
2499 .clkdm_name
= "l4_ao_clkdm",
2500 .main_clk
= "smartreflex_iva_fck",
2503 .clkctrl_offs
= OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET
,
2504 .context_offs
= OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET
,
2505 .modulemode
= MODULEMODE_SWCTRL
,
2508 .dev_attr
= &smartreflex_iva_dev_attr
,
2511 /* smartreflex_mpu */
2512 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr
= {
2513 .sensor_voltdm_name
= "mpu",
2516 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod
= {
2517 .name
= "smartreflex_mpu",
2518 .class = &omap44xx_smartreflex_hwmod_class
,
2519 .clkdm_name
= "l4_ao_clkdm",
2520 .main_clk
= "smartreflex_mpu_fck",
2523 .clkctrl_offs
= OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET
,
2524 .context_offs
= OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET
,
2525 .modulemode
= MODULEMODE_SWCTRL
,
2528 .dev_attr
= &smartreflex_mpu_dev_attr
,
2533 * spinlock provides hardware assistance for synchronizing the processes
2534 * running on multiple processors
2537 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc
= {
2539 .sysc_offs
= 0x0010,
2540 .syss_offs
= 0x0014,
2541 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
2542 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
2543 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
2544 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2545 .sysc_fields
= &omap_hwmod_sysc_type1
,
2548 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class
= {
2550 .sysc
= &omap44xx_spinlock_sysc
,
2554 static struct omap_hwmod omap44xx_spinlock_hwmod
= {
2556 .class = &omap44xx_spinlock_hwmod_class
,
2557 .clkdm_name
= "l4_cfg_clkdm",
2560 .clkctrl_offs
= OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET
,
2561 .context_offs
= OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET
,
2568 * general purpose timer module with accurate 1ms tick
2569 * This class contains several variants: ['timer_1ms', 'timer']
2572 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc
= {
2574 .sysc_offs
= 0x0010,
2575 .syss_offs
= 0x0014,
2576 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
2577 SYSC_HAS_EMUFREE
| SYSC_HAS_ENAWAKEUP
|
2578 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
2579 SYSS_HAS_RESET_STATUS
),
2580 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2581 .clockact
= CLOCKACT_TEST_ICLK
,
2582 .sysc_fields
= &omap_hwmod_sysc_type1
,
2585 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class
= {
2587 .sysc
= &omap44xx_timer_1ms_sysc
,
2590 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc
= {
2592 .sysc_offs
= 0x0010,
2593 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2594 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2595 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2597 .sysc_fields
= &omap_hwmod_sysc_type2
,
2600 static struct omap_hwmod_class omap44xx_timer_hwmod_class
= {
2602 .sysc
= &omap44xx_timer_sysc
,
2605 /* always-on timers dev attribute */
2606 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr
= {
2607 .timer_capability
= OMAP_TIMER_ALWON
,
2610 /* pwm timers dev attribute */
2611 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr
= {
2612 .timer_capability
= OMAP_TIMER_HAS_PWM
,
2615 /* timers with DSP interrupt dev attribute */
2616 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr
= {
2617 .timer_capability
= OMAP_TIMER_HAS_DSP_IRQ
,
2620 /* pwm timers with DSP interrupt dev attribute */
2621 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr
= {
2622 .timer_capability
= OMAP_TIMER_HAS_DSP_IRQ
| OMAP_TIMER_HAS_PWM
,
2626 static struct omap_hwmod omap44xx_timer1_hwmod
= {
2628 .class = &omap44xx_timer_1ms_hwmod_class
,
2629 .clkdm_name
= "l4_wkup_clkdm",
2630 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
2631 .main_clk
= "dmt1_clk_mux",
2634 .clkctrl_offs
= OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET
,
2635 .context_offs
= OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET
,
2636 .modulemode
= MODULEMODE_SWCTRL
,
2639 .dev_attr
= &capability_alwon_dev_attr
,
2643 static struct omap_hwmod omap44xx_timer2_hwmod
= {
2645 .class = &omap44xx_timer_1ms_hwmod_class
,
2646 .clkdm_name
= "l4_per_clkdm",
2647 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
2648 .main_clk
= "cm2_dm2_mux",
2651 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET
,
2652 .context_offs
= OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET
,
2653 .modulemode
= MODULEMODE_SWCTRL
,
2659 static struct omap_hwmod omap44xx_timer3_hwmod
= {
2661 .class = &omap44xx_timer_hwmod_class
,
2662 .clkdm_name
= "l4_per_clkdm",
2663 .main_clk
= "cm2_dm3_mux",
2666 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET
,
2667 .context_offs
= OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET
,
2668 .modulemode
= MODULEMODE_SWCTRL
,
2674 static struct omap_hwmod omap44xx_timer4_hwmod
= {
2676 .class = &omap44xx_timer_hwmod_class
,
2677 .clkdm_name
= "l4_per_clkdm",
2678 .main_clk
= "cm2_dm4_mux",
2681 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET
,
2682 .context_offs
= OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET
,
2683 .modulemode
= MODULEMODE_SWCTRL
,
2689 static struct omap_hwmod omap44xx_timer5_hwmod
= {
2691 .class = &omap44xx_timer_hwmod_class
,
2692 .clkdm_name
= "abe_clkdm",
2693 .main_clk
= "timer5_sync_mux",
2696 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET
,
2697 .context_offs
= OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET
,
2698 .modulemode
= MODULEMODE_SWCTRL
,
2701 .dev_attr
= &capability_dsp_dev_attr
,
2705 static struct omap_hwmod omap44xx_timer6_hwmod
= {
2707 .class = &omap44xx_timer_hwmod_class
,
2708 .clkdm_name
= "abe_clkdm",
2709 .main_clk
= "timer6_sync_mux",
2712 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET
,
2713 .context_offs
= OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET
,
2714 .modulemode
= MODULEMODE_SWCTRL
,
2717 .dev_attr
= &capability_dsp_dev_attr
,
2721 static struct omap_hwmod omap44xx_timer7_hwmod
= {
2723 .class = &omap44xx_timer_hwmod_class
,
2724 .clkdm_name
= "abe_clkdm",
2725 .main_clk
= "timer7_sync_mux",
2728 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET
,
2729 .context_offs
= OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET
,
2730 .modulemode
= MODULEMODE_SWCTRL
,
2733 .dev_attr
= &capability_dsp_dev_attr
,
2737 static struct omap_hwmod omap44xx_timer8_hwmod
= {
2739 .class = &omap44xx_timer_hwmod_class
,
2740 .clkdm_name
= "abe_clkdm",
2741 .main_clk
= "timer8_sync_mux",
2744 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET
,
2745 .context_offs
= OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET
,
2746 .modulemode
= MODULEMODE_SWCTRL
,
2749 .dev_attr
= &capability_dsp_pwm_dev_attr
,
2753 static struct omap_hwmod omap44xx_timer9_hwmod
= {
2755 .class = &omap44xx_timer_hwmod_class
,
2756 .clkdm_name
= "l4_per_clkdm",
2757 .main_clk
= "cm2_dm9_mux",
2760 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET
,
2761 .context_offs
= OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET
,
2762 .modulemode
= MODULEMODE_SWCTRL
,
2765 .dev_attr
= &capability_pwm_dev_attr
,
2769 static struct omap_hwmod omap44xx_timer10_hwmod
= {
2771 .class = &omap44xx_timer_1ms_hwmod_class
,
2772 .clkdm_name
= "l4_per_clkdm",
2773 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
2774 .main_clk
= "cm2_dm10_mux",
2777 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET
,
2778 .context_offs
= OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET
,
2779 .modulemode
= MODULEMODE_SWCTRL
,
2782 .dev_attr
= &capability_pwm_dev_attr
,
2786 static struct omap_hwmod omap44xx_timer11_hwmod
= {
2788 .class = &omap44xx_timer_hwmod_class
,
2789 .clkdm_name
= "l4_per_clkdm",
2790 .main_clk
= "cm2_dm11_mux",
2793 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET
,
2794 .context_offs
= OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET
,
2795 .modulemode
= MODULEMODE_SWCTRL
,
2798 .dev_attr
= &capability_pwm_dev_attr
,
2803 * universal asynchronous receiver/transmitter (uart)
2806 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc
= {
2808 .sysc_offs
= 0x0054,
2809 .syss_offs
= 0x0058,
2810 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
2811 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
2812 SYSS_HAS_RESET_STATUS
),
2813 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2815 .sysc_fields
= &omap_hwmod_sysc_type1
,
2818 static struct omap_hwmod_class omap44xx_uart_hwmod_class
= {
2820 .sysc
= &omap44xx_uart_sysc
,
2824 static struct omap_hwmod omap44xx_uart1_hwmod
= {
2826 .class = &omap44xx_uart_hwmod_class
,
2827 .clkdm_name
= "l4_per_clkdm",
2828 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2829 .main_clk
= "func_48m_fclk",
2832 .clkctrl_offs
= OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET
,
2833 .context_offs
= OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET
,
2834 .modulemode
= MODULEMODE_SWCTRL
,
2840 static struct omap_hwmod omap44xx_uart2_hwmod
= {
2842 .class = &omap44xx_uart_hwmod_class
,
2843 .clkdm_name
= "l4_per_clkdm",
2844 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2845 .main_clk
= "func_48m_fclk",
2848 .clkctrl_offs
= OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET
,
2849 .context_offs
= OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET
,
2850 .modulemode
= MODULEMODE_SWCTRL
,
2856 static struct omap_hwmod omap44xx_uart3_hwmod
= {
2858 .class = &omap44xx_uart_hwmod_class
,
2859 .clkdm_name
= "l4_per_clkdm",
2860 .flags
= DEBUG_OMAP4UART3_FLAGS
| HWMOD_SWSUP_SIDLE_ACT
,
2861 .main_clk
= "func_48m_fclk",
2864 .clkctrl_offs
= OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET
,
2865 .context_offs
= OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET
,
2866 .modulemode
= MODULEMODE_SWCTRL
,
2872 static struct omap_hwmod omap44xx_uart4_hwmod
= {
2874 .class = &omap44xx_uart_hwmod_class
,
2875 .clkdm_name
= "l4_per_clkdm",
2876 .flags
= DEBUG_OMAP4UART4_FLAGS
| HWMOD_SWSUP_SIDLE_ACT
,
2877 .main_clk
= "func_48m_fclk",
2880 .clkctrl_offs
= OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET
,
2881 .context_offs
= OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET
,
2882 .modulemode
= MODULEMODE_SWCTRL
,
2888 * 'usb_host_fs' class
2889 * full-speed usb host controller
2892 /* The IP is not compliant to type1 / type2 scheme */
2893 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs
= {
2899 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc
= {
2901 .sysc_offs
= 0x0210,
2902 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
2903 SYSC_HAS_SOFTRESET
),
2904 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2906 .sysc_fields
= &omap_hwmod_sysc_type_usb_host_fs
,
2909 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class
= {
2910 .name
= "usb_host_fs",
2911 .sysc
= &omap44xx_usb_host_fs_sysc
,
2915 static struct omap_hwmod omap44xx_usb_host_fs_hwmod
= {
2916 .name
= "usb_host_fs",
2917 .class = &omap44xx_usb_host_fs_hwmod_class
,
2918 .clkdm_name
= "l3_init_clkdm",
2919 .main_clk
= "usb_host_fs_fck",
2922 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET
,
2923 .context_offs
= OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET
,
2924 .modulemode
= MODULEMODE_SWCTRL
,
2930 * 'usb_host_hs' class
2931 * high-speed multi-port usb host controller
2934 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc
= {
2936 .sysc_offs
= 0x0010,
2937 .syss_offs
= 0x0014,
2938 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
2939 SYSC_HAS_SOFTRESET
| SYSC_HAS_RESET_STATUS
),
2940 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2941 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
2942 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
2943 .sysc_fields
= &omap_hwmod_sysc_type2
,
2946 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class
= {
2947 .name
= "usb_host_hs",
2948 .sysc
= &omap44xx_usb_host_hs_sysc
,
2952 static struct omap_hwmod omap44xx_usb_host_hs_hwmod
= {
2953 .name
= "usb_host_hs",
2954 .class = &omap44xx_usb_host_hs_hwmod_class
,
2955 .clkdm_name
= "l3_init_clkdm",
2956 .main_clk
= "usb_host_hs_fck",
2959 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET
,
2960 .context_offs
= OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET
,
2961 .modulemode
= MODULEMODE_SWCTRL
,
2966 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2970 * In the following configuration :
2971 * - USBHOST module is set to smart-idle mode
2972 * - PRCM asserts idle_req to the USBHOST module ( This typically
2973 * happens when the system is going to a low power mode : all ports
2974 * have been suspended, the master part of the USBHOST module has
2975 * entered the standby state, and SW has cut the functional clocks)
2976 * - an USBHOST interrupt occurs before the module is able to answer
2977 * idle_ack, typically a remote wakeup IRQ.
2978 * Then the USB HOST module will enter a deadlock situation where it
2979 * is no more accessible nor functional.
2982 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2986 * Errata: USB host EHCI may stall when entering smart-standby mode
2990 * When the USBHOST module is set to smart-standby mode, and when it is
2991 * ready to enter the standby state (i.e. all ports are suspended and
2992 * all attached devices are in suspend mode), then it can wrongly assert
2993 * the Mstandby signal too early while there are still some residual OCP
2994 * transactions ongoing. If this condition occurs, the internal state
2995 * machine may go to an undefined state and the USB link may be stuck
2996 * upon the next resume.
2999 * Don't use smart standby; use only force standby,
3000 * hence HWMOD_SWSUP_MSTANDBY
3003 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
3007 * 'usb_otg_hs' class
3008 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3011 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc
= {
3013 .sysc_offs
= 0x0404,
3014 .syss_offs
= 0x0408,
3015 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
3016 SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3017 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3018 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3019 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
3021 .sysc_fields
= &omap_hwmod_sysc_type1
,
3024 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class
= {
3025 .name
= "usb_otg_hs",
3026 .sysc
= &omap44xx_usb_otg_hs_sysc
,
3030 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks
[] = {
3031 { .role
= "xclk", .clk
= "usb_otg_hs_xclk" },
3034 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod
= {
3035 .name
= "usb_otg_hs",
3036 .class = &omap44xx_usb_otg_hs_hwmod_class
,
3037 .clkdm_name
= "l3_init_clkdm",
3038 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
3039 .main_clk
= "usb_otg_hs_ick",
3042 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET
,
3043 .context_offs
= OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET
,
3044 .modulemode
= MODULEMODE_HWCTRL
,
3047 .opt_clks
= usb_otg_hs_opt_clks
,
3048 .opt_clks_cnt
= ARRAY_SIZE(usb_otg_hs_opt_clks
),
3052 * 'usb_tll_hs' class
3053 * usb_tll_hs module is the adapter on the usb_host_hs ports
3056 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc
= {
3058 .sysc_offs
= 0x0010,
3059 .syss_offs
= 0x0014,
3060 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
3061 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
3063 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
3064 .sysc_fields
= &omap_hwmod_sysc_type1
,
3067 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class
= {
3068 .name
= "usb_tll_hs",
3069 .sysc
= &omap44xx_usb_tll_hs_sysc
,
3072 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod
= {
3073 .name
= "usb_tll_hs",
3074 .class = &omap44xx_usb_tll_hs_hwmod_class
,
3075 .clkdm_name
= "l3_init_clkdm",
3076 .main_clk
= "usb_tll_hs_ick",
3079 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET
,
3080 .context_offs
= OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET
,
3081 .modulemode
= MODULEMODE_HWCTRL
,
3088 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3089 * overflow condition
3092 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc
= {
3094 .sysc_offs
= 0x0010,
3095 .syss_offs
= 0x0014,
3096 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
3097 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3098 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3100 .sysc_fields
= &omap_hwmod_sysc_type1
,
3103 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class
= {
3105 .sysc
= &omap44xx_wd_timer_sysc
,
3106 .pre_shutdown
= &omap2_wd_timer_disable
,
3107 .reset
= &omap2_wd_timer_reset
,
3111 static struct omap_hwmod omap44xx_wd_timer2_hwmod
= {
3112 .name
= "wd_timer2",
3113 .class = &omap44xx_wd_timer_hwmod_class
,
3114 .clkdm_name
= "l4_wkup_clkdm",
3115 .main_clk
= "sys_32k_ck",
3118 .clkctrl_offs
= OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET
,
3119 .context_offs
= OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET
,
3120 .modulemode
= MODULEMODE_SWCTRL
,
3126 static struct omap_hwmod omap44xx_wd_timer3_hwmod
= {
3127 .name
= "wd_timer3",
3128 .class = &omap44xx_wd_timer_hwmod_class
,
3129 .clkdm_name
= "abe_clkdm",
3130 .main_clk
= "sys_32k_ck",
3133 .clkctrl_offs
= OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET
,
3134 .context_offs
= OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET
,
3135 .modulemode
= MODULEMODE_SWCTRL
,
3145 /* l3_main_1 -> dmm */
3146 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm
= {
3147 .master
= &omap44xx_l3_main_1_hwmod
,
3148 .slave
= &omap44xx_dmm_hwmod
,
3150 .user
= OCP_USER_SDMA
,
3154 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm
= {
3155 .master
= &omap44xx_mpu_hwmod
,
3156 .slave
= &omap44xx_dmm_hwmod
,
3158 .user
= OCP_USER_MPU
,
3161 /* iva -> l3_instr */
3162 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr
= {
3163 .master
= &omap44xx_iva_hwmod
,
3164 .slave
= &omap44xx_l3_instr_hwmod
,
3166 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3169 /* l3_main_3 -> l3_instr */
3170 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr
= {
3171 .master
= &omap44xx_l3_main_3_hwmod
,
3172 .slave
= &omap44xx_l3_instr_hwmod
,
3174 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3177 /* ocp_wp_noc -> l3_instr */
3178 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr
= {
3179 .master
= &omap44xx_ocp_wp_noc_hwmod
,
3180 .slave
= &omap44xx_l3_instr_hwmod
,
3182 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3185 /* dsp -> l3_main_1 */
3186 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1
= {
3187 .master
= &omap44xx_dsp_hwmod
,
3188 .slave
= &omap44xx_l3_main_1_hwmod
,
3190 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3193 /* dss -> l3_main_1 */
3194 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1
= {
3195 .master
= &omap44xx_dss_hwmod
,
3196 .slave
= &omap44xx_l3_main_1_hwmod
,
3198 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3201 /* l3_main_2 -> l3_main_1 */
3202 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1
= {
3203 .master
= &omap44xx_l3_main_2_hwmod
,
3204 .slave
= &omap44xx_l3_main_1_hwmod
,
3206 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3209 /* l4_cfg -> l3_main_1 */
3210 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1
= {
3211 .master
= &omap44xx_l4_cfg_hwmod
,
3212 .slave
= &omap44xx_l3_main_1_hwmod
,
3214 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3217 /* mmc1 -> l3_main_1 */
3218 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1
= {
3219 .master
= &omap44xx_mmc1_hwmod
,
3220 .slave
= &omap44xx_l3_main_1_hwmod
,
3222 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3225 /* mmc2 -> l3_main_1 */
3226 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1
= {
3227 .master
= &omap44xx_mmc2_hwmod
,
3228 .slave
= &omap44xx_l3_main_1_hwmod
,
3230 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3233 /* mpu -> l3_main_1 */
3234 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1
= {
3235 .master
= &omap44xx_mpu_hwmod
,
3236 .slave
= &omap44xx_l3_main_1_hwmod
,
3238 .user
= OCP_USER_MPU
,
3241 /* debugss -> l3_main_2 */
3242 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2
= {
3243 .master
= &omap44xx_debugss_hwmod
,
3244 .slave
= &omap44xx_l3_main_2_hwmod
,
3245 .clk
= "dbgclk_mux_ck",
3246 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3249 /* dma_system -> l3_main_2 */
3250 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2
= {
3251 .master
= &omap44xx_dma_system_hwmod
,
3252 .slave
= &omap44xx_l3_main_2_hwmod
,
3254 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3257 /* fdif -> l3_main_2 */
3258 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2
= {
3259 .master
= &omap44xx_fdif_hwmod
,
3260 .slave
= &omap44xx_l3_main_2_hwmod
,
3262 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3265 /* gpu -> l3_main_2 */
3266 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2
= {
3267 .master
= &omap44xx_gpu_hwmod
,
3268 .slave
= &omap44xx_l3_main_2_hwmod
,
3270 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3273 /* hsi -> l3_main_2 */
3274 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2
= {
3275 .master
= &omap44xx_hsi_hwmod
,
3276 .slave
= &omap44xx_l3_main_2_hwmod
,
3278 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3281 /* ipu -> l3_main_2 */
3282 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2
= {
3283 .master
= &omap44xx_ipu_hwmod
,
3284 .slave
= &omap44xx_l3_main_2_hwmod
,
3286 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3289 /* iss -> l3_main_2 */
3290 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2
= {
3291 .master
= &omap44xx_iss_hwmod
,
3292 .slave
= &omap44xx_l3_main_2_hwmod
,
3294 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3297 /* iva -> l3_main_2 */
3298 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2
= {
3299 .master
= &omap44xx_iva_hwmod
,
3300 .slave
= &omap44xx_l3_main_2_hwmod
,
3302 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3305 /* l3_main_1 -> l3_main_2 */
3306 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2
= {
3307 .master
= &omap44xx_l3_main_1_hwmod
,
3308 .slave
= &omap44xx_l3_main_2_hwmod
,
3310 .user
= OCP_USER_MPU
,
3313 /* l4_cfg -> l3_main_2 */
3314 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2
= {
3315 .master
= &omap44xx_l4_cfg_hwmod
,
3316 .slave
= &omap44xx_l3_main_2_hwmod
,
3318 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3321 /* usb_host_fs -> l3_main_2 */
3322 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2
= {
3323 .master
= &omap44xx_usb_host_fs_hwmod
,
3324 .slave
= &omap44xx_l3_main_2_hwmod
,
3326 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3329 /* usb_host_hs -> l3_main_2 */
3330 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2
= {
3331 .master
= &omap44xx_usb_host_hs_hwmod
,
3332 .slave
= &omap44xx_l3_main_2_hwmod
,
3334 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3337 /* usb_otg_hs -> l3_main_2 */
3338 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2
= {
3339 .master
= &omap44xx_usb_otg_hs_hwmod
,
3340 .slave
= &omap44xx_l3_main_2_hwmod
,
3342 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3345 /* l3_main_1 -> l3_main_3 */
3346 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3
= {
3347 .master
= &omap44xx_l3_main_1_hwmod
,
3348 .slave
= &omap44xx_l3_main_3_hwmod
,
3350 .user
= OCP_USER_MPU
,
3353 /* l3_main_2 -> l3_main_3 */
3354 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3
= {
3355 .master
= &omap44xx_l3_main_2_hwmod
,
3356 .slave
= &omap44xx_l3_main_3_hwmod
,
3358 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3361 /* l4_cfg -> l3_main_3 */
3362 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3
= {
3363 .master
= &omap44xx_l4_cfg_hwmod
,
3364 .slave
= &omap44xx_l3_main_3_hwmod
,
3366 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3369 /* aess -> l4_abe */
3370 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe
= {
3371 .master
= &omap44xx_aess_hwmod
,
3372 .slave
= &omap44xx_l4_abe_hwmod
,
3373 .clk
= "ocp_abe_iclk",
3374 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3378 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe
= {
3379 .master
= &omap44xx_dsp_hwmod
,
3380 .slave
= &omap44xx_l4_abe_hwmod
,
3381 .clk
= "ocp_abe_iclk",
3382 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3385 /* l3_main_1 -> l4_abe */
3386 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe
= {
3387 .master
= &omap44xx_l3_main_1_hwmod
,
3388 .slave
= &omap44xx_l4_abe_hwmod
,
3390 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3394 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe
= {
3395 .master
= &omap44xx_mpu_hwmod
,
3396 .slave
= &omap44xx_l4_abe_hwmod
,
3397 .clk
= "ocp_abe_iclk",
3398 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3401 /* l3_main_1 -> l4_cfg */
3402 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg
= {
3403 .master
= &omap44xx_l3_main_1_hwmod
,
3404 .slave
= &omap44xx_l4_cfg_hwmod
,
3406 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3409 /* l3_main_2 -> l4_per */
3410 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per
= {
3411 .master
= &omap44xx_l3_main_2_hwmod
,
3412 .slave
= &omap44xx_l4_per_hwmod
,
3414 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3417 /* l4_cfg -> l4_wkup */
3418 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup
= {
3419 .master
= &omap44xx_l4_cfg_hwmod
,
3420 .slave
= &omap44xx_l4_wkup_hwmod
,
3422 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3425 /* mpu -> mpu_private */
3426 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private
= {
3427 .master
= &omap44xx_mpu_hwmod
,
3428 .slave
= &omap44xx_mpu_private_hwmod
,
3430 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3433 /* l4_cfg -> ocp_wp_noc */
3434 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc
= {
3435 .master
= &omap44xx_l4_cfg_hwmod
,
3436 .slave
= &omap44xx_ocp_wp_noc_hwmod
,
3438 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3441 static struct omap_hwmod_addr_space omap44xx_aess_addrs
[] = {
3444 .pa_start
= 0x40180000,
3445 .pa_end
= 0x4018ffff
3449 .pa_start
= 0x401a0000,
3450 .pa_end
= 0x401a1fff
3454 .pa_start
= 0x401c0000,
3455 .pa_end
= 0x401c5fff
3459 .pa_start
= 0x401e0000,
3460 .pa_end
= 0x401e1fff
3464 .pa_start
= 0x401f1000,
3465 .pa_end
= 0x401f13ff,
3466 .flags
= ADDR_TYPE_RT
3471 /* l4_abe -> aess */
3472 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess
= {
3473 .master
= &omap44xx_l4_abe_hwmod
,
3474 .slave
= &omap44xx_aess_hwmod
,
3475 .clk
= "ocp_abe_iclk",
3476 .addr
= omap44xx_aess_addrs
,
3477 .user
= OCP_USER_MPU
,
3480 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs
[] = {
3483 .pa_start
= 0x49080000,
3484 .pa_end
= 0x4908ffff
3488 .pa_start
= 0x490a0000,
3489 .pa_end
= 0x490a1fff
3493 .pa_start
= 0x490c0000,
3494 .pa_end
= 0x490c5fff
3498 .pa_start
= 0x490e0000,
3499 .pa_end
= 0x490e1fff
3503 .pa_start
= 0x490f1000,
3504 .pa_end
= 0x490f13ff,
3505 .flags
= ADDR_TYPE_RT
3510 /* l4_abe -> aess (dma) */
3511 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma
= {
3512 .master
= &omap44xx_l4_abe_hwmod
,
3513 .slave
= &omap44xx_aess_hwmod
,
3514 .clk
= "ocp_abe_iclk",
3515 .addr
= omap44xx_aess_dma_addrs
,
3516 .user
= OCP_USER_SDMA
,
3519 /* l3_main_2 -> c2c */
3520 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c
= {
3521 .master
= &omap44xx_l3_main_2_hwmod
,
3522 .slave
= &omap44xx_c2c_hwmod
,
3524 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3527 /* l4_wkup -> counter_32k */
3528 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k
= {
3529 .master
= &omap44xx_l4_wkup_hwmod
,
3530 .slave
= &omap44xx_counter_32k_hwmod
,
3531 .clk
= "l4_wkup_clk_mux_ck",
3532 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3535 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs
[] = {
3537 .pa_start
= 0x4a002000,
3538 .pa_end
= 0x4a0027ff,
3539 .flags
= ADDR_TYPE_RT
3544 /* l4_cfg -> ctrl_module_core */
3545 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core
= {
3546 .master
= &omap44xx_l4_cfg_hwmod
,
3547 .slave
= &omap44xx_ctrl_module_core_hwmod
,
3549 .addr
= omap44xx_ctrl_module_core_addrs
,
3550 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3553 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs
[] = {
3555 .pa_start
= 0x4a100000,
3556 .pa_end
= 0x4a1007ff,
3557 .flags
= ADDR_TYPE_RT
3562 /* l4_cfg -> ctrl_module_pad_core */
3563 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core
= {
3564 .master
= &omap44xx_l4_cfg_hwmod
,
3565 .slave
= &omap44xx_ctrl_module_pad_core_hwmod
,
3567 .addr
= omap44xx_ctrl_module_pad_core_addrs
,
3568 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3571 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs
[] = {
3573 .pa_start
= 0x4a30c000,
3574 .pa_end
= 0x4a30c7ff,
3575 .flags
= ADDR_TYPE_RT
3580 /* l4_wkup -> ctrl_module_wkup */
3581 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup
= {
3582 .master
= &omap44xx_l4_wkup_hwmod
,
3583 .slave
= &omap44xx_ctrl_module_wkup_hwmod
,
3584 .clk
= "l4_wkup_clk_mux_ck",
3585 .addr
= omap44xx_ctrl_module_wkup_addrs
,
3586 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3589 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs
[] = {
3591 .pa_start
= 0x4a31e000,
3592 .pa_end
= 0x4a31e7ff,
3593 .flags
= ADDR_TYPE_RT
3598 /* l4_wkup -> ctrl_module_pad_wkup */
3599 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup
= {
3600 .master
= &omap44xx_l4_wkup_hwmod
,
3601 .slave
= &omap44xx_ctrl_module_pad_wkup_hwmod
,
3602 .clk
= "l4_wkup_clk_mux_ck",
3603 .addr
= omap44xx_ctrl_module_pad_wkup_addrs
,
3604 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3607 /* l3_instr -> debugss */
3608 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss
= {
3609 .master
= &omap44xx_l3_instr_hwmod
,
3610 .slave
= &omap44xx_debugss_hwmod
,
3612 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3615 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs
[] = {
3617 .pa_start
= 0x4a056000,
3618 .pa_end
= 0x4a056fff,
3619 .flags
= ADDR_TYPE_RT
3624 /* l4_cfg -> dma_system */
3625 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system
= {
3626 .master
= &omap44xx_l4_cfg_hwmod
,
3627 .slave
= &omap44xx_dma_system_hwmod
,
3629 .addr
= omap44xx_dma_system_addrs
,
3630 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3633 /* l4_abe -> dmic */
3634 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic
= {
3635 .master
= &omap44xx_l4_abe_hwmod
,
3636 .slave
= &omap44xx_dmic_hwmod
,
3637 .clk
= "ocp_abe_iclk",
3638 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3642 static struct omap_hwmod_ocp_if omap44xx_dsp__iva
= {
3643 .master
= &omap44xx_dsp_hwmod
,
3644 .slave
= &omap44xx_iva_hwmod
,
3645 .clk
= "dpll_iva_m5x2_ck",
3646 .user
= OCP_USER_DSP
,
3650 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if
= {
3651 .master
= &omap44xx_dsp_hwmod
,
3652 .slave
= &omap44xx_sl2if_hwmod
,
3653 .clk
= "dpll_iva_m5x2_ck",
3654 .user
= OCP_USER_DSP
,
3658 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp
= {
3659 .master
= &omap44xx_l4_cfg_hwmod
,
3660 .slave
= &omap44xx_dsp_hwmod
,
3662 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3665 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs
[] = {
3667 .pa_start
= 0x58000000,
3668 .pa_end
= 0x5800007f,
3669 .flags
= ADDR_TYPE_RT
3674 /* l3_main_2 -> dss */
3675 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss
= {
3676 .master
= &omap44xx_l3_main_2_hwmod
,
3677 .slave
= &omap44xx_dss_hwmod
,
3679 .addr
= omap44xx_dss_dma_addrs
,
3680 .user
= OCP_USER_SDMA
,
3683 static struct omap_hwmod_addr_space omap44xx_dss_addrs
[] = {
3685 .pa_start
= 0x48040000,
3686 .pa_end
= 0x4804007f,
3687 .flags
= ADDR_TYPE_RT
3693 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss
= {
3694 .master
= &omap44xx_l4_per_hwmod
,
3695 .slave
= &omap44xx_dss_hwmod
,
3697 .addr
= omap44xx_dss_addrs
,
3698 .user
= OCP_USER_MPU
,
3701 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs
[] = {
3703 .pa_start
= 0x58001000,
3704 .pa_end
= 0x58001fff,
3705 .flags
= ADDR_TYPE_RT
3710 /* l3_main_2 -> dss_dispc */
3711 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc
= {
3712 .master
= &omap44xx_l3_main_2_hwmod
,
3713 .slave
= &omap44xx_dss_dispc_hwmod
,
3715 .addr
= omap44xx_dss_dispc_dma_addrs
,
3716 .user
= OCP_USER_SDMA
,
3719 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs
[] = {
3721 .pa_start
= 0x48041000,
3722 .pa_end
= 0x48041fff,
3723 .flags
= ADDR_TYPE_RT
3728 /* l4_per -> dss_dispc */
3729 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc
= {
3730 .master
= &omap44xx_l4_per_hwmod
,
3731 .slave
= &omap44xx_dss_dispc_hwmod
,
3733 .addr
= omap44xx_dss_dispc_addrs
,
3734 .user
= OCP_USER_MPU
,
3737 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs
[] = {
3739 .pa_start
= 0x58004000,
3740 .pa_end
= 0x580041ff,
3741 .flags
= ADDR_TYPE_RT
3746 /* l3_main_2 -> dss_dsi1 */
3747 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1
= {
3748 .master
= &omap44xx_l3_main_2_hwmod
,
3749 .slave
= &omap44xx_dss_dsi1_hwmod
,
3751 .addr
= omap44xx_dss_dsi1_dma_addrs
,
3752 .user
= OCP_USER_SDMA
,
3755 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs
[] = {
3757 .pa_start
= 0x48044000,
3758 .pa_end
= 0x480441ff,
3759 .flags
= ADDR_TYPE_RT
3764 /* l4_per -> dss_dsi1 */
3765 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1
= {
3766 .master
= &omap44xx_l4_per_hwmod
,
3767 .slave
= &omap44xx_dss_dsi1_hwmod
,
3769 .addr
= omap44xx_dss_dsi1_addrs
,
3770 .user
= OCP_USER_MPU
,
3773 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs
[] = {
3775 .pa_start
= 0x58005000,
3776 .pa_end
= 0x580051ff,
3777 .flags
= ADDR_TYPE_RT
3782 /* l3_main_2 -> dss_dsi2 */
3783 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2
= {
3784 .master
= &omap44xx_l3_main_2_hwmod
,
3785 .slave
= &omap44xx_dss_dsi2_hwmod
,
3787 .addr
= omap44xx_dss_dsi2_dma_addrs
,
3788 .user
= OCP_USER_SDMA
,
3791 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs
[] = {
3793 .pa_start
= 0x48045000,
3794 .pa_end
= 0x480451ff,
3795 .flags
= ADDR_TYPE_RT
3800 /* l4_per -> dss_dsi2 */
3801 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2
= {
3802 .master
= &omap44xx_l4_per_hwmod
,
3803 .slave
= &omap44xx_dss_dsi2_hwmod
,
3805 .addr
= omap44xx_dss_dsi2_addrs
,
3806 .user
= OCP_USER_MPU
,
3809 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs
[] = {
3811 .pa_start
= 0x58006000,
3812 .pa_end
= 0x58006fff,
3813 .flags
= ADDR_TYPE_RT
3818 /* l3_main_2 -> dss_hdmi */
3819 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi
= {
3820 .master
= &omap44xx_l3_main_2_hwmod
,
3821 .slave
= &omap44xx_dss_hdmi_hwmod
,
3823 .addr
= omap44xx_dss_hdmi_dma_addrs
,
3824 .user
= OCP_USER_SDMA
,
3827 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs
[] = {
3829 .pa_start
= 0x48046000,
3830 .pa_end
= 0x48046fff,
3831 .flags
= ADDR_TYPE_RT
3836 /* l4_per -> dss_hdmi */
3837 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi
= {
3838 .master
= &omap44xx_l4_per_hwmod
,
3839 .slave
= &omap44xx_dss_hdmi_hwmod
,
3841 .addr
= omap44xx_dss_hdmi_addrs
,
3842 .user
= OCP_USER_MPU
,
3845 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs
[] = {
3847 .pa_start
= 0x58002000,
3848 .pa_end
= 0x580020ff,
3849 .flags
= ADDR_TYPE_RT
3854 /* l3_main_2 -> dss_rfbi */
3855 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi
= {
3856 .master
= &omap44xx_l3_main_2_hwmod
,
3857 .slave
= &omap44xx_dss_rfbi_hwmod
,
3859 .addr
= omap44xx_dss_rfbi_dma_addrs
,
3860 .user
= OCP_USER_SDMA
,
3863 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs
[] = {
3865 .pa_start
= 0x48042000,
3866 .pa_end
= 0x480420ff,
3867 .flags
= ADDR_TYPE_RT
3872 /* l4_per -> dss_rfbi */
3873 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi
= {
3874 .master
= &omap44xx_l4_per_hwmod
,
3875 .slave
= &omap44xx_dss_rfbi_hwmod
,
3877 .addr
= omap44xx_dss_rfbi_addrs
,
3878 .user
= OCP_USER_MPU
,
3881 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs
[] = {
3883 .pa_start
= 0x58003000,
3884 .pa_end
= 0x580030ff,
3885 .flags
= ADDR_TYPE_RT
3890 /* l3_main_2 -> dss_venc */
3891 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc
= {
3892 .master
= &omap44xx_l3_main_2_hwmod
,
3893 .slave
= &omap44xx_dss_venc_hwmod
,
3895 .addr
= omap44xx_dss_venc_dma_addrs
,
3896 .user
= OCP_USER_SDMA
,
3899 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs
[] = {
3901 .pa_start
= 0x48043000,
3902 .pa_end
= 0x480430ff,
3903 .flags
= ADDR_TYPE_RT
3908 /* l4_per -> dss_venc */
3909 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc
= {
3910 .master
= &omap44xx_l4_per_hwmod
,
3911 .slave
= &omap44xx_dss_venc_hwmod
,
3913 .addr
= omap44xx_dss_venc_addrs
,
3914 .user
= OCP_USER_MPU
,
3917 static struct omap_hwmod_addr_space omap44xx_elm_addrs
[] = {
3919 .pa_start
= 0x48078000,
3920 .pa_end
= 0x48078fff,
3921 .flags
= ADDR_TYPE_RT
3927 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm
= {
3928 .master
= &omap44xx_l4_per_hwmod
,
3929 .slave
= &omap44xx_elm_hwmod
,
3931 .addr
= omap44xx_elm_addrs
,
3932 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3935 static struct omap_hwmod_addr_space omap44xx_fdif_addrs
[] = {
3937 .pa_start
= 0x4a10a000,
3938 .pa_end
= 0x4a10a1ff,
3939 .flags
= ADDR_TYPE_RT
3944 /* l4_cfg -> fdif */
3945 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif
= {
3946 .master
= &omap44xx_l4_cfg_hwmod
,
3947 .slave
= &omap44xx_fdif_hwmod
,
3949 .addr
= omap44xx_fdif_addrs
,
3950 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3953 /* l4_wkup -> gpio1 */
3954 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1
= {
3955 .master
= &omap44xx_l4_wkup_hwmod
,
3956 .slave
= &omap44xx_gpio1_hwmod
,
3957 .clk
= "l4_wkup_clk_mux_ck",
3958 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3961 /* l4_per -> gpio2 */
3962 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2
= {
3963 .master
= &omap44xx_l4_per_hwmod
,
3964 .slave
= &omap44xx_gpio2_hwmod
,
3966 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3969 /* l4_per -> gpio3 */
3970 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3
= {
3971 .master
= &omap44xx_l4_per_hwmod
,
3972 .slave
= &omap44xx_gpio3_hwmod
,
3974 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3977 /* l4_per -> gpio4 */
3978 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4
= {
3979 .master
= &omap44xx_l4_per_hwmod
,
3980 .slave
= &omap44xx_gpio4_hwmod
,
3982 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3985 /* l4_per -> gpio5 */
3986 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5
= {
3987 .master
= &omap44xx_l4_per_hwmod
,
3988 .slave
= &omap44xx_gpio5_hwmod
,
3990 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3993 /* l4_per -> gpio6 */
3994 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6
= {
3995 .master
= &omap44xx_l4_per_hwmod
,
3996 .slave
= &omap44xx_gpio6_hwmod
,
3998 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4001 /* l3_main_2 -> gpmc */
4002 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc
= {
4003 .master
= &omap44xx_l3_main_2_hwmod
,
4004 .slave
= &omap44xx_gpmc_hwmod
,
4006 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4009 static struct omap_hwmod_addr_space omap44xx_gpu_addrs
[] = {
4011 .pa_start
= 0x56000000,
4012 .pa_end
= 0x5600ffff,
4013 .flags
= ADDR_TYPE_RT
4018 /* l3_main_2 -> gpu */
4019 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu
= {
4020 .master
= &omap44xx_l3_main_2_hwmod
,
4021 .slave
= &omap44xx_gpu_hwmod
,
4023 .addr
= omap44xx_gpu_addrs
,
4024 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4027 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs
[] = {
4029 .pa_start
= 0x480b2000,
4030 .pa_end
= 0x480b201f,
4031 .flags
= ADDR_TYPE_RT
4036 /* l4_per -> hdq1w */
4037 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w
= {
4038 .master
= &omap44xx_l4_per_hwmod
,
4039 .slave
= &omap44xx_hdq1w_hwmod
,
4041 .addr
= omap44xx_hdq1w_addrs
,
4042 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4045 static struct omap_hwmod_addr_space omap44xx_hsi_addrs
[] = {
4047 .pa_start
= 0x4a058000,
4048 .pa_end
= 0x4a05bfff,
4049 .flags
= ADDR_TYPE_RT
4055 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi
= {
4056 .master
= &omap44xx_l4_cfg_hwmod
,
4057 .slave
= &omap44xx_hsi_hwmod
,
4059 .addr
= omap44xx_hsi_addrs
,
4060 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4063 /* l4_per -> i2c1 */
4064 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1
= {
4065 .master
= &omap44xx_l4_per_hwmod
,
4066 .slave
= &omap44xx_i2c1_hwmod
,
4068 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4071 /* l4_per -> i2c2 */
4072 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2
= {
4073 .master
= &omap44xx_l4_per_hwmod
,
4074 .slave
= &omap44xx_i2c2_hwmod
,
4076 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4079 /* l4_per -> i2c3 */
4080 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3
= {
4081 .master
= &omap44xx_l4_per_hwmod
,
4082 .slave
= &omap44xx_i2c3_hwmod
,
4084 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4087 /* l4_per -> i2c4 */
4088 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4
= {
4089 .master
= &omap44xx_l4_per_hwmod
,
4090 .slave
= &omap44xx_i2c4_hwmod
,
4092 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4095 /* l3_main_2 -> ipu */
4096 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu
= {
4097 .master
= &omap44xx_l3_main_2_hwmod
,
4098 .slave
= &omap44xx_ipu_hwmod
,
4100 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4103 static struct omap_hwmod_addr_space omap44xx_iss_addrs
[] = {
4105 .pa_start
= 0x52000000,
4106 .pa_end
= 0x520000ff,
4107 .flags
= ADDR_TYPE_RT
4112 /* l3_main_2 -> iss */
4113 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss
= {
4114 .master
= &omap44xx_l3_main_2_hwmod
,
4115 .slave
= &omap44xx_iss_hwmod
,
4117 .addr
= omap44xx_iss_addrs
,
4118 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4122 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if
= {
4123 .master
= &omap44xx_iva_hwmod
,
4124 .slave
= &omap44xx_sl2if_hwmod
,
4125 .clk
= "dpll_iva_m5x2_ck",
4126 .user
= OCP_USER_IVA
,
4129 /* l3_main_2 -> iva */
4130 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva
= {
4131 .master
= &omap44xx_l3_main_2_hwmod
,
4132 .slave
= &omap44xx_iva_hwmod
,
4134 .user
= OCP_USER_MPU
,
4137 /* l4_wkup -> kbd */
4138 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd
= {
4139 .master
= &omap44xx_l4_wkup_hwmod
,
4140 .slave
= &omap44xx_kbd_hwmod
,
4141 .clk
= "l4_wkup_clk_mux_ck",
4142 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4145 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs
[] = {
4147 .pa_start
= 0x4a0f4000,
4148 .pa_end
= 0x4a0f41ff,
4149 .flags
= ADDR_TYPE_RT
4154 /* l4_cfg -> mailbox */
4155 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox
= {
4156 .master
= &omap44xx_l4_cfg_hwmod
,
4157 .slave
= &omap44xx_mailbox_hwmod
,
4159 .addr
= omap44xx_mailbox_addrs
,
4160 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4163 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs
[] = {
4165 .pa_start
= 0x40128000,
4166 .pa_end
= 0x401283ff,
4167 .flags
= ADDR_TYPE_RT
4172 /* l4_abe -> mcasp */
4173 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp
= {
4174 .master
= &omap44xx_l4_abe_hwmod
,
4175 .slave
= &omap44xx_mcasp_hwmod
,
4176 .clk
= "ocp_abe_iclk",
4177 .addr
= omap44xx_mcasp_addrs
,
4178 .user
= OCP_USER_MPU
,
4181 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs
[] = {
4183 .pa_start
= 0x49028000,
4184 .pa_end
= 0x490283ff,
4185 .flags
= ADDR_TYPE_RT
4190 /* l4_abe -> mcasp (dma) */
4191 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma
= {
4192 .master
= &omap44xx_l4_abe_hwmod
,
4193 .slave
= &omap44xx_mcasp_hwmod
,
4194 .clk
= "ocp_abe_iclk",
4195 .addr
= omap44xx_mcasp_dma_addrs
,
4196 .user
= OCP_USER_SDMA
,
4199 /* l4_abe -> mcbsp1 */
4200 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1
= {
4201 .master
= &omap44xx_l4_abe_hwmod
,
4202 .slave
= &omap44xx_mcbsp1_hwmod
,
4203 .clk
= "ocp_abe_iclk",
4204 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4207 /* l4_abe -> mcbsp2 */
4208 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2
= {
4209 .master
= &omap44xx_l4_abe_hwmod
,
4210 .slave
= &omap44xx_mcbsp2_hwmod
,
4211 .clk
= "ocp_abe_iclk",
4212 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4215 /* l4_abe -> mcbsp3 */
4216 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3
= {
4217 .master
= &omap44xx_l4_abe_hwmod
,
4218 .slave
= &omap44xx_mcbsp3_hwmod
,
4219 .clk
= "ocp_abe_iclk",
4220 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4223 /* l4_per -> mcbsp4 */
4224 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4
= {
4225 .master
= &omap44xx_l4_per_hwmod
,
4226 .slave
= &omap44xx_mcbsp4_hwmod
,
4228 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4231 /* l4_abe -> mcpdm */
4232 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm
= {
4233 .master
= &omap44xx_l4_abe_hwmod
,
4234 .slave
= &omap44xx_mcpdm_hwmod
,
4235 .clk
= "ocp_abe_iclk",
4236 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4239 /* l4_per -> mcspi1 */
4240 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1
= {
4241 .master
= &omap44xx_l4_per_hwmod
,
4242 .slave
= &omap44xx_mcspi1_hwmod
,
4244 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4247 /* l4_per -> mcspi2 */
4248 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2
= {
4249 .master
= &omap44xx_l4_per_hwmod
,
4250 .slave
= &omap44xx_mcspi2_hwmod
,
4252 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4255 /* l4_per -> mcspi3 */
4256 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3
= {
4257 .master
= &omap44xx_l4_per_hwmod
,
4258 .slave
= &omap44xx_mcspi3_hwmod
,
4260 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4263 /* l4_per -> mcspi4 */
4264 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4
= {
4265 .master
= &omap44xx_l4_per_hwmod
,
4266 .slave
= &omap44xx_mcspi4_hwmod
,
4268 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4271 /* l4_per -> mmc1 */
4272 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1
= {
4273 .master
= &omap44xx_l4_per_hwmod
,
4274 .slave
= &omap44xx_mmc1_hwmod
,
4276 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4279 /* l4_per -> mmc2 */
4280 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2
= {
4281 .master
= &omap44xx_l4_per_hwmod
,
4282 .slave
= &omap44xx_mmc2_hwmod
,
4284 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4287 /* l4_per -> mmc3 */
4288 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3
= {
4289 .master
= &omap44xx_l4_per_hwmod
,
4290 .slave
= &omap44xx_mmc3_hwmod
,
4292 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4295 /* l4_per -> mmc4 */
4296 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4
= {
4297 .master
= &omap44xx_l4_per_hwmod
,
4298 .slave
= &omap44xx_mmc4_hwmod
,
4300 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4303 /* l4_per -> mmc5 */
4304 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5
= {
4305 .master
= &omap44xx_l4_per_hwmod
,
4306 .slave
= &omap44xx_mmc5_hwmod
,
4308 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4311 /* l3_main_2 -> ocmc_ram */
4312 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram
= {
4313 .master
= &omap44xx_l3_main_2_hwmod
,
4314 .slave
= &omap44xx_ocmc_ram_hwmod
,
4316 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4319 /* l4_cfg -> ocp2scp_usb_phy */
4320 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy
= {
4321 .master
= &omap44xx_l4_cfg_hwmod
,
4322 .slave
= &omap44xx_ocp2scp_usb_phy_hwmod
,
4324 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4327 /* mpu_private -> prcm_mpu */
4328 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu
= {
4329 .master
= &omap44xx_mpu_private_hwmod
,
4330 .slave
= &omap44xx_prcm_mpu_hwmod
,
4332 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4335 /* l4_wkup -> cm_core_aon */
4336 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon
= {
4337 .master
= &omap44xx_l4_wkup_hwmod
,
4338 .slave
= &omap44xx_cm_core_aon_hwmod
,
4339 .clk
= "l4_wkup_clk_mux_ck",
4340 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4343 /* l4_cfg -> cm_core */
4344 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core
= {
4345 .master
= &omap44xx_l4_cfg_hwmod
,
4346 .slave
= &omap44xx_cm_core_hwmod
,
4348 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4351 /* l4_wkup -> prm */
4352 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm
= {
4353 .master
= &omap44xx_l4_wkup_hwmod
,
4354 .slave
= &omap44xx_prm_hwmod
,
4355 .clk
= "l4_wkup_clk_mux_ck",
4356 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4359 /* l4_wkup -> scrm */
4360 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm
= {
4361 .master
= &omap44xx_l4_wkup_hwmod
,
4362 .slave
= &omap44xx_scrm_hwmod
,
4363 .clk
= "l4_wkup_clk_mux_ck",
4364 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4367 /* l3_main_2 -> sl2if */
4368 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if
= {
4369 .master
= &omap44xx_l3_main_2_hwmod
,
4370 .slave
= &omap44xx_sl2if_hwmod
,
4372 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4375 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs
[] = {
4377 .pa_start
= 0x4012c000,
4378 .pa_end
= 0x4012c3ff,
4379 .flags
= ADDR_TYPE_RT
4384 /* l4_abe -> slimbus1 */
4385 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1
= {
4386 .master
= &omap44xx_l4_abe_hwmod
,
4387 .slave
= &omap44xx_slimbus1_hwmod
,
4388 .clk
= "ocp_abe_iclk",
4389 .addr
= omap44xx_slimbus1_addrs
,
4390 .user
= OCP_USER_MPU
,
4393 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs
[] = {
4395 .pa_start
= 0x4902c000,
4396 .pa_end
= 0x4902c3ff,
4397 .flags
= ADDR_TYPE_RT
4402 /* l4_abe -> slimbus1 (dma) */
4403 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma
= {
4404 .master
= &omap44xx_l4_abe_hwmod
,
4405 .slave
= &omap44xx_slimbus1_hwmod
,
4406 .clk
= "ocp_abe_iclk",
4407 .addr
= omap44xx_slimbus1_dma_addrs
,
4408 .user
= OCP_USER_SDMA
,
4411 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs
[] = {
4413 .pa_start
= 0x48076000,
4414 .pa_end
= 0x480763ff,
4415 .flags
= ADDR_TYPE_RT
4420 /* l4_per -> slimbus2 */
4421 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2
= {
4422 .master
= &omap44xx_l4_per_hwmod
,
4423 .slave
= &omap44xx_slimbus2_hwmod
,
4425 .addr
= omap44xx_slimbus2_addrs
,
4426 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4429 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs
[] = {
4431 .pa_start
= 0x4a0dd000,
4432 .pa_end
= 0x4a0dd03f,
4433 .flags
= ADDR_TYPE_RT
4438 /* l4_cfg -> smartreflex_core */
4439 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core
= {
4440 .master
= &omap44xx_l4_cfg_hwmod
,
4441 .slave
= &omap44xx_smartreflex_core_hwmod
,
4443 .addr
= omap44xx_smartreflex_core_addrs
,
4444 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4447 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs
[] = {
4449 .pa_start
= 0x4a0db000,
4450 .pa_end
= 0x4a0db03f,
4451 .flags
= ADDR_TYPE_RT
4456 /* l4_cfg -> smartreflex_iva */
4457 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva
= {
4458 .master
= &omap44xx_l4_cfg_hwmod
,
4459 .slave
= &omap44xx_smartreflex_iva_hwmod
,
4461 .addr
= omap44xx_smartreflex_iva_addrs
,
4462 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4465 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs
[] = {
4467 .pa_start
= 0x4a0d9000,
4468 .pa_end
= 0x4a0d903f,
4469 .flags
= ADDR_TYPE_RT
4474 /* l4_cfg -> smartreflex_mpu */
4475 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu
= {
4476 .master
= &omap44xx_l4_cfg_hwmod
,
4477 .slave
= &omap44xx_smartreflex_mpu_hwmod
,
4479 .addr
= omap44xx_smartreflex_mpu_addrs
,
4480 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4483 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs
[] = {
4485 .pa_start
= 0x4a0f6000,
4486 .pa_end
= 0x4a0f6fff,
4487 .flags
= ADDR_TYPE_RT
4492 /* l4_cfg -> spinlock */
4493 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock
= {
4494 .master
= &omap44xx_l4_cfg_hwmod
,
4495 .slave
= &omap44xx_spinlock_hwmod
,
4497 .addr
= omap44xx_spinlock_addrs
,
4498 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4501 /* l4_wkup -> timer1 */
4502 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1
= {
4503 .master
= &omap44xx_l4_wkup_hwmod
,
4504 .slave
= &omap44xx_timer1_hwmod
,
4505 .clk
= "l4_wkup_clk_mux_ck",
4506 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4509 /* l4_per -> timer2 */
4510 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2
= {
4511 .master
= &omap44xx_l4_per_hwmod
,
4512 .slave
= &omap44xx_timer2_hwmod
,
4514 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4517 /* l4_per -> timer3 */
4518 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3
= {
4519 .master
= &omap44xx_l4_per_hwmod
,
4520 .slave
= &omap44xx_timer3_hwmod
,
4522 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4525 /* l4_per -> timer4 */
4526 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4
= {
4527 .master
= &omap44xx_l4_per_hwmod
,
4528 .slave
= &omap44xx_timer4_hwmod
,
4530 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4533 /* l4_abe -> timer5 */
4534 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5
= {
4535 .master
= &omap44xx_l4_abe_hwmod
,
4536 .slave
= &omap44xx_timer5_hwmod
,
4537 .clk
= "ocp_abe_iclk",
4538 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4541 /* l4_abe -> timer6 */
4542 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6
= {
4543 .master
= &omap44xx_l4_abe_hwmod
,
4544 .slave
= &omap44xx_timer6_hwmod
,
4545 .clk
= "ocp_abe_iclk",
4546 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4549 /* l4_abe -> timer7 */
4550 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7
= {
4551 .master
= &omap44xx_l4_abe_hwmod
,
4552 .slave
= &omap44xx_timer7_hwmod
,
4553 .clk
= "ocp_abe_iclk",
4554 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4557 /* l4_abe -> timer8 */
4558 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8
= {
4559 .master
= &omap44xx_l4_abe_hwmod
,
4560 .slave
= &omap44xx_timer8_hwmod
,
4561 .clk
= "ocp_abe_iclk",
4562 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4565 /* l4_per -> timer9 */
4566 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9
= {
4567 .master
= &omap44xx_l4_per_hwmod
,
4568 .slave
= &omap44xx_timer9_hwmod
,
4570 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4573 /* l4_per -> timer10 */
4574 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10
= {
4575 .master
= &omap44xx_l4_per_hwmod
,
4576 .slave
= &omap44xx_timer10_hwmod
,
4578 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4581 /* l4_per -> timer11 */
4582 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11
= {
4583 .master
= &omap44xx_l4_per_hwmod
,
4584 .slave
= &omap44xx_timer11_hwmod
,
4586 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4589 /* l4_per -> uart1 */
4590 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1
= {
4591 .master
= &omap44xx_l4_per_hwmod
,
4592 .slave
= &omap44xx_uart1_hwmod
,
4594 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4597 /* l4_per -> uart2 */
4598 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2
= {
4599 .master
= &omap44xx_l4_per_hwmod
,
4600 .slave
= &omap44xx_uart2_hwmod
,
4602 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4605 /* l4_per -> uart3 */
4606 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3
= {
4607 .master
= &omap44xx_l4_per_hwmod
,
4608 .slave
= &omap44xx_uart3_hwmod
,
4610 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4613 /* l4_per -> uart4 */
4614 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4
= {
4615 .master
= &omap44xx_l4_per_hwmod
,
4616 .slave
= &omap44xx_uart4_hwmod
,
4618 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4621 /* l4_cfg -> usb_host_fs */
4622 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs
= {
4623 .master
= &omap44xx_l4_cfg_hwmod
,
4624 .slave
= &omap44xx_usb_host_fs_hwmod
,
4626 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4629 /* l4_cfg -> usb_host_hs */
4630 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs
= {
4631 .master
= &omap44xx_l4_cfg_hwmod
,
4632 .slave
= &omap44xx_usb_host_hs_hwmod
,
4634 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4637 /* l4_cfg -> usb_otg_hs */
4638 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs
= {
4639 .master
= &omap44xx_l4_cfg_hwmod
,
4640 .slave
= &omap44xx_usb_otg_hs_hwmod
,
4642 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4645 /* l4_cfg -> usb_tll_hs */
4646 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs
= {
4647 .master
= &omap44xx_l4_cfg_hwmod
,
4648 .slave
= &omap44xx_usb_tll_hs_hwmod
,
4650 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4653 /* l4_wkup -> wd_timer2 */
4654 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2
= {
4655 .master
= &omap44xx_l4_wkup_hwmod
,
4656 .slave
= &omap44xx_wd_timer2_hwmod
,
4657 .clk
= "l4_wkup_clk_mux_ck",
4658 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4661 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs
[] = {
4663 .pa_start
= 0x40130000,
4664 .pa_end
= 0x4013007f,
4665 .flags
= ADDR_TYPE_RT
4670 /* l4_abe -> wd_timer3 */
4671 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3
= {
4672 .master
= &omap44xx_l4_abe_hwmod
,
4673 .slave
= &omap44xx_wd_timer3_hwmod
,
4674 .clk
= "ocp_abe_iclk",
4675 .addr
= omap44xx_wd_timer3_addrs
,
4676 .user
= OCP_USER_MPU
,
4679 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs
[] = {
4681 .pa_start
= 0x49030000,
4682 .pa_end
= 0x4903007f,
4683 .flags
= ADDR_TYPE_RT
4688 /* l4_abe -> wd_timer3 (dma) */
4689 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma
= {
4690 .master
= &omap44xx_l4_abe_hwmod
,
4691 .slave
= &omap44xx_wd_timer3_hwmod
,
4692 .clk
= "ocp_abe_iclk",
4693 .addr
= omap44xx_wd_timer3_dma_addrs
,
4694 .user
= OCP_USER_SDMA
,
4698 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1
= {
4699 .master
= &omap44xx_mpu_hwmod
,
4700 .slave
= &omap44xx_emif1_hwmod
,
4702 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4706 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2
= {
4707 .master
= &omap44xx_mpu_hwmod
,
4708 .slave
= &omap44xx_emif2_hwmod
,
4710 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4713 static struct omap_hwmod_ocp_if
*omap44xx_hwmod_ocp_ifs
[] __initdata
= {
4714 &omap44xx_l3_main_1__dmm
,
4716 &omap44xx_iva__l3_instr
,
4717 &omap44xx_l3_main_3__l3_instr
,
4718 &omap44xx_ocp_wp_noc__l3_instr
,
4719 &omap44xx_dsp__l3_main_1
,
4720 &omap44xx_dss__l3_main_1
,
4721 &omap44xx_l3_main_2__l3_main_1
,
4722 &omap44xx_l4_cfg__l3_main_1
,
4723 &omap44xx_mmc1__l3_main_1
,
4724 &omap44xx_mmc2__l3_main_1
,
4725 &omap44xx_mpu__l3_main_1
,
4726 &omap44xx_debugss__l3_main_2
,
4727 &omap44xx_dma_system__l3_main_2
,
4728 &omap44xx_fdif__l3_main_2
,
4729 &omap44xx_gpu__l3_main_2
,
4730 &omap44xx_hsi__l3_main_2
,
4731 &omap44xx_ipu__l3_main_2
,
4732 &omap44xx_iss__l3_main_2
,
4733 &omap44xx_iva__l3_main_2
,
4734 &omap44xx_l3_main_1__l3_main_2
,
4735 &omap44xx_l4_cfg__l3_main_2
,
4736 /* &omap44xx_usb_host_fs__l3_main_2, */
4737 &omap44xx_usb_host_hs__l3_main_2
,
4738 &omap44xx_usb_otg_hs__l3_main_2
,
4739 &omap44xx_l3_main_1__l3_main_3
,
4740 &omap44xx_l3_main_2__l3_main_3
,
4741 &omap44xx_l4_cfg__l3_main_3
,
4742 &omap44xx_aess__l4_abe
,
4743 &omap44xx_dsp__l4_abe
,
4744 &omap44xx_l3_main_1__l4_abe
,
4745 &omap44xx_mpu__l4_abe
,
4746 &omap44xx_l3_main_1__l4_cfg
,
4747 &omap44xx_l3_main_2__l4_per
,
4748 &omap44xx_l4_cfg__l4_wkup
,
4749 &omap44xx_mpu__mpu_private
,
4750 &omap44xx_l4_cfg__ocp_wp_noc
,
4751 &omap44xx_l4_abe__aess
,
4752 &omap44xx_l4_abe__aess_dma
,
4753 &omap44xx_l3_main_2__c2c
,
4754 &omap44xx_l4_wkup__counter_32k
,
4755 &omap44xx_l4_cfg__ctrl_module_core
,
4756 &omap44xx_l4_cfg__ctrl_module_pad_core
,
4757 &omap44xx_l4_wkup__ctrl_module_wkup
,
4758 &omap44xx_l4_wkup__ctrl_module_pad_wkup
,
4759 &omap44xx_l3_instr__debugss
,
4760 &omap44xx_l4_cfg__dma_system
,
4761 &omap44xx_l4_abe__dmic
,
4763 /* &omap44xx_dsp__sl2if, */
4764 &omap44xx_l4_cfg__dsp
,
4765 &omap44xx_l3_main_2__dss
,
4766 &omap44xx_l4_per__dss
,
4767 &omap44xx_l3_main_2__dss_dispc
,
4768 &omap44xx_l4_per__dss_dispc
,
4769 &omap44xx_l3_main_2__dss_dsi1
,
4770 &omap44xx_l4_per__dss_dsi1
,
4771 &omap44xx_l3_main_2__dss_dsi2
,
4772 &omap44xx_l4_per__dss_dsi2
,
4773 &omap44xx_l3_main_2__dss_hdmi
,
4774 &omap44xx_l4_per__dss_hdmi
,
4775 &omap44xx_l3_main_2__dss_rfbi
,
4776 &omap44xx_l4_per__dss_rfbi
,
4777 &omap44xx_l3_main_2__dss_venc
,
4778 &omap44xx_l4_per__dss_venc
,
4779 &omap44xx_l4_per__elm
,
4780 &omap44xx_l4_cfg__fdif
,
4781 &omap44xx_l4_wkup__gpio1
,
4782 &omap44xx_l4_per__gpio2
,
4783 &omap44xx_l4_per__gpio3
,
4784 &omap44xx_l4_per__gpio4
,
4785 &omap44xx_l4_per__gpio5
,
4786 &omap44xx_l4_per__gpio6
,
4787 &omap44xx_l3_main_2__gpmc
,
4788 &omap44xx_l3_main_2__gpu
,
4789 &omap44xx_l4_per__hdq1w
,
4790 &omap44xx_l4_cfg__hsi
,
4791 &omap44xx_l4_per__i2c1
,
4792 &omap44xx_l4_per__i2c2
,
4793 &omap44xx_l4_per__i2c3
,
4794 &omap44xx_l4_per__i2c4
,
4795 &omap44xx_l3_main_2__ipu
,
4796 &omap44xx_l3_main_2__iss
,
4797 /* &omap44xx_iva__sl2if, */
4798 &omap44xx_l3_main_2__iva
,
4799 &omap44xx_l4_wkup__kbd
,
4800 &omap44xx_l4_cfg__mailbox
,
4801 &omap44xx_l4_abe__mcasp
,
4802 &omap44xx_l4_abe__mcasp_dma
,
4803 &omap44xx_l4_abe__mcbsp1
,
4804 &omap44xx_l4_abe__mcbsp2
,
4805 &omap44xx_l4_abe__mcbsp3
,
4806 &omap44xx_l4_per__mcbsp4
,
4807 &omap44xx_l4_abe__mcpdm
,
4808 &omap44xx_l4_per__mcspi1
,
4809 &omap44xx_l4_per__mcspi2
,
4810 &omap44xx_l4_per__mcspi3
,
4811 &omap44xx_l4_per__mcspi4
,
4812 &omap44xx_l4_per__mmc1
,
4813 &omap44xx_l4_per__mmc2
,
4814 &omap44xx_l4_per__mmc3
,
4815 &omap44xx_l4_per__mmc4
,
4816 &omap44xx_l4_per__mmc5
,
4817 &omap44xx_l3_main_2__mmu_ipu
,
4818 &omap44xx_l4_cfg__mmu_dsp
,
4819 &omap44xx_l3_main_2__ocmc_ram
,
4820 &omap44xx_l4_cfg__ocp2scp_usb_phy
,
4821 &omap44xx_mpu_private__prcm_mpu
,
4822 &omap44xx_l4_wkup__cm_core_aon
,
4823 &omap44xx_l4_cfg__cm_core
,
4824 &omap44xx_l4_wkup__prm
,
4825 &omap44xx_l4_wkup__scrm
,
4826 /* &omap44xx_l3_main_2__sl2if, */
4827 &omap44xx_l4_abe__slimbus1
,
4828 &omap44xx_l4_abe__slimbus1_dma
,
4829 &omap44xx_l4_per__slimbus2
,
4830 &omap44xx_l4_cfg__smartreflex_core
,
4831 &omap44xx_l4_cfg__smartreflex_iva
,
4832 &omap44xx_l4_cfg__smartreflex_mpu
,
4833 &omap44xx_l4_cfg__spinlock
,
4834 &omap44xx_l4_wkup__timer1
,
4835 &omap44xx_l4_per__timer2
,
4836 &omap44xx_l4_per__timer3
,
4837 &omap44xx_l4_per__timer4
,
4838 &omap44xx_l4_abe__timer5
,
4839 &omap44xx_l4_abe__timer6
,
4840 &omap44xx_l4_abe__timer7
,
4841 &omap44xx_l4_abe__timer8
,
4842 &omap44xx_l4_per__timer9
,
4843 &omap44xx_l4_per__timer10
,
4844 &omap44xx_l4_per__timer11
,
4845 &omap44xx_l4_per__uart1
,
4846 &omap44xx_l4_per__uart2
,
4847 &omap44xx_l4_per__uart3
,
4848 &omap44xx_l4_per__uart4
,
4849 /* &omap44xx_l4_cfg__usb_host_fs, */
4850 &omap44xx_l4_cfg__usb_host_hs
,
4851 &omap44xx_l4_cfg__usb_otg_hs
,
4852 &omap44xx_l4_cfg__usb_tll_hs
,
4853 &omap44xx_l4_wkup__wd_timer2
,
4854 &omap44xx_l4_abe__wd_timer3
,
4855 &omap44xx_l4_abe__wd_timer3_dma
,
4856 &omap44xx_mpu__emif1
,
4857 &omap44xx_mpu__emif2
,
4861 int __init
omap44xx_hwmod_init(void)
4864 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs
);