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Merge tag 'locks-v3.16-2' of git://git.samba.org/jlayton/linux
[linux/fpc-iii.git] / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
blob20b4398cec05ce63dea1a1cece300800c975060c
1 /*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/i2c-omap.h>
24
25 #include <linux/omap-dma.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/asoc-ti-mcbsp.h>
28 #include <plat/dmtimer.h>
29
30 #include "omap_hwmod.h"
31 #include "omap_hwmod_common_data.h"
32 #include "cm1_7xx.h"
33 #include "cm2_7xx.h"
34 #include "prm7xx.h"
35 #include "i2c.h"
36 #include "mmc.h"
37 #include "wd_timer.h"
38
39 /* Base offset for all DRA7XX interrupts external to MPUSS */
40 #define DRA7XX_IRQ_GIC_START 32
41
42 /* Base offset for all DRA7XX dma requests */
43 #define DRA7XX_DMA_REQ_START 1
44
45
46 /*
47 * IP blocks
48 */
49
50 /*
51 * 'l3' class
52 * instance(s): l3_instr, l3_main_1, l3_main_2
53 */
54 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
55 .name = "l3",
56 };
57
58 /* l3_instr */
59 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
60 .name = "l3_instr",
61 .class = &dra7xx_l3_hwmod_class,
62 .clkdm_name = "l3instr_clkdm",
63 .prcm = {
64 .omap4 = {
65 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
66 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
67 .modulemode = MODULEMODE_HWCTRL,
68 },
69 },
70 };
71
72 /* l3_main_1 */
73 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
74 .name = "l3_main_1",
75 .class = &dra7xx_l3_hwmod_class,
76 .clkdm_name = "l3main1_clkdm",
77 .prcm = {
78 .omap4 = {
79 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
80 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
81 },
82 },
83 };
84
85 /* l3_main_2 */
86 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
87 .name = "l3_main_2",
88 .class = &dra7xx_l3_hwmod_class,
89 .clkdm_name = "l3instr_clkdm",
90 .prcm = {
91 .omap4 = {
92 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
93 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
94 .modulemode = MODULEMODE_HWCTRL,
95 },
96 },
97 };
98
99 /*
100 * 'l4' class
101 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
102 */
103 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
104 .name = "l4",
105 };
106
107 /* l4_cfg */
108 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
109 .name = "l4_cfg",
110 .class = &dra7xx_l4_hwmod_class,
111 .clkdm_name = "l4cfg_clkdm",
112 .prcm = {
113 .omap4 = {
114 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
116 },
117 },
118 };
119
120 /* l4_per1 */
121 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
122 .name = "l4_per1",
123 .class = &dra7xx_l4_hwmod_class,
124 .clkdm_name = "l4per_clkdm",
125 .prcm = {
126 .omap4 = {
127 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
128 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
129 },
130 },
131 };
132
133 /* l4_per2 */
134 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
135 .name = "l4_per2",
136 .class = &dra7xx_l4_hwmod_class,
137 .clkdm_name = "l4per2_clkdm",
138 .prcm = {
139 .omap4 = {
140 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
141 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
142 },
143 },
144 };
145
146 /* l4_per3 */
147 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
148 .name = "l4_per3",
149 .class = &dra7xx_l4_hwmod_class,
150 .clkdm_name = "l4per3_clkdm",
151 .prcm = {
152 .omap4 = {
153 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
154 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
155 },
156 },
157 };
158
159 /* l4_wkup */
160 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
161 .name = "l4_wkup",
162 .class = &dra7xx_l4_hwmod_class,
163 .clkdm_name = "wkupaon_clkdm",
164 .prcm = {
165 .omap4 = {
166 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
167 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
168 },
169 },
170 };
171
172 /*
173 * 'atl' class
174 *
175 */
176
177 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
178 .name = "atl",
179 };
180
181 /* atl */
182 static struct omap_hwmod dra7xx_atl_hwmod = {
183 .name = "atl",
184 .class = &dra7xx_atl_hwmod_class,
185 .clkdm_name = "atl_clkdm",
186 .main_clk = "atl_gfclk_mux",
187 .prcm = {
188 .omap4 = {
189 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
190 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
191 .modulemode = MODULEMODE_SWCTRL,
192 },
193 },
194 };
195
196 /*
197 * 'bb2d' class
198 *
199 */
200
201 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
202 .name = "bb2d",
203 };
204
205 /* bb2d */
206 static struct omap_hwmod dra7xx_bb2d_hwmod = {
207 .name = "bb2d",
208 .class = &dra7xx_bb2d_hwmod_class,
209 .clkdm_name = "dss_clkdm",
210 .main_clk = "dpll_core_h24x2_ck",
211 .prcm = {
212 .omap4 = {
213 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
214 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
215 .modulemode = MODULEMODE_SWCTRL,
216 },
217 },
218 };
219
220 /*
221 * 'counter' class
222 *
223 */
224
225 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
226 .rev_offs = 0x0000,
227 .sysc_offs = 0x0010,
228 .sysc_flags = SYSC_HAS_SIDLEMODE,
229 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
230 SIDLE_SMART_WKUP),
231 .sysc_fields = &omap_hwmod_sysc_type1,
232 };
233
234 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
235 .name = "counter",
236 .sysc = &dra7xx_counter_sysc,
237 };
238
239 /* counter_32k */
240 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
241 .name = "counter_32k",
242 .class = &dra7xx_counter_hwmod_class,
243 .clkdm_name = "wkupaon_clkdm",
244 .flags = HWMOD_SWSUP_SIDLE,
245 .main_clk = "wkupaon_iclk_mux",
246 .prcm = {
247 .omap4 = {
248 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
249 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
250 },
251 },
252 };
253
254 /*
255 * 'ctrl_module' class
256 *
257 */
258
259 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
260 .name = "ctrl_module",
261 };
262
263 /* ctrl_module_wkup */
264 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
265 .name = "ctrl_module_wkup",
266 .class = &dra7xx_ctrl_module_hwmod_class,
267 .clkdm_name = "wkupaon_clkdm",
268 .prcm = {
269 .omap4 = {
270 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
271 },
272 },
273 };
274
275 /*
276 * 'dcan' class
277 *
278 */
279
280 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
281 .name = "dcan",
282 };
283
284 /* dcan1 */
285 static struct omap_hwmod dra7xx_dcan1_hwmod = {
286 .name = "dcan1",
287 .class = &dra7xx_dcan_hwmod_class,
288 .clkdm_name = "wkupaon_clkdm",
289 .main_clk = "dcan1_sys_clk_mux",
290 .prcm = {
291 .omap4 = {
292 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
293 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
294 .modulemode = MODULEMODE_SWCTRL,
295 },
296 },
297 };
298
299 /* dcan2 */
300 static struct omap_hwmod dra7xx_dcan2_hwmod = {
301 .name = "dcan2",
302 .class = &dra7xx_dcan_hwmod_class,
303 .clkdm_name = "l4per2_clkdm",
304 .main_clk = "sys_clkin1",
305 .prcm = {
306 .omap4 = {
307 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
308 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
309 .modulemode = MODULEMODE_SWCTRL,
310 },
311 },
312 };
313
314 /*
315 * 'dma' class
316 *
317 */
318
319 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
320 .rev_offs = 0x0000,
321 .sysc_offs = 0x002c,
322 .syss_offs = 0x0028,
323 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
324 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
325 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
326 SYSS_HAS_RESET_STATUS),
327 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
328 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
329 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
330 .sysc_fields = &omap_hwmod_sysc_type1,
331 };
332
333 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
334 .name = "dma",
335 .sysc = &dra7xx_dma_sysc,
336 };
337
338 /* dma dev_attr */
339 static struct omap_dma_dev_attr dma_dev_attr = {
340 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
341 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
342 .lch_count = 32,
343 };
344
345 /* dma_system */
346 static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
347 { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
348 { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
349 { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
350 { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
351 { .irq = -1 }
352 };
353
354 static struct omap_hwmod dra7xx_dma_system_hwmod = {
355 .name = "dma_system",
356 .class = &dra7xx_dma_hwmod_class,
357 .clkdm_name = "dma_clkdm",
358 .mpu_irqs = dra7xx_dma_system_irqs,
359 .main_clk = "l3_iclk_div",
360 .prcm = {
361 .omap4 = {
362 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
363 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
364 },
365 },
366 .dev_attr = &dma_dev_attr,
367 };
368
369 /*
370 * 'dss' class
371 *
372 */
373
374 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
375 .rev_offs = 0x0000,
376 .syss_offs = 0x0014,
377 .sysc_flags = SYSS_HAS_RESET_STATUS,
378 };
379
380 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
381 .name = "dss",
382 .sysc = &dra7xx_dss_sysc,
383 .reset = omap_dss_reset,
384 };
385
386 /* dss */
387 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
388 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
389 { .dma_req = -1 }
390 };
391
392 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
393 { .role = "dss_clk", .clk = "dss_dss_clk" },
394 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
395 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
396 { .role = "video2_clk", .clk = "dss_video2_clk" },
397 { .role = "video1_clk", .clk = "dss_video1_clk" },
398 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
399 };
400
401 static struct omap_hwmod dra7xx_dss_hwmod = {
402 .name = "dss_core",
403 .class = &dra7xx_dss_hwmod_class,
404 .clkdm_name = "dss_clkdm",
405 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
406 .sdma_reqs = dra7xx_dss_sdma_reqs,
407 .main_clk = "dss_dss_clk",
408 .prcm = {
409 .omap4 = {
410 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
411 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
412 .modulemode = MODULEMODE_SWCTRL,
413 },
414 },
415 .opt_clks = dss_opt_clks,
416 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
417 };
418
419 /*
420 * 'dispc' class
421 * display controller
422 */
423
424 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
425 .rev_offs = 0x0000,
426 .sysc_offs = 0x0010,
427 .syss_offs = 0x0014,
428 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
429 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
430 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
431 SYSS_HAS_RESET_STATUS),
432 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
433 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
434 .sysc_fields = &omap_hwmod_sysc_type1,
435 };
436
437 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
438 .name = "dispc",
439 .sysc = &dra7xx_dispc_sysc,
440 };
441
442 /* dss_dispc */
443 /* dss_dispc dev_attr */
444 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
445 .has_framedonetv_irq = 1,
446 .manager_count = 4,
447 };
448
449 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
450 .name = "dss_dispc",
451 .class = &dra7xx_dispc_hwmod_class,
452 .clkdm_name = "dss_clkdm",
453 .main_clk = "dss_dss_clk",
454 .prcm = {
455 .omap4 = {
456 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
457 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
458 },
459 },
460 .dev_attr = &dss_dispc_dev_attr,
461 };
462
463 /*
464 * 'hdmi' class
465 * hdmi controller
466 */
467
468 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
469 .rev_offs = 0x0000,
470 .sysc_offs = 0x0010,
471 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
472 SYSC_HAS_SOFTRESET),
473 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
474 SIDLE_SMART_WKUP),
475 .sysc_fields = &omap_hwmod_sysc_type2,
476 };
477
478 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
479 .name = "hdmi",
480 .sysc = &dra7xx_hdmi_sysc,
481 };
482
483 /* dss_hdmi */
484
485 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
486 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
487 };
488
489 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
490 .name = "dss_hdmi",
491 .class = &dra7xx_hdmi_hwmod_class,
492 .clkdm_name = "dss_clkdm",
493 .main_clk = "dss_48mhz_clk",
494 .prcm = {
495 .omap4 = {
496 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
497 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
498 },
499 },
500 .opt_clks = dss_hdmi_opt_clks,
501 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
502 };
503
504 /*
505 * 'elm' class
506 *
507 */
508
509 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
510 .rev_offs = 0x0000,
511 .sysc_offs = 0x0010,
512 .syss_offs = 0x0014,
513 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
514 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
515 SYSS_HAS_RESET_STATUS),
516 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
517 SIDLE_SMART_WKUP),
518 .sysc_fields = &omap_hwmod_sysc_type1,
519 };
520
521 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
522 .name = "elm",
523 .sysc = &dra7xx_elm_sysc,
524 };
525
526 /* elm */
527
528 static struct omap_hwmod dra7xx_elm_hwmod = {
529 .name = "elm",
530 .class = &dra7xx_elm_hwmod_class,
531 .clkdm_name = "l4per_clkdm",
532 .main_clk = "l3_iclk_div",
533 .prcm = {
534 .omap4 = {
535 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
536 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
537 },
538 },
539 };
540
541 /*
542 * 'gpio' class
543 *
544 */
545
546 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
547 .rev_offs = 0x0000,
548 .sysc_offs = 0x0010,
549 .syss_offs = 0x0114,
550 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
551 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
552 SYSS_HAS_RESET_STATUS),
553 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
554 SIDLE_SMART_WKUP),
555 .sysc_fields = &omap_hwmod_sysc_type1,
556 };
557
558 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
559 .name = "gpio",
560 .sysc = &dra7xx_gpio_sysc,
561 .rev = 2,
562 };
563
564 /* gpio dev_attr */
565 static struct omap_gpio_dev_attr gpio_dev_attr = {
566 .bank_width = 32,
567 .dbck_flag = true,
568 };
569
570 /* gpio1 */
571 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
572 { .role = "dbclk", .clk = "gpio1_dbclk" },
573 };
574
575 static struct omap_hwmod dra7xx_gpio1_hwmod = {
576 .name = "gpio1",
577 .class = &dra7xx_gpio_hwmod_class,
578 .clkdm_name = "wkupaon_clkdm",
579 .main_clk = "wkupaon_iclk_mux",
580 .prcm = {
581 .omap4 = {
582 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
583 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
584 .modulemode = MODULEMODE_HWCTRL,
585 },
586 },
587 .opt_clks = gpio1_opt_clks,
588 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
589 .dev_attr = &gpio_dev_attr,
590 };
591
592 /* gpio2 */
593 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
594 { .role = "dbclk", .clk = "gpio2_dbclk" },
595 };
596
597 static struct omap_hwmod dra7xx_gpio2_hwmod = {
598 .name = "gpio2",
599 .class = &dra7xx_gpio_hwmod_class,
600 .clkdm_name = "l4per_clkdm",
601 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
602 .main_clk = "l3_iclk_div",
603 .prcm = {
604 .omap4 = {
605 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
606 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
607 .modulemode = MODULEMODE_HWCTRL,
608 },
609 },
610 .opt_clks = gpio2_opt_clks,
611 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
612 .dev_attr = &gpio_dev_attr,
613 };
614
615 /* gpio3 */
616 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
617 { .role = "dbclk", .clk = "gpio3_dbclk" },
618 };
619
620 static struct omap_hwmod dra7xx_gpio3_hwmod = {
621 .name = "gpio3",
622 .class = &dra7xx_gpio_hwmod_class,
623 .clkdm_name = "l4per_clkdm",
624 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
625 .main_clk = "l3_iclk_div",
626 .prcm = {
627 .omap4 = {
628 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
629 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
630 .modulemode = MODULEMODE_HWCTRL,
631 },
632 },
633 .opt_clks = gpio3_opt_clks,
634 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
635 .dev_attr = &gpio_dev_attr,
636 };
637
638 /* gpio4 */
639 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
640 { .role = "dbclk", .clk = "gpio4_dbclk" },
641 };
642
643 static struct omap_hwmod dra7xx_gpio4_hwmod = {
644 .name = "gpio4",
645 .class = &dra7xx_gpio_hwmod_class,
646 .clkdm_name = "l4per_clkdm",
647 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
648 .main_clk = "l3_iclk_div",
649 .prcm = {
650 .omap4 = {
651 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
652 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
653 .modulemode = MODULEMODE_HWCTRL,
654 },
655 },
656 .opt_clks = gpio4_opt_clks,
657 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
658 .dev_attr = &gpio_dev_attr,
659 };
660
661 /* gpio5 */
662 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
663 { .role = "dbclk", .clk = "gpio5_dbclk" },
664 };
665
666 static struct omap_hwmod dra7xx_gpio5_hwmod = {
667 .name = "gpio5",
668 .class = &dra7xx_gpio_hwmod_class,
669 .clkdm_name = "l4per_clkdm",
670 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
671 .main_clk = "l3_iclk_div",
672 .prcm = {
673 .omap4 = {
674 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
675 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
676 .modulemode = MODULEMODE_HWCTRL,
677 },
678 },
679 .opt_clks = gpio5_opt_clks,
680 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
681 .dev_attr = &gpio_dev_attr,
682 };
683
684 /* gpio6 */
685 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
686 { .role = "dbclk", .clk = "gpio6_dbclk" },
687 };
688
689 static struct omap_hwmod dra7xx_gpio6_hwmod = {
690 .name = "gpio6",
691 .class = &dra7xx_gpio_hwmod_class,
692 .clkdm_name = "l4per_clkdm",
693 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
694 .main_clk = "l3_iclk_div",
695 .prcm = {
696 .omap4 = {
697 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
698 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
699 .modulemode = MODULEMODE_HWCTRL,
700 },
701 },
702 .opt_clks = gpio6_opt_clks,
703 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
704 .dev_attr = &gpio_dev_attr,
705 };
706
707 /* gpio7 */
708 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
709 { .role = "dbclk", .clk = "gpio7_dbclk" },
710 };
711
712 static struct omap_hwmod dra7xx_gpio7_hwmod = {
713 .name = "gpio7",
714 .class = &dra7xx_gpio_hwmod_class,
715 .clkdm_name = "l4per_clkdm",
716 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
717 .main_clk = "l3_iclk_div",
718 .prcm = {
719 .omap4 = {
720 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
721 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
722 .modulemode = MODULEMODE_HWCTRL,
723 },
724 },
725 .opt_clks = gpio7_opt_clks,
726 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
727 .dev_attr = &gpio_dev_attr,
728 };
729
730 /* gpio8 */
731 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
732 { .role = "dbclk", .clk = "gpio8_dbclk" },
733 };
734
735 static struct omap_hwmod dra7xx_gpio8_hwmod = {
736 .name = "gpio8",
737 .class = &dra7xx_gpio_hwmod_class,
738 .clkdm_name = "l4per_clkdm",
739 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
740 .main_clk = "l3_iclk_div",
741 .prcm = {
742 .omap4 = {
743 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
744 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
745 .modulemode = MODULEMODE_HWCTRL,
746 },
747 },
748 .opt_clks = gpio8_opt_clks,
749 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
750 .dev_attr = &gpio_dev_attr,
751 };
752
753 /*
754 * 'gpmc' class
755 *
756 */
757
758 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
759 .rev_offs = 0x0000,
760 .sysc_offs = 0x0010,
761 .syss_offs = 0x0014,
762 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
763 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
764 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
765 SIDLE_SMART_WKUP),
766 .sysc_fields = &omap_hwmod_sysc_type1,
767 };
768
769 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
770 .name = "gpmc",
771 .sysc = &dra7xx_gpmc_sysc,
772 };
773
774 /* gpmc */
775
776 static struct omap_hwmod dra7xx_gpmc_hwmod = {
777 .name = "gpmc",
778 .class = &dra7xx_gpmc_hwmod_class,
779 .clkdm_name = "l3main1_clkdm",
780 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
781 .main_clk = "l3_iclk_div",
782 .prcm = {
783 .omap4 = {
784 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
785 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
786 .modulemode = MODULEMODE_HWCTRL,
787 },
788 },
789 };
790
791 /*
792 * 'hdq1w' class
793 *
794 */
795
796 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
797 .rev_offs = 0x0000,
798 .sysc_offs = 0x0014,
799 .syss_offs = 0x0018,
800 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
801 SYSS_HAS_RESET_STATUS),
802 .sysc_fields = &omap_hwmod_sysc_type1,
803 };
804
805 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
806 .name = "hdq1w",
807 .sysc = &dra7xx_hdq1w_sysc,
808 };
809
810 /* hdq1w */
811
812 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
813 .name = "hdq1w",
814 .class = &dra7xx_hdq1w_hwmod_class,
815 .clkdm_name = "l4per_clkdm",
816 .flags = HWMOD_INIT_NO_RESET,
817 .main_clk = "func_12m_fclk",
818 .prcm = {
819 .omap4 = {
820 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
821 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
822 .modulemode = MODULEMODE_SWCTRL,
823 },
824 },
825 };
826
827 /*
828 * 'i2c' class
829 *
830 */
831
832 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
833 .sysc_offs = 0x0010,
834 .syss_offs = 0x0090,
835 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
836 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
837 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
838 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
839 SIDLE_SMART_WKUP),
840 .clockact = CLOCKACT_TEST_ICLK,
841 .sysc_fields = &omap_hwmod_sysc_type1,
842 };
843
844 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
845 .name = "i2c",
846 .sysc = &dra7xx_i2c_sysc,
847 .reset = &omap_i2c_reset,
848 .rev = OMAP_I2C_IP_VERSION_2,
849 };
850
851 /* i2c dev_attr */
852 static struct omap_i2c_dev_attr i2c_dev_attr = {
853 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
854 };
855
856 /* i2c1 */
857 static struct omap_hwmod dra7xx_i2c1_hwmod = {
858 .name = "i2c1",
859 .class = &dra7xx_i2c_hwmod_class,
860 .clkdm_name = "l4per_clkdm",
861 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
862 .main_clk = "func_96m_fclk",
863 .prcm = {
864 .omap4 = {
865 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
866 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
867 .modulemode = MODULEMODE_SWCTRL,
868 },
869 },
870 .dev_attr = &i2c_dev_attr,
871 };
872
873 /* i2c2 */
874 static struct omap_hwmod dra7xx_i2c2_hwmod = {
875 .name = "i2c2",
876 .class = &dra7xx_i2c_hwmod_class,
877 .clkdm_name = "l4per_clkdm",
878 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
879 .main_clk = "func_96m_fclk",
880 .prcm = {
881 .omap4 = {
882 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
883 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
884 .modulemode = MODULEMODE_SWCTRL,
885 },
886 },
887 .dev_attr = &i2c_dev_attr,
888 };
889
890 /* i2c3 */
891 static struct omap_hwmod dra7xx_i2c3_hwmod = {
892 .name = "i2c3",
893 .class = &dra7xx_i2c_hwmod_class,
894 .clkdm_name = "l4per_clkdm",
895 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
896 .main_clk = "func_96m_fclk",
897 .prcm = {
898 .omap4 = {
899 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
900 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
901 .modulemode = MODULEMODE_SWCTRL,
902 },
903 },
904 .dev_attr = &i2c_dev_attr,
905 };
906
907 /* i2c4 */
908 static struct omap_hwmod dra7xx_i2c4_hwmod = {
909 .name = "i2c4",
910 .class = &dra7xx_i2c_hwmod_class,
911 .clkdm_name = "l4per_clkdm",
912 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
913 .main_clk = "func_96m_fclk",
914 .prcm = {
915 .omap4 = {
916 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
917 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
918 .modulemode = MODULEMODE_SWCTRL,
919 },
920 },
921 .dev_attr = &i2c_dev_attr,
922 };
923
924 /* i2c5 */
925 static struct omap_hwmod dra7xx_i2c5_hwmod = {
926 .name = "i2c5",
927 .class = &dra7xx_i2c_hwmod_class,
928 .clkdm_name = "ipu_clkdm",
929 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
930 .main_clk = "func_96m_fclk",
931 .prcm = {
932 .omap4 = {
933 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
934 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
935 .modulemode = MODULEMODE_SWCTRL,
936 },
937 },
938 .dev_attr = &i2c_dev_attr,
939 };
940
941 /*
942 * 'mcspi' class
943 *
944 */
945
946 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
947 .rev_offs = 0x0000,
948 .sysc_offs = 0x0010,
949 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
950 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
951 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
952 SIDLE_SMART_WKUP),
953 .sysc_fields = &omap_hwmod_sysc_type2,
954 };
955
956 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
957 .name = "mcspi",
958 .sysc = &dra7xx_mcspi_sysc,
959 .rev = OMAP4_MCSPI_REV,
960 };
961
962 /* mcspi1 */
963 /* mcspi1 dev_attr */
964 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
965 .num_chipselect = 4,
966 };
967
968 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
969 .name = "mcspi1",
970 .class = &dra7xx_mcspi_hwmod_class,
971 .clkdm_name = "l4per_clkdm",
972 .main_clk = "func_48m_fclk",
973 .prcm = {
974 .omap4 = {
975 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
976 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
977 .modulemode = MODULEMODE_SWCTRL,
978 },
979 },
980 .dev_attr = &mcspi1_dev_attr,
981 };
982
983 /* mcspi2 */
984 /* mcspi2 dev_attr */
985 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
986 .num_chipselect = 2,
987 };
988
989 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
990 .name = "mcspi2",
991 .class = &dra7xx_mcspi_hwmod_class,
992 .clkdm_name = "l4per_clkdm",
993 .main_clk = "func_48m_fclk",
994 .prcm = {
995 .omap4 = {
996 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
997 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
998 .modulemode = MODULEMODE_SWCTRL,
999 },
1000 },
1001 .dev_attr = &mcspi2_dev_attr,
1002 };
1003
1004 /* mcspi3 */
1005 /* mcspi3 dev_attr */
1006 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1007 .num_chipselect = 2,
1008 };
1009
1010 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1011 .name = "mcspi3",
1012 .class = &dra7xx_mcspi_hwmod_class,
1013 .clkdm_name = "l4per_clkdm",
1014 .main_clk = "func_48m_fclk",
1015 .prcm = {
1016 .omap4 = {
1017 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1018 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1019 .modulemode = MODULEMODE_SWCTRL,
1020 },
1021 },
1022 .dev_attr = &mcspi3_dev_attr,
1023 };
1024
1025 /* mcspi4 */
1026 /* mcspi4 dev_attr */
1027 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1028 .num_chipselect = 1,
1029 };
1030
1031 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1032 .name = "mcspi4",
1033 .class = &dra7xx_mcspi_hwmod_class,
1034 .clkdm_name = "l4per_clkdm",
1035 .main_clk = "func_48m_fclk",
1036 .prcm = {
1037 .omap4 = {
1038 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1039 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1040 .modulemode = MODULEMODE_SWCTRL,
1041 },
1042 },
1043 .dev_attr = &mcspi4_dev_attr,
1044 };
1045
1046 /*
1047 * 'mmc' class
1048 *
1049 */
1050
1051 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1052 .rev_offs = 0x0000,
1053 .sysc_offs = 0x0010,
1054 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1055 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1056 SYSC_HAS_SOFTRESET),
1057 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1058 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1059 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1060 .sysc_fields = &omap_hwmod_sysc_type2,
1061 };
1062
1063 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1064 .name = "mmc",
1065 .sysc = &dra7xx_mmc_sysc,
1066 };
1067
1068 /* mmc1 */
1069 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1070 { .role = "clk32k", .clk = "mmc1_clk32k" },
1071 };
1072
1073 /* mmc1 dev_attr */
1074 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1075 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1076 };
1077
1078 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1079 .name = "mmc1",
1080 .class = &dra7xx_mmc_hwmod_class,
1081 .clkdm_name = "l3init_clkdm",
1082 .main_clk = "mmc1_fclk_div",
1083 .prcm = {
1084 .omap4 = {
1085 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1086 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1087 .modulemode = MODULEMODE_SWCTRL,
1088 },
1089 },
1090 .opt_clks = mmc1_opt_clks,
1091 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1092 .dev_attr = &mmc1_dev_attr,
1093 };
1094
1095 /* mmc2 */
1096 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1097 { .role = "clk32k", .clk = "mmc2_clk32k" },
1098 };
1099
1100 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1101 .name = "mmc2",
1102 .class = &dra7xx_mmc_hwmod_class,
1103 .clkdm_name = "l3init_clkdm",
1104 .main_clk = "mmc2_fclk_div",
1105 .prcm = {
1106 .omap4 = {
1107 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1108 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1109 .modulemode = MODULEMODE_SWCTRL,
1110 },
1111 },
1112 .opt_clks = mmc2_opt_clks,
1113 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1114 };
1115
1116 /* mmc3 */
1117 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1118 { .role = "clk32k", .clk = "mmc3_clk32k" },
1119 };
1120
1121 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1122 .name = "mmc3",
1123 .class = &dra7xx_mmc_hwmod_class,
1124 .clkdm_name = "l4per_clkdm",
1125 .main_clk = "mmc3_gfclk_div",
1126 .prcm = {
1127 .omap4 = {
1128 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1129 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1130 .modulemode = MODULEMODE_SWCTRL,
1131 },
1132 },
1133 .opt_clks = mmc3_opt_clks,
1134 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1135 };
1136
1137 /* mmc4 */
1138 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1139 { .role = "clk32k", .clk = "mmc4_clk32k" },
1140 };
1141
1142 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1143 .name = "mmc4",
1144 .class = &dra7xx_mmc_hwmod_class,
1145 .clkdm_name = "l4per_clkdm",
1146 .main_clk = "mmc4_gfclk_div",
1147 .prcm = {
1148 .omap4 = {
1149 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1150 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1151 .modulemode = MODULEMODE_SWCTRL,
1152 },
1153 },
1154 .opt_clks = mmc4_opt_clks,
1155 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1156 };
1157
1158 /*
1159 * 'mpu' class
1160 *
1161 */
1162
1163 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1164 .name = "mpu",
1165 };
1166
1167 /* mpu */
1168 static struct omap_hwmod dra7xx_mpu_hwmod = {
1169 .name = "mpu",
1170 .class = &dra7xx_mpu_hwmod_class,
1171 .clkdm_name = "mpu_clkdm",
1172 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1173 .main_clk = "dpll_mpu_m2_ck",
1174 .prcm = {
1175 .omap4 = {
1176 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1177 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1178 },
1179 },
1180 };
1181
1182 /*
1183 * 'ocp2scp' class
1184 *
1185 */
1186
1187 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1188 .rev_offs = 0x0000,
1189 .sysc_offs = 0x0010,
1190 .syss_offs = 0x0014,
1191 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1192 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1193 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1194 SIDLE_SMART_WKUP),
1195 .sysc_fields = &omap_hwmod_sysc_type1,
1196 };
1197
1198 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1199 .name = "ocp2scp",
1200 .sysc = &dra7xx_ocp2scp_sysc,
1201 };
1202
1203 /* ocp2scp1 */
1204 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1205 .name = "ocp2scp1",
1206 .class = &dra7xx_ocp2scp_hwmod_class,
1207 .clkdm_name = "l3init_clkdm",
1208 .main_clk = "l4_root_clk_div",
1209 .prcm = {
1210 .omap4 = {
1211 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1212 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1213 .modulemode = MODULEMODE_HWCTRL,
1214 },
1215 },
1216 };
1217
1218 /*
1219 * 'qspi' class
1220 *
1221 */
1222
1223 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1224 .sysc_offs = 0x0010,
1225 .sysc_flags = SYSC_HAS_SIDLEMODE,
1226 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1227 SIDLE_SMART_WKUP),
1228 .sysc_fields = &omap_hwmod_sysc_type2,
1229 };
1230
1231 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1232 .name = "qspi",
1233 .sysc = &dra7xx_qspi_sysc,
1234 };
1235
1236 /* qspi */
1237 static struct omap_hwmod dra7xx_qspi_hwmod = {
1238 .name = "qspi",
1239 .class = &dra7xx_qspi_hwmod_class,
1240 .clkdm_name = "l4per2_clkdm",
1241 .main_clk = "qspi_gfclk_div",
1242 .prcm = {
1243 .omap4 = {
1244 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1245 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1246 .modulemode = MODULEMODE_SWCTRL,
1247 },
1248 },
1249 };
1250
1251 /*
1252 * 'sata' class
1253 *
1254 */
1255
1256 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1257 .sysc_offs = 0x0000,
1258 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1259 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1260 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1261 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1262 .sysc_fields = &omap_hwmod_sysc_type2,
1263 };
1264
1265 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1266 .name = "sata",
1267 .sysc = &dra7xx_sata_sysc,
1268 };
1269
1270 /* sata */
1271 static struct omap_hwmod_opt_clk sata_opt_clks[] = {
1272 { .role = "ref_clk", .clk = "sata_ref_clk" },
1273 };
1274
1275 static struct omap_hwmod dra7xx_sata_hwmod = {
1276 .name = "sata",
1277 .class = &dra7xx_sata_hwmod_class,
1278 .clkdm_name = "l3init_clkdm",
1279 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1280 .main_clk = "func_48m_fclk",
1281 .prcm = {
1282 .omap4 = {
1283 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1284 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1285 .modulemode = MODULEMODE_SWCTRL,
1286 },
1287 },
1288 .opt_clks = sata_opt_clks,
1289 .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
1290 };
1291
1292 /*
1293 * 'smartreflex' class
1294 *
1295 */
1296
1297 /* The IP is not compliant to type1 / type2 scheme */
1298 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1299 .sidle_shift = 24,
1300 .enwkup_shift = 26,
1301 };
1302
1303 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1304 .sysc_offs = 0x0038,
1305 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1306 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1307 SIDLE_SMART_WKUP),
1308 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1309 };
1310
1311 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1312 .name = "smartreflex",
1313 .sysc = &dra7xx_smartreflex_sysc,
1314 .rev = 2,
1315 };
1316
1317 /* smartreflex_core */
1318 /* smartreflex_core dev_attr */
1319 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1320 .sensor_voltdm_name = "core",
1321 };
1322
1323 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1324 .name = "smartreflex_core",
1325 .class = &dra7xx_smartreflex_hwmod_class,
1326 .clkdm_name = "coreaon_clkdm",
1327 .main_clk = "wkupaon_iclk_mux",
1328 .prcm = {
1329 .omap4 = {
1330 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1331 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1332 .modulemode = MODULEMODE_SWCTRL,
1333 },
1334 },
1335 .dev_attr = &smartreflex_core_dev_attr,
1336 };
1337
1338 /* smartreflex_mpu */
1339 /* smartreflex_mpu dev_attr */
1340 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1341 .sensor_voltdm_name = "mpu",
1342 };
1343
1344 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1345 .name = "smartreflex_mpu",
1346 .class = &dra7xx_smartreflex_hwmod_class,
1347 .clkdm_name = "coreaon_clkdm",
1348 .main_clk = "wkupaon_iclk_mux",
1349 .prcm = {
1350 .omap4 = {
1351 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1352 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1353 .modulemode = MODULEMODE_SWCTRL,
1354 },
1355 },
1356 .dev_attr = &smartreflex_mpu_dev_attr,
1357 };
1358
1359 /*
1360 * 'spinlock' class
1361 *
1362 */
1363
1364 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1365 .rev_offs = 0x0000,
1366 .sysc_offs = 0x0010,
1367 .syss_offs = 0x0014,
1368 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1369 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1370 SYSS_HAS_RESET_STATUS),
1371 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1372 .sysc_fields = &omap_hwmod_sysc_type1,
1373 };
1374
1375 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1376 .name = "spinlock",
1377 .sysc = &dra7xx_spinlock_sysc,
1378 };
1379
1380 /* spinlock */
1381 static struct omap_hwmod dra7xx_spinlock_hwmod = {
1382 .name = "spinlock",
1383 .class = &dra7xx_spinlock_hwmod_class,
1384 .clkdm_name = "l4cfg_clkdm",
1385 .main_clk = "l3_iclk_div",
1386 .prcm = {
1387 .omap4 = {
1388 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1389 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1390 },
1391 },
1392 };
1393
1394 /*
1395 * 'timer' class
1396 *
1397 * This class contains several variants: ['timer_1ms', 'timer_secure',
1398 * 'timer']
1399 */
1400
1401 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1402 .rev_offs = 0x0000,
1403 .sysc_offs = 0x0010,
1404 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1405 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1406 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1407 SIDLE_SMART_WKUP),
1408 .sysc_fields = &omap_hwmod_sysc_type2,
1409 };
1410
1411 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1412 .name = "timer",
1413 .sysc = &dra7xx_timer_1ms_sysc,
1414 };
1415
1416 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
1417 .rev_offs = 0x0000,
1418 .sysc_offs = 0x0010,
1419 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1420 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1421 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1422 SIDLE_SMART_WKUP),
1423 .sysc_fields = &omap_hwmod_sysc_type2,
1424 };
1425
1426 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
1427 .name = "timer",
1428 .sysc = &dra7xx_timer_secure_sysc,
1429 };
1430
1431 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1432 .rev_offs = 0x0000,
1433 .sysc_offs = 0x0010,
1434 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1435 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1436 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1437 SIDLE_SMART_WKUP),
1438 .sysc_fields = &omap_hwmod_sysc_type2,
1439 };
1440
1441 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1442 .name = "timer",
1443 .sysc = &dra7xx_timer_sysc,
1444 };
1445
1446 /* timer1 */
1447 static struct omap_hwmod dra7xx_timer1_hwmod = {
1448 .name = "timer1",
1449 .class = &dra7xx_timer_1ms_hwmod_class,
1450 .clkdm_name = "wkupaon_clkdm",
1451 .main_clk = "timer1_gfclk_mux",
1452 .prcm = {
1453 .omap4 = {
1454 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1455 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1456 .modulemode = MODULEMODE_SWCTRL,
1457 },
1458 },
1459 };
1460
1461 /* timer2 */
1462 static struct omap_hwmod dra7xx_timer2_hwmod = {
1463 .name = "timer2",
1464 .class = &dra7xx_timer_1ms_hwmod_class,
1465 .clkdm_name = "l4per_clkdm",
1466 .main_clk = "timer2_gfclk_mux",
1467 .prcm = {
1468 .omap4 = {
1469 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1470 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1471 .modulemode = MODULEMODE_SWCTRL,
1472 },
1473 },
1474 };
1475
1476 /* timer3 */
1477 static struct omap_hwmod dra7xx_timer3_hwmod = {
1478 .name = "timer3",
1479 .class = &dra7xx_timer_hwmod_class,
1480 .clkdm_name = "l4per_clkdm",
1481 .main_clk = "timer3_gfclk_mux",
1482 .prcm = {
1483 .omap4 = {
1484 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1485 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1486 .modulemode = MODULEMODE_SWCTRL,
1487 },
1488 },
1489 };
1490
1491 /* timer4 */
1492 static struct omap_hwmod dra7xx_timer4_hwmod = {
1493 .name = "timer4",
1494 .class = &dra7xx_timer_secure_hwmod_class,
1495 .clkdm_name = "l4per_clkdm",
1496 .main_clk = "timer4_gfclk_mux",
1497 .prcm = {
1498 .omap4 = {
1499 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1500 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1501 .modulemode = MODULEMODE_SWCTRL,
1502 },
1503 },
1504 };
1505
1506 /* timer5 */
1507 static struct omap_hwmod dra7xx_timer5_hwmod = {
1508 .name = "timer5",
1509 .class = &dra7xx_timer_hwmod_class,
1510 .clkdm_name = "ipu_clkdm",
1511 .main_clk = "timer5_gfclk_mux",
1512 .prcm = {
1513 .omap4 = {
1514 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1515 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1516 .modulemode = MODULEMODE_SWCTRL,
1517 },
1518 },
1519 };
1520
1521 /* timer6 */
1522 static struct omap_hwmod dra7xx_timer6_hwmod = {
1523 .name = "timer6",
1524 .class = &dra7xx_timer_hwmod_class,
1525 .clkdm_name = "ipu_clkdm",
1526 .main_clk = "timer6_gfclk_mux",
1527 .prcm = {
1528 .omap4 = {
1529 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1530 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1531 .modulemode = MODULEMODE_SWCTRL,
1532 },
1533 },
1534 };
1535
1536 /* timer7 */
1537 static struct omap_hwmod dra7xx_timer7_hwmod = {
1538 .name = "timer7",
1539 .class = &dra7xx_timer_hwmod_class,
1540 .clkdm_name = "ipu_clkdm",
1541 .main_clk = "timer7_gfclk_mux",
1542 .prcm = {
1543 .omap4 = {
1544 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1545 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1546 .modulemode = MODULEMODE_SWCTRL,
1547 },
1548 },
1549 };
1550
1551 /* timer8 */
1552 static struct omap_hwmod dra7xx_timer8_hwmod = {
1553 .name = "timer8",
1554 .class = &dra7xx_timer_hwmod_class,
1555 .clkdm_name = "ipu_clkdm",
1556 .main_clk = "timer8_gfclk_mux",
1557 .prcm = {
1558 .omap4 = {
1559 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1560 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1561 .modulemode = MODULEMODE_SWCTRL,
1562 },
1563 },
1564 };
1565
1566 /* timer9 */
1567 static struct omap_hwmod dra7xx_timer9_hwmod = {
1568 .name = "timer9",
1569 .class = &dra7xx_timer_hwmod_class,
1570 .clkdm_name = "l4per_clkdm",
1571 .main_clk = "timer9_gfclk_mux",
1572 .prcm = {
1573 .omap4 = {
1574 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1575 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1576 .modulemode = MODULEMODE_SWCTRL,
1577 },
1578 },
1579 };
1580
1581 /* timer10 */
1582 static struct omap_hwmod dra7xx_timer10_hwmod = {
1583 .name = "timer10",
1584 .class = &dra7xx_timer_1ms_hwmod_class,
1585 .clkdm_name = "l4per_clkdm",
1586 .main_clk = "timer10_gfclk_mux",
1587 .prcm = {
1588 .omap4 = {
1589 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1590 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1591 .modulemode = MODULEMODE_SWCTRL,
1592 },
1593 },
1594 };
1595
1596 /* timer11 */
1597 static struct omap_hwmod dra7xx_timer11_hwmod = {
1598 .name = "timer11",
1599 .class = &dra7xx_timer_hwmod_class,
1600 .clkdm_name = "l4per_clkdm",
1601 .main_clk = "timer11_gfclk_mux",
1602 .prcm = {
1603 .omap4 = {
1604 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1605 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1606 .modulemode = MODULEMODE_SWCTRL,
1607 },
1608 },
1609 };
1610
1611 /*
1612 * 'uart' class
1613 *
1614 */
1615
1616 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1617 .rev_offs = 0x0050,
1618 .sysc_offs = 0x0054,
1619 .syss_offs = 0x0058,
1620 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1621 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1622 SYSS_HAS_RESET_STATUS),
1623 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1624 SIDLE_SMART_WKUP),
1625 .sysc_fields = &omap_hwmod_sysc_type1,
1626 };
1627
1628 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
1629 .name = "uart",
1630 .sysc = &dra7xx_uart_sysc,
1631 };
1632
1633 /* uart1 */
1634 static struct omap_hwmod dra7xx_uart1_hwmod = {
1635 .name = "uart1",
1636 .class = &dra7xx_uart_hwmod_class,
1637 .clkdm_name = "l4per_clkdm",
1638 .main_clk = "uart1_gfclk_mux",
1639 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
1640 .prcm = {
1641 .omap4 = {
1642 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1643 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1644 .modulemode = MODULEMODE_SWCTRL,
1645 },
1646 },
1647 };
1648
1649 /* uart2 */
1650 static struct omap_hwmod dra7xx_uart2_hwmod = {
1651 .name = "uart2",
1652 .class = &dra7xx_uart_hwmod_class,
1653 .clkdm_name = "l4per_clkdm",
1654 .main_clk = "uart2_gfclk_mux",
1655 .flags = HWMOD_SWSUP_SIDLE_ACT,
1656 .prcm = {
1657 .omap4 = {
1658 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1659 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1660 .modulemode = MODULEMODE_SWCTRL,
1661 },
1662 },
1663 };
1664
1665 /* uart3 */
1666 static struct omap_hwmod dra7xx_uart3_hwmod = {
1667 .name = "uart3",
1668 .class = &dra7xx_uart_hwmod_class,
1669 .clkdm_name = "l4per_clkdm",
1670 .main_clk = "uart3_gfclk_mux",
1671 .flags = HWMOD_SWSUP_SIDLE_ACT,
1672 .prcm = {
1673 .omap4 = {
1674 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1675 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1676 .modulemode = MODULEMODE_SWCTRL,
1677 },
1678 },
1679 };
1680
1681 /* uart4 */
1682 static struct omap_hwmod dra7xx_uart4_hwmod = {
1683 .name = "uart4",
1684 .class = &dra7xx_uart_hwmod_class,
1685 .clkdm_name = "l4per_clkdm",
1686 .main_clk = "uart4_gfclk_mux",
1687 .flags = HWMOD_SWSUP_SIDLE_ACT,
1688 .prcm = {
1689 .omap4 = {
1690 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1691 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1692 .modulemode = MODULEMODE_SWCTRL,
1693 },
1694 },
1695 };
1696
1697 /* uart5 */
1698 static struct omap_hwmod dra7xx_uart5_hwmod = {
1699 .name = "uart5",
1700 .class = &dra7xx_uart_hwmod_class,
1701 .clkdm_name = "l4per_clkdm",
1702 .main_clk = "uart5_gfclk_mux",
1703 .flags = HWMOD_SWSUP_SIDLE_ACT,
1704 .prcm = {
1705 .omap4 = {
1706 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1707 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1708 .modulemode = MODULEMODE_SWCTRL,
1709 },
1710 },
1711 };
1712
1713 /* uart6 */
1714 static struct omap_hwmod dra7xx_uart6_hwmod = {
1715 .name = "uart6",
1716 .class = &dra7xx_uart_hwmod_class,
1717 .clkdm_name = "ipu_clkdm",
1718 .main_clk = "uart6_gfclk_mux",
1719 .flags = HWMOD_SWSUP_SIDLE_ACT,
1720 .prcm = {
1721 .omap4 = {
1722 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
1723 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
1724 .modulemode = MODULEMODE_SWCTRL,
1725 },
1726 },
1727 };
1728
1729 /*
1730 * 'usb_otg_ss' class
1731 *
1732 */
1733
1734 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
1735 .name = "usb_otg_ss",
1736 };
1737
1738 /* usb_otg_ss1 */
1739 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
1740 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
1741 };
1742
1743 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
1744 .name = "usb_otg_ss1",
1745 .class = &dra7xx_usb_otg_ss_hwmod_class,
1746 .clkdm_name = "l3init_clkdm",
1747 .main_clk = "dpll_core_h13x2_ck",
1748 .prcm = {
1749 .omap4 = {
1750 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
1751 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
1752 .modulemode = MODULEMODE_HWCTRL,
1753 },
1754 },
1755 .opt_clks = usb_otg_ss1_opt_clks,
1756 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
1757 };
1758
1759 /* usb_otg_ss2 */
1760 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
1761 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
1762 };
1763
1764 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
1765 .name = "usb_otg_ss2",
1766 .class = &dra7xx_usb_otg_ss_hwmod_class,
1767 .clkdm_name = "l3init_clkdm",
1768 .main_clk = "dpll_core_h13x2_ck",
1769 .prcm = {
1770 .omap4 = {
1771 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
1772 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
1773 .modulemode = MODULEMODE_HWCTRL,
1774 },
1775 },
1776 .opt_clks = usb_otg_ss2_opt_clks,
1777 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
1778 };
1779
1780 /* usb_otg_ss3 */
1781 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
1782 .name = "usb_otg_ss3",
1783 .class = &dra7xx_usb_otg_ss_hwmod_class,
1784 .clkdm_name = "l3init_clkdm",
1785 .main_clk = "dpll_core_h13x2_ck",
1786 .prcm = {
1787 .omap4 = {
1788 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
1789 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
1790 .modulemode = MODULEMODE_HWCTRL,
1791 },
1792 },
1793 };
1794
1795 /* usb_otg_ss4 */
1796 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
1797 .name = "usb_otg_ss4",
1798 .class = &dra7xx_usb_otg_ss_hwmod_class,
1799 .clkdm_name = "l3init_clkdm",
1800 .main_clk = "dpll_core_h13x2_ck",
1801 .prcm = {
1802 .omap4 = {
1803 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
1804 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
1805 .modulemode = MODULEMODE_HWCTRL,
1806 },
1807 },
1808 };
1809
1810 /*
1811 * 'vcp' class
1812 *
1813 */
1814
1815 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
1816 .name = "vcp",
1817 };
1818
1819 /* vcp1 */
1820 static struct omap_hwmod dra7xx_vcp1_hwmod = {
1821 .name = "vcp1",
1822 .class = &dra7xx_vcp_hwmod_class,
1823 .clkdm_name = "l3main1_clkdm",
1824 .main_clk = "l3_iclk_div",
1825 .prcm = {
1826 .omap4 = {
1827 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
1828 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
1829 },
1830 },
1831 };
1832
1833 /* vcp2 */
1834 static struct omap_hwmod dra7xx_vcp2_hwmod = {
1835 .name = "vcp2",
1836 .class = &dra7xx_vcp_hwmod_class,
1837 .clkdm_name = "l3main1_clkdm",
1838 .main_clk = "l3_iclk_div",
1839 .prcm = {
1840 .omap4 = {
1841 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
1842 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
1843 },
1844 },
1845 };
1846
1847 /*
1848 * 'wd_timer' class
1849 *
1850 */
1851
1852 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
1853 .rev_offs = 0x0000,
1854 .sysc_offs = 0x0010,
1855 .syss_offs = 0x0014,
1856 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1857 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1858 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1859 SIDLE_SMART_WKUP),
1860 .sysc_fields = &omap_hwmod_sysc_type1,
1861 };
1862
1863 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
1864 .name = "wd_timer",
1865 .sysc = &dra7xx_wd_timer_sysc,
1866 .pre_shutdown = &omap2_wd_timer_disable,
1867 .reset = &omap2_wd_timer_reset,
1868 };
1869
1870 /* wd_timer2 */
1871 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
1872 .name = "wd_timer2",
1873 .class = &dra7xx_wd_timer_hwmod_class,
1874 .clkdm_name = "wkupaon_clkdm",
1875 .main_clk = "sys_32k_ck",
1876 .prcm = {
1877 .omap4 = {
1878 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1879 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1880 .modulemode = MODULEMODE_SWCTRL,
1881 },
1882 },
1883 };
1884
1885
1886 /*
1887 * Interfaces
1888 */
1889
1890 /* l3_main_2 -> l3_instr */
1891 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
1892 .master = &dra7xx_l3_main_2_hwmod,
1893 .slave = &dra7xx_l3_instr_hwmod,
1894 .clk = "l3_iclk_div",
1895 .user = OCP_USER_MPU | OCP_USER_SDMA,
1896 };
1897
1898 /* l4_cfg -> l3_main_1 */
1899 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
1900 .master = &dra7xx_l4_cfg_hwmod,
1901 .slave = &dra7xx_l3_main_1_hwmod,
1902 .clk = "l3_iclk_div",
1903 .user = OCP_USER_MPU | OCP_USER_SDMA,
1904 };
1905
1906 /* mpu -> l3_main_1 */
1907 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
1908 .master = &dra7xx_mpu_hwmod,
1909 .slave = &dra7xx_l3_main_1_hwmod,
1910 .clk = "l3_iclk_div",
1911 .user = OCP_USER_MPU,
1912 };
1913
1914 /* l3_main_1 -> l3_main_2 */
1915 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
1916 .master = &dra7xx_l3_main_1_hwmod,
1917 .slave = &dra7xx_l3_main_2_hwmod,
1918 .clk = "l3_iclk_div",
1919 .user = OCP_USER_MPU,
1920 };
1921
1922 /* l4_cfg -> l3_main_2 */
1923 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
1924 .master = &dra7xx_l4_cfg_hwmod,
1925 .slave = &dra7xx_l3_main_2_hwmod,
1926 .clk = "l3_iclk_div",
1927 .user = OCP_USER_MPU | OCP_USER_SDMA,
1928 };
1929
1930 /* l3_main_1 -> l4_cfg */
1931 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
1932 .master = &dra7xx_l3_main_1_hwmod,
1933 .slave = &dra7xx_l4_cfg_hwmod,
1934 .clk = "l3_iclk_div",
1935 .user = OCP_USER_MPU | OCP_USER_SDMA,
1936 };
1937
1938 /* l3_main_1 -> l4_per1 */
1939 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
1940 .master = &dra7xx_l3_main_1_hwmod,
1941 .slave = &dra7xx_l4_per1_hwmod,
1942 .clk = "l3_iclk_div",
1943 .user = OCP_USER_MPU | OCP_USER_SDMA,
1944 };
1945
1946 /* l3_main_1 -> l4_per2 */
1947 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
1948 .master = &dra7xx_l3_main_1_hwmod,
1949 .slave = &dra7xx_l4_per2_hwmod,
1950 .clk = "l3_iclk_div",
1951 .user = OCP_USER_MPU | OCP_USER_SDMA,
1952 };
1953
1954 /* l3_main_1 -> l4_per3 */
1955 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
1956 .master = &dra7xx_l3_main_1_hwmod,
1957 .slave = &dra7xx_l4_per3_hwmod,
1958 .clk = "l3_iclk_div",
1959 .user = OCP_USER_MPU | OCP_USER_SDMA,
1960 };
1961
1962 /* l3_main_1 -> l4_wkup */
1963 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
1964 .master = &dra7xx_l3_main_1_hwmod,
1965 .slave = &dra7xx_l4_wkup_hwmod,
1966 .clk = "wkupaon_iclk_mux",
1967 .user = OCP_USER_MPU | OCP_USER_SDMA,
1968 };
1969
1970 /* l4_per2 -> atl */
1971 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
1972 .master = &dra7xx_l4_per2_hwmod,
1973 .slave = &dra7xx_atl_hwmod,
1974 .clk = "l3_iclk_div",
1975 .user = OCP_USER_MPU | OCP_USER_SDMA,
1976 };
1977
1978 /* l3_main_1 -> bb2d */
1979 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
1980 .master = &dra7xx_l3_main_1_hwmod,
1981 .slave = &dra7xx_bb2d_hwmod,
1982 .clk = "l3_iclk_div",
1983 .user = OCP_USER_MPU | OCP_USER_SDMA,
1984 };
1985
1986 /* l4_wkup -> counter_32k */
1987 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
1988 .master = &dra7xx_l4_wkup_hwmod,
1989 .slave = &dra7xx_counter_32k_hwmod,
1990 .clk = "wkupaon_iclk_mux",
1991 .user = OCP_USER_MPU | OCP_USER_SDMA,
1992 };
1993
1994 /* l4_wkup -> ctrl_module_wkup */
1995 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
1996 .master = &dra7xx_l4_wkup_hwmod,
1997 .slave = &dra7xx_ctrl_module_wkup_hwmod,
1998 .clk = "wkupaon_iclk_mux",
1999 .user = OCP_USER_MPU | OCP_USER_SDMA,
2000 };
2001
2002 /* l4_wkup -> dcan1 */
2003 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2004 .master = &dra7xx_l4_wkup_hwmod,
2005 .slave = &dra7xx_dcan1_hwmod,
2006 .clk = "wkupaon_iclk_mux",
2007 .user = OCP_USER_MPU | OCP_USER_SDMA,
2008 };
2009
2010 /* l4_per2 -> dcan2 */
2011 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2012 .master = &dra7xx_l4_per2_hwmod,
2013 .slave = &dra7xx_dcan2_hwmod,
2014 .clk = "l3_iclk_div",
2015 .user = OCP_USER_MPU | OCP_USER_SDMA,
2016 };
2017
2018 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2019 {
2020 .pa_start = 0x4a056000,
2021 .pa_end = 0x4a056fff,
2022 .flags = ADDR_TYPE_RT
2023 },
2024 { }
2025 };
2026
2027 /* l4_cfg -> dma_system */
2028 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2029 .master = &dra7xx_l4_cfg_hwmod,
2030 .slave = &dra7xx_dma_system_hwmod,
2031 .clk = "l3_iclk_div",
2032 .addr = dra7xx_dma_system_addrs,
2033 .user = OCP_USER_MPU | OCP_USER_SDMA,
2034 };
2035
2036 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2037 {
2038 .name = "family",
2039 .pa_start = 0x58000000,
2040 .pa_end = 0x5800007f,
2041 .flags = ADDR_TYPE_RT
2042 },
2043 };
2044
2045 /* l3_main_1 -> dss */
2046 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2047 .master = &dra7xx_l3_main_1_hwmod,
2048 .slave = &dra7xx_dss_hwmod,
2049 .clk = "l3_iclk_div",
2050 .addr = dra7xx_dss_addrs,
2051 .user = OCP_USER_MPU | OCP_USER_SDMA,
2052 };
2053
2054 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2055 {
2056 .name = "dispc",
2057 .pa_start = 0x58001000,
2058 .pa_end = 0x58001fff,
2059 .flags = ADDR_TYPE_RT
2060 },
2061 };
2062
2063 /* l3_main_1 -> dispc */
2064 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2065 .master = &dra7xx_l3_main_1_hwmod,
2066 .slave = &dra7xx_dss_dispc_hwmod,
2067 .clk = "l3_iclk_div",
2068 .addr = dra7xx_dss_dispc_addrs,
2069 .user = OCP_USER_MPU | OCP_USER_SDMA,
2070 };
2071
2072 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2073 {
2074 .name = "hdmi_wp",
2075 .pa_start = 0x58040000,
2076 .pa_end = 0x580400ff,
2077 .flags = ADDR_TYPE_RT
2078 },
2079 { }
2080 };
2081
2082 /* l3_main_1 -> dispc */
2083 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2084 .master = &dra7xx_l3_main_1_hwmod,
2085 .slave = &dra7xx_dss_hdmi_hwmod,
2086 .clk = "l3_iclk_div",
2087 .addr = dra7xx_dss_hdmi_addrs,
2088 .user = OCP_USER_MPU | OCP_USER_SDMA,
2089 };
2090
2091 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2092 {
2093 .pa_start = 0x48078000,
2094 .pa_end = 0x48078fff,
2095 .flags = ADDR_TYPE_RT
2096 },
2097 { }
2098 };
2099
2100 /* l4_per1 -> elm */
2101 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2102 .master = &dra7xx_l4_per1_hwmod,
2103 .slave = &dra7xx_elm_hwmod,
2104 .clk = "l3_iclk_div",
2105 .addr = dra7xx_elm_addrs,
2106 .user = OCP_USER_MPU | OCP_USER_SDMA,
2107 };
2108
2109 /* l4_wkup -> gpio1 */
2110 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2111 .master = &dra7xx_l4_wkup_hwmod,
2112 .slave = &dra7xx_gpio1_hwmod,
2113 .clk = "wkupaon_iclk_mux",
2114 .user = OCP_USER_MPU | OCP_USER_SDMA,
2115 };
2116
2117 /* l4_per1 -> gpio2 */
2118 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2119 .master = &dra7xx_l4_per1_hwmod,
2120 .slave = &dra7xx_gpio2_hwmod,
2121 .clk = "l3_iclk_div",
2122 .user = OCP_USER_MPU | OCP_USER_SDMA,
2123 };
2124
2125 /* l4_per1 -> gpio3 */
2126 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2127 .master = &dra7xx_l4_per1_hwmod,
2128 .slave = &dra7xx_gpio3_hwmod,
2129 .clk = "l3_iclk_div",
2130 .user = OCP_USER_MPU | OCP_USER_SDMA,
2131 };
2132
2133 /* l4_per1 -> gpio4 */
2134 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2135 .master = &dra7xx_l4_per1_hwmod,
2136 .slave = &dra7xx_gpio4_hwmod,
2137 .clk = "l3_iclk_div",
2138 .user = OCP_USER_MPU | OCP_USER_SDMA,
2139 };
2140
2141 /* l4_per1 -> gpio5 */
2142 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2143 .master = &dra7xx_l4_per1_hwmod,
2144 .slave = &dra7xx_gpio5_hwmod,
2145 .clk = "l3_iclk_div",
2146 .user = OCP_USER_MPU | OCP_USER_SDMA,
2147 };
2148
2149 /* l4_per1 -> gpio6 */
2150 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2151 .master = &dra7xx_l4_per1_hwmod,
2152 .slave = &dra7xx_gpio6_hwmod,
2153 .clk = "l3_iclk_div",
2154 .user = OCP_USER_MPU | OCP_USER_SDMA,
2155 };
2156
2157 /* l4_per1 -> gpio7 */
2158 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2159 .master = &dra7xx_l4_per1_hwmod,
2160 .slave = &dra7xx_gpio7_hwmod,
2161 .clk = "l3_iclk_div",
2162 .user = OCP_USER_MPU | OCP_USER_SDMA,
2163 };
2164
2165 /* l4_per1 -> gpio8 */
2166 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2167 .master = &dra7xx_l4_per1_hwmod,
2168 .slave = &dra7xx_gpio8_hwmod,
2169 .clk = "l3_iclk_div",
2170 .user = OCP_USER_MPU | OCP_USER_SDMA,
2171 };
2172
2173 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2174 {
2175 .pa_start = 0x50000000,
2176 .pa_end = 0x500003ff,
2177 .flags = ADDR_TYPE_RT
2178 },
2179 { }
2180 };
2181
2182 /* l3_main_1 -> gpmc */
2183 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2184 .master = &dra7xx_l3_main_1_hwmod,
2185 .slave = &dra7xx_gpmc_hwmod,
2186 .clk = "l3_iclk_div",
2187 .addr = dra7xx_gpmc_addrs,
2188 .user = OCP_USER_MPU | OCP_USER_SDMA,
2189 };
2190
2191 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2192 {
2193 .pa_start = 0x480b2000,
2194 .pa_end = 0x480b201f,
2195 .flags = ADDR_TYPE_RT
2196 },
2197 { }
2198 };
2199
2200 /* l4_per1 -> hdq1w */
2201 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2202 .master = &dra7xx_l4_per1_hwmod,
2203 .slave = &dra7xx_hdq1w_hwmod,
2204 .clk = "l3_iclk_div",
2205 .addr = dra7xx_hdq1w_addrs,
2206 .user = OCP_USER_MPU | OCP_USER_SDMA,
2207 };
2208
2209 /* l4_per1 -> i2c1 */
2210 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2211 .master = &dra7xx_l4_per1_hwmod,
2212 .slave = &dra7xx_i2c1_hwmod,
2213 .clk = "l3_iclk_div",
2214 .user = OCP_USER_MPU | OCP_USER_SDMA,
2215 };
2216
2217 /* l4_per1 -> i2c2 */
2218 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2219 .master = &dra7xx_l4_per1_hwmod,
2220 .slave = &dra7xx_i2c2_hwmod,
2221 .clk = "l3_iclk_div",
2222 .user = OCP_USER_MPU | OCP_USER_SDMA,
2223 };
2224
2225 /* l4_per1 -> i2c3 */
2226 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2227 .master = &dra7xx_l4_per1_hwmod,
2228 .slave = &dra7xx_i2c3_hwmod,
2229 .clk = "l3_iclk_div",
2230 .user = OCP_USER_MPU | OCP_USER_SDMA,
2231 };
2232
2233 /* l4_per1 -> i2c4 */
2234 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2235 .master = &dra7xx_l4_per1_hwmod,
2236 .slave = &dra7xx_i2c4_hwmod,
2237 .clk = "l3_iclk_div",
2238 .user = OCP_USER_MPU | OCP_USER_SDMA,
2239 };
2240
2241 /* l4_per1 -> i2c5 */
2242 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2243 .master = &dra7xx_l4_per1_hwmod,
2244 .slave = &dra7xx_i2c5_hwmod,
2245 .clk = "l3_iclk_div",
2246 .user = OCP_USER_MPU | OCP_USER_SDMA,
2247 };
2248
2249 /* l4_per1 -> mcspi1 */
2250 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2251 .master = &dra7xx_l4_per1_hwmod,
2252 .slave = &dra7xx_mcspi1_hwmod,
2253 .clk = "l3_iclk_div",
2254 .user = OCP_USER_MPU | OCP_USER_SDMA,
2255 };
2256
2257 /* l4_per1 -> mcspi2 */
2258 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2259 .master = &dra7xx_l4_per1_hwmod,
2260 .slave = &dra7xx_mcspi2_hwmod,
2261 .clk = "l3_iclk_div",
2262 .user = OCP_USER_MPU | OCP_USER_SDMA,
2263 };
2264
2265 /* l4_per1 -> mcspi3 */
2266 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2267 .master = &dra7xx_l4_per1_hwmod,
2268 .slave = &dra7xx_mcspi3_hwmod,
2269 .clk = "l3_iclk_div",
2270 .user = OCP_USER_MPU | OCP_USER_SDMA,
2271 };
2272
2273 /* l4_per1 -> mcspi4 */
2274 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2275 .master = &dra7xx_l4_per1_hwmod,
2276 .slave = &dra7xx_mcspi4_hwmod,
2277 .clk = "l3_iclk_div",
2278 .user = OCP_USER_MPU | OCP_USER_SDMA,
2279 };
2280
2281 /* l4_per1 -> mmc1 */
2282 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2283 .master = &dra7xx_l4_per1_hwmod,
2284 .slave = &dra7xx_mmc1_hwmod,
2285 .clk = "l3_iclk_div",
2286 .user = OCP_USER_MPU | OCP_USER_SDMA,
2287 };
2288
2289 /* l4_per1 -> mmc2 */
2290 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2291 .master = &dra7xx_l4_per1_hwmod,
2292 .slave = &dra7xx_mmc2_hwmod,
2293 .clk = "l3_iclk_div",
2294 .user = OCP_USER_MPU | OCP_USER_SDMA,
2295 };
2296
2297 /* l4_per1 -> mmc3 */
2298 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2299 .master = &dra7xx_l4_per1_hwmod,
2300 .slave = &dra7xx_mmc3_hwmod,
2301 .clk = "l3_iclk_div",
2302 .user = OCP_USER_MPU | OCP_USER_SDMA,
2303 };
2304
2305 /* l4_per1 -> mmc4 */
2306 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2307 .master = &dra7xx_l4_per1_hwmod,
2308 .slave = &dra7xx_mmc4_hwmod,
2309 .clk = "l3_iclk_div",
2310 .user = OCP_USER_MPU | OCP_USER_SDMA,
2311 };
2312
2313 /* l4_cfg -> mpu */
2314 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2315 .master = &dra7xx_l4_cfg_hwmod,
2316 .slave = &dra7xx_mpu_hwmod,
2317 .clk = "l3_iclk_div",
2318 .user = OCP_USER_MPU | OCP_USER_SDMA,
2319 };
2320
2321 /* l4_cfg -> ocp2scp1 */
2322 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2323 .master = &dra7xx_l4_cfg_hwmod,
2324 .slave = &dra7xx_ocp2scp1_hwmod,
2325 .clk = "l4_root_clk_div",
2326 .user = OCP_USER_MPU | OCP_USER_SDMA,
2327 };
2328
2329 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2330 {
2331 .pa_start = 0x4b300000,
2332 .pa_end = 0x4b30007f,
2333 .flags = ADDR_TYPE_RT
2334 },
2335 { }
2336 };
2337
2338 /* l3_main_1 -> qspi */
2339 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2340 .master = &dra7xx_l3_main_1_hwmod,
2341 .slave = &dra7xx_qspi_hwmod,
2342 .clk = "l3_iclk_div",
2343 .addr = dra7xx_qspi_addrs,
2344 .user = OCP_USER_MPU | OCP_USER_SDMA,
2345 };
2346
2347 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2348 {
2349 .name = "sysc",
2350 .pa_start = 0x4a141100,
2351 .pa_end = 0x4a141107,
2352 .flags = ADDR_TYPE_RT
2353 },
2354 { }
2355 };
2356
2357 /* l4_cfg -> sata */
2358 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2359 .master = &dra7xx_l4_cfg_hwmod,
2360 .slave = &dra7xx_sata_hwmod,
2361 .clk = "l3_iclk_div",
2362 .addr = dra7xx_sata_addrs,
2363 .user = OCP_USER_MPU | OCP_USER_SDMA,
2364 };
2365
2366 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2367 {
2368 .pa_start = 0x4a0dd000,
2369 .pa_end = 0x4a0dd07f,
2370 .flags = ADDR_TYPE_RT
2371 },
2372 { }
2373 };
2374
2375 /* l4_cfg -> smartreflex_core */
2376 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2377 .master = &dra7xx_l4_cfg_hwmod,
2378 .slave = &dra7xx_smartreflex_core_hwmod,
2379 .clk = "l4_root_clk_div",
2380 .addr = dra7xx_smartreflex_core_addrs,
2381 .user = OCP_USER_MPU | OCP_USER_SDMA,
2382 };
2383
2384 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
2385 {
2386 .pa_start = 0x4a0d9000,
2387 .pa_end = 0x4a0d907f,
2388 .flags = ADDR_TYPE_RT
2389 },
2390 { }
2391 };
2392
2393 /* l4_cfg -> smartreflex_mpu */
2394 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
2395 .master = &dra7xx_l4_cfg_hwmod,
2396 .slave = &dra7xx_smartreflex_mpu_hwmod,
2397 .clk = "l4_root_clk_div",
2398 .addr = dra7xx_smartreflex_mpu_addrs,
2399 .user = OCP_USER_MPU | OCP_USER_SDMA,
2400 };
2401
2402 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
2403 {
2404 .pa_start = 0x4a0f6000,
2405 .pa_end = 0x4a0f6fff,
2406 .flags = ADDR_TYPE_RT
2407 },
2408 { }
2409 };
2410
2411 /* l4_cfg -> spinlock */
2412 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
2413 .master = &dra7xx_l4_cfg_hwmod,
2414 .slave = &dra7xx_spinlock_hwmod,
2415 .clk = "l3_iclk_div",
2416 .addr = dra7xx_spinlock_addrs,
2417 .user = OCP_USER_MPU | OCP_USER_SDMA,
2418 };
2419
2420 /* l4_wkup -> timer1 */
2421 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
2422 .master = &dra7xx_l4_wkup_hwmod,
2423 .slave = &dra7xx_timer1_hwmod,
2424 .clk = "wkupaon_iclk_mux",
2425 .user = OCP_USER_MPU | OCP_USER_SDMA,
2426 };
2427
2428 /* l4_per1 -> timer2 */
2429 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
2430 .master = &dra7xx_l4_per1_hwmod,
2431 .slave = &dra7xx_timer2_hwmod,
2432 .clk = "l3_iclk_div",
2433 .user = OCP_USER_MPU | OCP_USER_SDMA,
2434 };
2435
2436 /* l4_per1 -> timer3 */
2437 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
2438 .master = &dra7xx_l4_per1_hwmod,
2439 .slave = &dra7xx_timer3_hwmod,
2440 .clk = "l3_iclk_div",
2441 .user = OCP_USER_MPU | OCP_USER_SDMA,
2442 };
2443
2444 /* l4_per1 -> timer4 */
2445 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
2446 .master = &dra7xx_l4_per1_hwmod,
2447 .slave = &dra7xx_timer4_hwmod,
2448 .clk = "l3_iclk_div",
2449 .user = OCP_USER_MPU | OCP_USER_SDMA,
2450 };
2451
2452 /* l4_per3 -> timer5 */
2453 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
2454 .master = &dra7xx_l4_per3_hwmod,
2455 .slave = &dra7xx_timer5_hwmod,
2456 .clk = "l3_iclk_div",
2457 .user = OCP_USER_MPU | OCP_USER_SDMA,
2458 };
2459
2460 /* l4_per3 -> timer6 */
2461 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
2462 .master = &dra7xx_l4_per3_hwmod,
2463 .slave = &dra7xx_timer6_hwmod,
2464 .clk = "l3_iclk_div",
2465 .user = OCP_USER_MPU | OCP_USER_SDMA,
2466 };
2467
2468 /* l4_per3 -> timer7 */
2469 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
2470 .master = &dra7xx_l4_per3_hwmod,
2471 .slave = &dra7xx_timer7_hwmod,
2472 .clk = "l3_iclk_div",
2473 .user = OCP_USER_MPU | OCP_USER_SDMA,
2474 };
2475
2476 /* l4_per3 -> timer8 */
2477 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
2478 .master = &dra7xx_l4_per3_hwmod,
2479 .slave = &dra7xx_timer8_hwmod,
2480 .clk = "l3_iclk_div",
2481 .user = OCP_USER_MPU | OCP_USER_SDMA,
2482 };
2483
2484 /* l4_per1 -> timer9 */
2485 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
2486 .master = &dra7xx_l4_per1_hwmod,
2487 .slave = &dra7xx_timer9_hwmod,
2488 .clk = "l3_iclk_div",
2489 .user = OCP_USER_MPU | OCP_USER_SDMA,
2490 };
2491
2492 /* l4_per1 -> timer10 */
2493 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
2494 .master = &dra7xx_l4_per1_hwmod,
2495 .slave = &dra7xx_timer10_hwmod,
2496 .clk = "l3_iclk_div",
2497 .user = OCP_USER_MPU | OCP_USER_SDMA,
2498 };
2499
2500 /* l4_per1 -> timer11 */
2501 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
2502 .master = &dra7xx_l4_per1_hwmod,
2503 .slave = &dra7xx_timer11_hwmod,
2504 .clk = "l3_iclk_div",
2505 .user = OCP_USER_MPU | OCP_USER_SDMA,
2506 };
2507
2508 /* l4_per1 -> uart1 */
2509 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
2510 .master = &dra7xx_l4_per1_hwmod,
2511 .slave = &dra7xx_uart1_hwmod,
2512 .clk = "l3_iclk_div",
2513 .user = OCP_USER_MPU | OCP_USER_SDMA,
2514 };
2515
2516 /* l4_per1 -> uart2 */
2517 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
2518 .master = &dra7xx_l4_per1_hwmod,
2519 .slave = &dra7xx_uart2_hwmod,
2520 .clk = "l3_iclk_div",
2521 .user = OCP_USER_MPU | OCP_USER_SDMA,
2522 };
2523
2524 /* l4_per1 -> uart3 */
2525 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
2526 .master = &dra7xx_l4_per1_hwmod,
2527 .slave = &dra7xx_uart3_hwmod,
2528 .clk = "l3_iclk_div",
2529 .user = OCP_USER_MPU | OCP_USER_SDMA,
2530 };
2531
2532 /* l4_per1 -> uart4 */
2533 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
2534 .master = &dra7xx_l4_per1_hwmod,
2535 .slave = &dra7xx_uart4_hwmod,
2536 .clk = "l3_iclk_div",
2537 .user = OCP_USER_MPU | OCP_USER_SDMA,
2538 };
2539
2540 /* l4_per1 -> uart5 */
2541 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
2542 .master = &dra7xx_l4_per1_hwmod,
2543 .slave = &dra7xx_uart5_hwmod,
2544 .clk = "l3_iclk_div",
2545 .user = OCP_USER_MPU | OCP_USER_SDMA,
2546 };
2547
2548 /* l4_per1 -> uart6 */
2549 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
2550 .master = &dra7xx_l4_per1_hwmod,
2551 .slave = &dra7xx_uart6_hwmod,
2552 .clk = "l3_iclk_div",
2553 .user = OCP_USER_MPU | OCP_USER_SDMA,
2554 };
2555
2556 /* l4_per3 -> usb_otg_ss1 */
2557 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
2558 .master = &dra7xx_l4_per3_hwmod,
2559 .slave = &dra7xx_usb_otg_ss1_hwmod,
2560 .clk = "dpll_core_h13x2_ck",
2561 .user = OCP_USER_MPU | OCP_USER_SDMA,
2562 };
2563
2564 /* l4_per3 -> usb_otg_ss2 */
2565 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
2566 .master = &dra7xx_l4_per3_hwmod,
2567 .slave = &dra7xx_usb_otg_ss2_hwmod,
2568 .clk = "dpll_core_h13x2_ck",
2569 .user = OCP_USER_MPU | OCP_USER_SDMA,
2570 };
2571
2572 /* l4_per3 -> usb_otg_ss3 */
2573 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
2574 .master = &dra7xx_l4_per3_hwmod,
2575 .slave = &dra7xx_usb_otg_ss3_hwmod,
2576 .clk = "dpll_core_h13x2_ck",
2577 .user = OCP_USER_MPU | OCP_USER_SDMA,
2578 };
2579
2580 /* l4_per3 -> usb_otg_ss4 */
2581 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
2582 .master = &dra7xx_l4_per3_hwmod,
2583 .slave = &dra7xx_usb_otg_ss4_hwmod,
2584 .clk = "dpll_core_h13x2_ck",
2585 .user = OCP_USER_MPU | OCP_USER_SDMA,
2586 };
2587
2588 /* l3_main_1 -> vcp1 */
2589 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
2590 .master = &dra7xx_l3_main_1_hwmod,
2591 .slave = &dra7xx_vcp1_hwmod,
2592 .clk = "l3_iclk_div",
2593 .user = OCP_USER_MPU | OCP_USER_SDMA,
2594 };
2595
2596 /* l4_per2 -> vcp1 */
2597 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
2598 .master = &dra7xx_l4_per2_hwmod,
2599 .slave = &dra7xx_vcp1_hwmod,
2600 .clk = "l3_iclk_div",
2601 .user = OCP_USER_MPU | OCP_USER_SDMA,
2602 };
2603
2604 /* l3_main_1 -> vcp2 */
2605 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
2606 .master = &dra7xx_l3_main_1_hwmod,
2607 .slave = &dra7xx_vcp2_hwmod,
2608 .clk = "l3_iclk_div",
2609 .user = OCP_USER_MPU | OCP_USER_SDMA,
2610 };
2611
2612 /* l4_per2 -> vcp2 */
2613 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
2614 .master = &dra7xx_l4_per2_hwmod,
2615 .slave = &dra7xx_vcp2_hwmod,
2616 .clk = "l3_iclk_div",
2617 .user = OCP_USER_MPU | OCP_USER_SDMA,
2618 };
2619
2620 /* l4_wkup -> wd_timer2 */
2621 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
2622 .master = &dra7xx_l4_wkup_hwmod,
2623 .slave = &dra7xx_wd_timer2_hwmod,
2624 .clk = "wkupaon_iclk_mux",
2625 .user = OCP_USER_MPU | OCP_USER_SDMA,
2626 };
2627
2628 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
2629 &dra7xx_l3_main_2__l3_instr,
2630 &dra7xx_l4_cfg__l3_main_1,
2631 &dra7xx_mpu__l3_main_1,
2632 &dra7xx_l3_main_1__l3_main_2,
2633 &dra7xx_l4_cfg__l3_main_2,
2634 &dra7xx_l3_main_1__l4_cfg,
2635 &dra7xx_l3_main_1__l4_per1,
2636 &dra7xx_l3_main_1__l4_per2,
2637 &dra7xx_l3_main_1__l4_per3,
2638 &dra7xx_l3_main_1__l4_wkup,
2639 &dra7xx_l4_per2__atl,
2640 &dra7xx_l3_main_1__bb2d,
2641 &dra7xx_l4_wkup__counter_32k,
2642 &dra7xx_l4_wkup__ctrl_module_wkup,
2643 &dra7xx_l4_wkup__dcan1,
2644 &dra7xx_l4_per2__dcan2,
2645 &dra7xx_l4_cfg__dma_system,
2646 &dra7xx_l3_main_1__dss,
2647 &dra7xx_l3_main_1__dispc,
2648 &dra7xx_l3_main_1__hdmi,
2649 &dra7xx_l4_per1__elm,
2650 &dra7xx_l4_wkup__gpio1,
2651 &dra7xx_l4_per1__gpio2,
2652 &dra7xx_l4_per1__gpio3,
2653 &dra7xx_l4_per1__gpio4,
2654 &dra7xx_l4_per1__gpio5,
2655 &dra7xx_l4_per1__gpio6,
2656 &dra7xx_l4_per1__gpio7,
2657 &dra7xx_l4_per1__gpio8,
2658 &dra7xx_l3_main_1__gpmc,
2659 &dra7xx_l4_per1__hdq1w,
2660 &dra7xx_l4_per1__i2c1,
2661 &dra7xx_l4_per1__i2c2,
2662 &dra7xx_l4_per1__i2c3,
2663 &dra7xx_l4_per1__i2c4,
2664 &dra7xx_l4_per1__i2c5,
2665 &dra7xx_l4_per1__mcspi1,
2666 &dra7xx_l4_per1__mcspi2,
2667 &dra7xx_l4_per1__mcspi3,
2668 &dra7xx_l4_per1__mcspi4,
2669 &dra7xx_l4_per1__mmc1,
2670 &dra7xx_l4_per1__mmc2,
2671 &dra7xx_l4_per1__mmc3,
2672 &dra7xx_l4_per1__mmc4,
2673 &dra7xx_l4_cfg__mpu,
2674 &dra7xx_l4_cfg__ocp2scp1,
2675 &dra7xx_l3_main_1__qspi,
2676 &dra7xx_l4_cfg__sata,
2677 &dra7xx_l4_cfg__smartreflex_core,
2678 &dra7xx_l4_cfg__smartreflex_mpu,
2679 &dra7xx_l4_cfg__spinlock,
2680 &dra7xx_l4_wkup__timer1,
2681 &dra7xx_l4_per1__timer2,
2682 &dra7xx_l4_per1__timer3,
2683 &dra7xx_l4_per1__timer4,
2684 &dra7xx_l4_per3__timer5,
2685 &dra7xx_l4_per3__timer6,
2686 &dra7xx_l4_per3__timer7,
2687 &dra7xx_l4_per3__timer8,
2688 &dra7xx_l4_per1__timer9,
2689 &dra7xx_l4_per1__timer10,
2690 &dra7xx_l4_per1__timer11,
2691 &dra7xx_l4_per1__uart1,
2692 &dra7xx_l4_per1__uart2,
2693 &dra7xx_l4_per1__uart3,
2694 &dra7xx_l4_per1__uart4,
2695 &dra7xx_l4_per1__uart5,
2696 &dra7xx_l4_per1__uart6,
2697 &dra7xx_l4_per3__usb_otg_ss1,
2698 &dra7xx_l4_per3__usb_otg_ss2,
2699 &dra7xx_l4_per3__usb_otg_ss3,
2700 &dra7xx_l4_per3__usb_otg_ss4,
2701 &dra7xx_l3_main_1__vcp1,
2702 &dra7xx_l4_per2__vcp1,
2703 &dra7xx_l3_main_1__vcp2,
2704 &dra7xx_l4_per2__vcp2,
2705 &dra7xx_l4_wkup__wd_timer2,
2706 NULL,
2707 };
2708
2709 int __init dra7xx_hwmod_init(void)
2710 {
2711 omap_hwmod_init();
2712 return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
2713 }
Linux with added FPC-III support