2 * Copyright 2003-2006 Simtec Electronics
3 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #ifdef CONFIG_S3C2410_DMA_DEBUG
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/sched.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/slab.h>
26 #include <linux/errno.h>
30 #include <mach/hardware.h>
34 #include <plat/dma-s3c24xx.h>
35 #include <plat/regs-dma.h>
38 static void __iomem
*dma_base
;
39 static struct kmem_cache
*dma_kmem
;
41 static int dma_channels
;
43 static struct s3c24xx_dma_selection dma_sel
;
46 /* debugging functions */
48 #define BUF_MAGIC (0xcafebabe)
50 #define dmawarn(fmt...) printk(KERN_DEBUG fmt)
52 #define dma_regaddr(chan, reg) ((chan)->regs + (reg))
55 #define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
58 dma_wrreg(struct s3c2410_dma_chan
*chan
, int reg
, unsigned long val
)
60 pr_debug("writing %08x to register %08x\n",(unsigned int)val
,reg
);
61 writel(val
, dma_regaddr(chan
, reg
));
65 #define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
67 /* captured register state for debug */
69 struct s3c2410_dma_regstate
{
74 unsigned long dmsktrig
;
77 #ifdef CONFIG_S3C2410_DMA_DEBUG
81 * simple debug routine to print the current state of the dma registers
85 dmadbg_capture(struct s3c2410_dma_chan
*chan
, struct s3c2410_dma_regstate
*regs
)
87 regs
->dcsrc
= dma_rdreg(chan
, S3C2410_DMA_DCSRC
);
88 regs
->disrc
= dma_rdreg(chan
, S3C2410_DMA_DISRC
);
89 regs
->dstat
= dma_rdreg(chan
, S3C2410_DMA_DSTAT
);
90 regs
->dcon
= dma_rdreg(chan
, S3C2410_DMA_DCON
);
91 regs
->dmsktrig
= dma_rdreg(chan
, S3C2410_DMA_DMASKTRIG
);
95 dmadbg_dumpregs(const char *fname
, int line
, struct s3c2410_dma_chan
*chan
,
96 struct s3c2410_dma_regstate
*regs
)
98 printk(KERN_DEBUG
"dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
99 chan
->number
, fname
, line
,
100 regs
->dcsrc
, regs
->disrc
, regs
->dstat
, regs
->dmsktrig
,
105 dmadbg_showchan(const char *fname
, int line
, struct s3c2410_dma_chan
*chan
)
107 struct s3c2410_dma_regstate state
;
109 dmadbg_capture(chan
, &state
);
111 printk(KERN_DEBUG
"dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
112 chan
->number
, fname
, line
, chan
->load_state
,
113 chan
->curr
, chan
->next
, chan
->end
);
115 dmadbg_dumpregs(fname
, line
, chan
, &state
);
119 dmadbg_showregs(const char *fname
, int line
, struct s3c2410_dma_chan
*chan
)
121 struct s3c2410_dma_regstate state
;
123 dmadbg_capture(chan
, &state
);
124 dmadbg_dumpregs(fname
, line
, chan
, &state
);
127 #define dbg_showregs(chan) dmadbg_showregs(__func__, __LINE__, (chan))
128 #define dbg_showchan(chan) dmadbg_showchan(__func__, __LINE__, (chan))
130 #define dbg_showregs(chan) do { } while(0)
131 #define dbg_showchan(chan) do { } while(0)
132 #endif /* CONFIG_S3C2410_DMA_DEBUG */
134 /* s3c2410_dma_stats_timeout
136 * Update DMA stats from timeout info
140 s3c2410_dma_stats_timeout(struct s3c2410_dma_stats
*stats
, int val
)
145 if (val
> stats
->timeout_longest
)
146 stats
->timeout_longest
= val
;
147 if (val
< stats
->timeout_shortest
)
148 stats
->timeout_shortest
= val
;
150 stats
->timeout_avg
+= val
;
153 /* s3c2410_dma_waitforload
155 * wait for the DMA engine to load a buffer, and update the state accordingly
159 s3c2410_dma_waitforload(struct s3c2410_dma_chan
*chan
, int line
)
161 int timeout
= chan
->load_timeout
;
164 if (chan
->load_state
!= S3C2410_DMALOAD_1LOADED
) {
165 printk(KERN_ERR
"dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan
->number
, chan
->load_state
, line
);
169 if (chan
->stats
!= NULL
)
170 chan
->stats
->loads
++;
172 while (--timeout
> 0) {
173 if ((dma_rdreg(chan
, S3C2410_DMA_DSTAT
) << (32-20)) != 0) {
174 took
= chan
->load_timeout
- timeout
;
176 s3c2410_dma_stats_timeout(chan
->stats
, took
);
178 switch (chan
->load_state
) {
179 case S3C2410_DMALOAD_1LOADED
:
180 chan
->load_state
= S3C2410_DMALOAD_1RUNNING
;
184 printk(KERN_ERR
"dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan
->number
, chan
->load_state
);
191 if (chan
->stats
!= NULL
) {
192 chan
->stats
->timeout_failed
++;
198 /* s3c2410_dma_loadbuffer
200 * load a buffer, and update the channel state
204 s3c2410_dma_loadbuffer(struct s3c2410_dma_chan
*chan
,
205 struct s3c2410_dma_buf
*buf
)
207 unsigned long reload
;
210 dmawarn("buffer is NULL\n");
214 pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
215 buf
, (unsigned long)buf
->data
, buf
->size
);
217 /* check the state of the channel before we do anything */
219 if (chan
->load_state
== S3C2410_DMALOAD_1LOADED
) {
220 dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
223 if (chan
->load_state
== S3C2410_DMALOAD_1LOADED_1RUNNING
) {
224 dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
227 /* it would seem sensible if we are the last buffer to not bother
228 * with the auto-reload bit, so that the DMA engine will not try
229 * and load another transfer after this one has finished...
231 if (chan
->load_state
== S3C2410_DMALOAD_NONE
) {
232 pr_debug("load_state is none, checking for noreload (next=%p)\n",
234 reload
= (buf
->next
== NULL
) ? S3C2410_DCON_NORELOAD
: 0;
236 //pr_debug("load_state is %d => autoreload\n", chan->load_state);
237 reload
= S3C2410_DCON_AUTORELOAD
;
240 if ((buf
->data
& 0xf0000000) != 0x30000000) {
241 dmawarn("dmaload: buffer is %p\n", (void *)buf
->data
);
244 writel(buf
->data
, chan
->addr_reg
);
246 dma_wrreg(chan
, S3C2410_DMA_DCON
,
247 chan
->dcon
| reload
| (buf
->size
/chan
->xfer_unit
));
249 chan
->next
= buf
->next
;
251 /* update the state of the channel */
253 switch (chan
->load_state
) {
254 case S3C2410_DMALOAD_NONE
:
255 chan
->load_state
= S3C2410_DMALOAD_1LOADED
;
258 case S3C2410_DMALOAD_1RUNNING
:
259 chan
->load_state
= S3C2410_DMALOAD_1LOADED_1RUNNING
;
263 dmawarn("dmaload: unknown state %d in loadbuffer\n",
271 /* s3c2410_dma_call_op
273 * small routine to call the op routine with the given op if it has been
278 s3c2410_dma_call_op(struct s3c2410_dma_chan
*chan
, enum s3c2410_chan_op op
)
280 if (chan
->op_fn
!= NULL
) {
281 (chan
->op_fn
)(chan
, op
);
285 /* s3c2410_dma_buffdone
287 * small wrapper to check if callback routine needs to be called, and
292 s3c2410_dma_buffdone(struct s3c2410_dma_chan
*chan
, struct s3c2410_dma_buf
*buf
,
293 enum s3c2410_dma_buffresult result
)
296 pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
297 chan
->callback_fn
, buf
, buf
->id
, buf
->size
, result
);
300 if (chan
->callback_fn
!= NULL
) {
301 (chan
->callback_fn
)(chan
, buf
->id
, buf
->size
, result
);
307 * start a dma channel going
310 static int s3c2410_dma_start(struct s3c2410_dma_chan
*chan
)
315 pr_debug("s3c2410_start_dma: channel=%d\n", chan
->number
);
317 local_irq_save(flags
);
319 if (chan
->state
== S3C2410_DMA_RUNNING
) {
320 pr_debug("s3c2410_start_dma: already running (%d)\n", chan
->state
);
321 local_irq_restore(flags
);
325 chan
->state
= S3C2410_DMA_RUNNING
;
327 /* check whether there is anything to load, and if not, see
328 * if we can find anything to load
331 if (chan
->load_state
== S3C2410_DMALOAD_NONE
) {
332 if (chan
->next
== NULL
) {
333 printk(KERN_ERR
"dma%d: channel has nothing loaded\n",
335 chan
->state
= S3C2410_DMA_IDLE
;
336 local_irq_restore(flags
);
340 s3c2410_dma_loadbuffer(chan
, chan
->next
);
345 /* enable the channel */
347 if (!chan
->irq_enabled
) {
348 enable_irq(chan
->irq
);
349 chan
->irq_enabled
= 1;
352 /* start the channel going */
354 tmp
= dma_rdreg(chan
, S3C2410_DMA_DMASKTRIG
);
355 tmp
&= ~S3C2410_DMASKTRIG_STOP
;
356 tmp
|= S3C2410_DMASKTRIG_ON
;
357 dma_wrreg(chan
, S3C2410_DMA_DMASKTRIG
, tmp
);
359 pr_debug("dma%d: %08lx to DMASKTRIG\n", chan
->number
, tmp
);
362 /* the dma buffer loads should take care of clearing the AUTO
363 * reloading feature */
364 tmp
= dma_rdreg(chan
, S3C2410_DMA_DCON
);
365 tmp
&= ~S3C2410_DCON_NORELOAD
;
366 dma_wrreg(chan
, S3C2410_DMA_DCON
, tmp
);
369 s3c2410_dma_call_op(chan
, S3C2410_DMAOP_START
);
373 /* if we've only loaded one buffer onto the channel, then chec
374 * to see if we have another, and if so, try and load it so when
375 * the first buffer is finished, the new one will be loaded onto
378 if (chan
->next
!= NULL
) {
379 if (chan
->load_state
== S3C2410_DMALOAD_1LOADED
) {
381 if (s3c2410_dma_waitforload(chan
, __LINE__
) == 0) {
382 pr_debug("%s: buff not yet loaded, no more todo\n",
385 chan
->load_state
= S3C2410_DMALOAD_1RUNNING
;
386 s3c2410_dma_loadbuffer(chan
, chan
->next
);
389 } else if (chan
->load_state
== S3C2410_DMALOAD_1RUNNING
) {
390 s3c2410_dma_loadbuffer(chan
, chan
->next
);
395 local_irq_restore(flags
);
400 /* s3c2410_dma_canload
402 * work out if we can queue another buffer into the DMA engine
406 s3c2410_dma_canload(struct s3c2410_dma_chan
*chan
)
408 if (chan
->load_state
== S3C2410_DMALOAD_NONE
||
409 chan
->load_state
== S3C2410_DMALOAD_1RUNNING
)
415 /* s3c2410_dma_enqueue
417 * queue an given buffer for dma transfer.
419 * id the device driver's id information for this buffer
420 * data the physical address of the buffer data
421 * size the size of the buffer in bytes
423 * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
424 * is checked, and if set, the channel is started. If this flag isn't set,
425 * then an error will be returned.
427 * It is possible to queue more than one DMA buffer onto a channel at
428 * once, and the code will deal with the re-loading of the next buffer
432 int s3c2410_dma_enqueue(enum dma_ch channel
, void *id
,
433 dma_addr_t data
, int size
)
435 struct s3c2410_dma_chan
*chan
= s3c_dma_lookup_channel(channel
);
436 struct s3c2410_dma_buf
*buf
;
442 pr_debug("%s: id=%p, data=%08x, size=%d\n",
443 __func__
, id
, (unsigned int)data
, size
);
445 buf
= kmem_cache_alloc(dma_kmem
, GFP_ATOMIC
);
447 pr_debug("%s: out of memory (%ld alloc)\n",
448 __func__
, (long)sizeof(*buf
));
452 //pr_debug("%s: new buffer %p\n", __func__, buf);
453 //dbg_showchan(chan);
456 buf
->data
= buf
->ptr
= data
;
459 buf
->magic
= BUF_MAGIC
;
461 local_irq_save(flags
);
463 if (chan
->curr
== NULL
) {
464 /* we've got nothing loaded... */
465 pr_debug("%s: buffer %p queued onto empty channel\n",
472 pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
473 chan
->number
, __func__
, buf
);
475 if (chan
->end
== NULL
) {
476 pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
477 chan
->number
, __func__
, chan
);
479 chan
->end
->next
= buf
;
484 /* if necessary, update the next buffer field */
485 if (chan
->next
== NULL
)
488 /* check to see if we can load a buffer */
489 if (chan
->state
== S3C2410_DMA_RUNNING
) {
490 if (chan
->load_state
== S3C2410_DMALOAD_1LOADED
&& 1) {
491 if (s3c2410_dma_waitforload(chan
, __LINE__
) == 0) {
492 printk(KERN_ERR
"dma%d: loadbuffer:"
493 "timeout loading buffer\n",
496 local_irq_restore(flags
);
501 while (s3c2410_dma_canload(chan
) && chan
->next
!= NULL
) {
502 s3c2410_dma_loadbuffer(chan
, chan
->next
);
504 } else if (chan
->state
== S3C2410_DMA_IDLE
) {
505 if (chan
->flags
& S3C2410_DMAF_AUTOSTART
) {
506 s3c2410_dma_ctrl(chan
->number
| DMACH_LOW_LEVEL
,
507 S3C2410_DMAOP_START
);
511 local_irq_restore(flags
);
515 EXPORT_SYMBOL(s3c2410_dma_enqueue
);
518 s3c2410_dma_freebuf(struct s3c2410_dma_buf
*buf
)
520 int magicok
= (buf
->magic
== BUF_MAGIC
);
525 kmem_cache_free(dma_kmem
, buf
);
527 printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf
);
531 /* s3c2410_dma_lastxfer
533 * called when the system is out of buffers, to ensure that the channel
534 * is prepared for shutdown.
538 s3c2410_dma_lastxfer(struct s3c2410_dma_chan
*chan
)
541 pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
542 chan
->number
, chan
->load_state
);
545 switch (chan
->load_state
) {
546 case S3C2410_DMALOAD_NONE
:
549 case S3C2410_DMALOAD_1LOADED
:
550 if (s3c2410_dma_waitforload(chan
, __LINE__
) == 0) {
552 printk(KERN_ERR
"dma%d: timeout waiting for load (%s)\n",
553 chan
->number
, __func__
);
558 case S3C2410_DMALOAD_1LOADED_1RUNNING
:
559 /* I believe in this case we do not have anything to do
560 * until the next buffer comes along, and we turn off the
565 pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n",
566 chan
->number
, chan
->load_state
);
571 /* hopefully this'll shut the damned thing up after the transfer... */
572 dma_wrreg(chan
, S3C2410_DMA_DCON
, chan
->dcon
| S3C2410_DCON_NORELOAD
);
576 #define dmadbg2(x...)
579 s3c2410_dma_irq(int irq
, void *devpw
)
581 struct s3c2410_dma_chan
*chan
= (struct s3c2410_dma_chan
*)devpw
;
582 struct s3c2410_dma_buf
*buf
;
588 /* modify the channel state */
590 switch (chan
->load_state
) {
591 case S3C2410_DMALOAD_1RUNNING
:
592 /* TODO - if we are running only one buffer, we probably
593 * want to reload here, and then worry about the buffer
596 chan
->load_state
= S3C2410_DMALOAD_NONE
;
599 case S3C2410_DMALOAD_1LOADED
:
600 /* iirc, we should go back to NONE loaded here, we
601 * had a buffer, and it was never verified as being
605 chan
->load_state
= S3C2410_DMALOAD_NONE
;
608 case S3C2410_DMALOAD_1LOADED_1RUNNING
:
609 /* we'll worry about checking to see if another buffer is
610 * ready after we've called back the owner. This should
611 * ensure we do not wait around too long for the DMA
612 * engine to start the next transfer
615 chan
->load_state
= S3C2410_DMALOAD_1LOADED
;
618 case S3C2410_DMALOAD_NONE
:
619 printk(KERN_ERR
"dma%d: IRQ with no loaded buffer?\n",
624 printk(KERN_ERR
"dma%d: IRQ in invalid load_state %d\n",
625 chan
->number
, chan
->load_state
);
630 /* update the chain to make sure that if we load any more
631 * buffers when we call the callback function, things should
634 chan
->curr
= buf
->next
;
637 if (buf
->magic
!= BUF_MAGIC
) {
638 printk(KERN_ERR
"dma%d: %s: buf %p incorrect magic\n",
639 chan
->number
, __func__
, buf
);
643 s3c2410_dma_buffdone(chan
, buf
, S3C2410_RES_OK
);
646 s3c2410_dma_freebuf(buf
);
650 /* only reload if the channel is still running... our buffer done
651 * routine may have altered the state by requesting the dma channel
652 * to stop or shutdown... */
654 /* todo: check that when the channel is shut-down from inside this
655 * function, we cope with unsetting reload, etc */
657 if (chan
->next
!= NULL
&& chan
->state
!= S3C2410_DMA_IDLE
) {
660 switch (chan
->load_state
) {
661 case S3C2410_DMALOAD_1RUNNING
:
662 /* don't need to do anything for this state */
665 case S3C2410_DMALOAD_NONE
:
666 /* can load buffer immediately */
669 case S3C2410_DMALOAD_1LOADED
:
670 if (s3c2410_dma_waitforload(chan
, __LINE__
) == 0) {
672 printk(KERN_ERR
"dma%d: timeout waiting for load (%s)\n",
673 chan
->number
, __func__
);
679 case S3C2410_DMALOAD_1LOADED_1RUNNING
:
683 printk(KERN_ERR
"dma%d: unknown load_state in irq, %d\n",
684 chan
->number
, chan
->load_state
);
688 local_irq_save(flags
);
689 s3c2410_dma_loadbuffer(chan
, chan
->next
);
690 local_irq_restore(flags
);
692 s3c2410_dma_lastxfer(chan
);
694 /* see if we can stop this channel.. */
695 if (chan
->load_state
== S3C2410_DMALOAD_NONE
) {
696 pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
697 chan
->number
, jiffies
);
698 s3c2410_dma_ctrl(chan
->number
| DMACH_LOW_LEVEL
,
707 static struct s3c2410_dma_chan
*s3c2410_dma_map_channel(int channel
);
709 /* s3c2410_request_dma
711 * get control of an dma channel
714 int s3c2410_dma_request(enum dma_ch channel
,
715 struct s3c2410_dma_client
*client
,
718 struct s3c2410_dma_chan
*chan
;
722 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
723 channel
, client
->name
, dev
);
725 local_irq_save(flags
);
727 chan
= s3c2410_dma_map_channel(channel
);
729 local_irq_restore(flags
);
735 chan
->client
= client
;
738 if (!chan
->irq_claimed
) {
739 pr_debug("dma%d: %s : requesting irq %d\n",
740 channel
, __func__
, chan
->irq
);
742 chan
->irq_claimed
= 1;
743 local_irq_restore(flags
);
745 err
= request_irq(chan
->irq
, s3c2410_dma_irq
, 0,
746 client
->name
, (void *)chan
);
748 local_irq_save(flags
);
752 chan
->irq_claimed
= 0;
753 local_irq_restore(flags
);
755 printk(KERN_ERR
"%s: cannot get IRQ %d for DMA %d\n",
756 client
->name
, chan
->irq
, chan
->number
);
760 chan
->irq_enabled
= 1;
763 local_irq_restore(flags
);
767 pr_debug("%s: channel initialised, %p\n", __func__
, chan
);
769 return chan
->number
| DMACH_LOW_LEVEL
;
772 EXPORT_SYMBOL(s3c2410_dma_request
);
776 * release the given channel back to the system, will stop and flush
777 * any outstanding transfers, and ensure the channel is ready for the
780 * Note, although a warning is currently printed if the freeing client
781 * info is not the same as the registrant's client info, the free is still
782 * allowed to go through.
785 int s3c2410_dma_free(enum dma_ch channel
, struct s3c2410_dma_client
*client
)
787 struct s3c2410_dma_chan
*chan
= s3c_dma_lookup_channel(channel
);
793 local_irq_save(flags
);
795 if (chan
->client
!= client
) {
796 printk(KERN_WARNING
"dma%d: possible free from different client (channel %p, passed %p)\n",
797 channel
, chan
->client
, client
);
800 /* sort out stopping and freeing the channel */
802 if (chan
->state
!= S3C2410_DMA_IDLE
) {
803 pr_debug("%s: need to stop dma channel %p\n",
806 /* possibly flush the channel */
807 s3c2410_dma_ctrl(channel
, S3C2410_DMAOP_STOP
);
813 if (chan
->irq_claimed
)
814 free_irq(chan
->irq
, (void *)chan
);
816 chan
->irq_claimed
= 0;
818 if (!(channel
& DMACH_LOW_LEVEL
))
819 s3c_dma_chan_map
[channel
] = NULL
;
821 local_irq_restore(flags
);
826 EXPORT_SYMBOL(s3c2410_dma_free
);
828 static int s3c2410_dma_dostop(struct s3c2410_dma_chan
*chan
)
833 pr_debug("%s:\n", __func__
);
837 local_irq_save(flags
);
839 s3c2410_dma_call_op(chan
, S3C2410_DMAOP_STOP
);
841 tmp
= dma_rdreg(chan
, S3C2410_DMA_DMASKTRIG
);
842 tmp
|= S3C2410_DMASKTRIG_STOP
;
843 //tmp &= ~S3C2410_DMASKTRIG_ON;
844 dma_wrreg(chan
, S3C2410_DMA_DMASKTRIG
, tmp
);
847 /* should also clear interrupts, according to WinCE BSP */
848 tmp
= dma_rdreg(chan
, S3C2410_DMA_DCON
);
849 tmp
|= S3C2410_DCON_NORELOAD
;
850 dma_wrreg(chan
, S3C2410_DMA_DCON
, tmp
);
853 /* should stop do this, or should we wait for flush? */
854 chan
->state
= S3C2410_DMA_IDLE
;
855 chan
->load_state
= S3C2410_DMALOAD_NONE
;
857 local_irq_restore(flags
);
862 static void s3c2410_dma_waitforstop(struct s3c2410_dma_chan
*chan
)
865 unsigned int timeout
= 0x10000;
867 while (timeout
-- > 0) {
868 tmp
= dma_rdreg(chan
, S3C2410_DMA_DMASKTRIG
);
870 if (!(tmp
& S3C2410_DMASKTRIG_ON
))
874 pr_debug("dma%d: failed to stop?\n", chan
->number
);
880 * stop the channel, and remove all current and pending transfers
883 static int s3c2410_dma_flush(struct s3c2410_dma_chan
*chan
)
885 struct s3c2410_dma_buf
*buf
, *next
;
888 pr_debug("%s: chan %p (%d)\n", __func__
, chan
, chan
->number
);
892 local_irq_save(flags
);
894 if (chan
->state
!= S3C2410_DMA_IDLE
) {
895 pr_debug("%s: stopping channel...\n", __func__
);
896 s3c2410_dma_ctrl(chan
->number
, S3C2410_DMAOP_STOP
);
903 chan
->curr
= chan
->next
= chan
->end
= NULL
;
906 for ( ; buf
!= NULL
; buf
= next
) {
909 pr_debug("%s: free buffer %p, next %p\n",
910 __func__
, buf
, buf
->next
);
912 s3c2410_dma_buffdone(chan
, buf
, S3C2410_RES_ABORT
);
913 s3c2410_dma_freebuf(buf
);
919 s3c2410_dma_waitforstop(chan
);
922 /* should also clear interrupts, according to WinCE BSP */
926 tmp
= dma_rdreg(chan
, S3C2410_DMA_DCON
);
927 tmp
|= S3C2410_DCON_NORELOAD
;
928 dma_wrreg(chan
, S3C2410_DMA_DCON
, tmp
);
934 local_irq_restore(flags
);
939 static int s3c2410_dma_started(struct s3c2410_dma_chan
*chan
)
943 local_irq_save(flags
);
947 /* if we've only loaded one buffer onto the channel, then chec
948 * to see if we have another, and if so, try and load it so when
949 * the first buffer is finished, the new one will be loaded onto
952 if (chan
->next
!= NULL
) {
953 if (chan
->load_state
== S3C2410_DMALOAD_1LOADED
) {
955 if (s3c2410_dma_waitforload(chan
, __LINE__
) == 0) {
956 pr_debug("%s: buff not yet loaded, no more todo\n",
959 chan
->load_state
= S3C2410_DMALOAD_1RUNNING
;
960 s3c2410_dma_loadbuffer(chan
, chan
->next
);
963 } else if (chan
->load_state
== S3C2410_DMALOAD_1RUNNING
) {
964 s3c2410_dma_loadbuffer(chan
, chan
->next
);
969 local_irq_restore(flags
);
976 s3c2410_dma_ctrl(enum dma_ch channel
, enum s3c2410_chan_op op
)
978 struct s3c2410_dma_chan
*chan
= s3c_dma_lookup_channel(channel
);
984 case S3C2410_DMAOP_START
:
985 return s3c2410_dma_start(chan
);
987 case S3C2410_DMAOP_STOP
:
988 return s3c2410_dma_dostop(chan
);
990 case S3C2410_DMAOP_PAUSE
:
991 case S3C2410_DMAOP_RESUME
:
994 case S3C2410_DMAOP_FLUSH
:
995 return s3c2410_dma_flush(chan
);
997 case S3C2410_DMAOP_STARTED
:
998 return s3c2410_dma_started(chan
);
1000 case S3C2410_DMAOP_TIMEOUT
:
1005 return -ENOENT
; /* unknown, don't bother */
1008 EXPORT_SYMBOL(s3c2410_dma_ctrl
);
1010 /* DMA configuration for each channel
1012 * DISRCC -> source of the DMA (AHB,APB)
1013 * DISRC -> source address of the DMA
1014 * DIDSTC -> destination of the DMA (AHB,APD)
1015 * DIDST -> destination address of the DMA
1018 /* s3c2410_dma_config
1020 * xfersize: size of unit in bytes (1,2,4)
1023 int s3c2410_dma_config(enum dma_ch channel
,
1026 struct s3c2410_dma_chan
*chan
= s3c_dma_lookup_channel(channel
);
1029 pr_debug("%s: chan=%d, xfer_unit=%d\n", __func__
, channel
, xferunit
);
1034 dcon
= chan
->dcon
& dma_sel
.dcon_mask
;
1035 pr_debug("%s: dcon is %08x\n", __func__
, dcon
);
1037 switch (chan
->req_ch
) {
1044 dcon
|= S3C2410_DCON_HANDSHAKE
;
1045 dcon
|= S3C2410_DCON_SYNC_PCLK
;
1049 /* note, ensure if need HANDSHAKE or not */
1050 dcon
|= S3C2410_DCON_SYNC_PCLK
;
1055 dcon
|= S3C2410_DCON_HANDSHAKE
;
1056 dcon
|= S3C2410_DCON_SYNC_HCLK
;
1062 dcon
|= S3C2410_DCON_BYTE
;
1066 dcon
|= S3C2410_DCON_HALFWORD
;
1070 dcon
|= S3C2410_DCON_WORD
;
1074 pr_debug("%s: bad transfer size %d\n", __func__
, xferunit
);
1078 dcon
|= S3C2410_DCON_HWTRIG
;
1079 dcon
|= S3C2410_DCON_INTREQ
;
1081 pr_debug("%s: dcon now %08x\n", __func__
, dcon
);
1084 chan
->xfer_unit
= xferunit
;
1089 EXPORT_SYMBOL(s3c2410_dma_config
);
1092 /* s3c2410_dma_devconfig
1094 * configure the dma source/destination hardware type and address
1096 * source: DMA_FROM_DEVICE: source is hardware
1097 * DMA_TO_DEVICE: source is memory
1099 * devaddr: physical address of the source
1102 int s3c2410_dma_devconfig(enum dma_ch channel
,
1103 enum dma_data_direction source
,
1104 unsigned long devaddr
)
1106 struct s3c2410_dma_chan
*chan
= s3c_dma_lookup_channel(channel
);
1112 pr_debug("%s: source=%d, devaddr=%08lx\n",
1113 __func__
, (int)source
, devaddr
);
1115 chan
->source
= source
;
1116 chan
->dev_addr
= devaddr
;
1118 switch (chan
->req_ch
) {
1121 hwcfg
= 0; /* AHB */
1125 hwcfg
= S3C2410_DISRCC_APB
;
1128 /* always assume our peripheral desintation is a fixed
1129 * address in memory. */
1130 hwcfg
|= S3C2410_DISRCC_INC
;
1133 case DMA_FROM_DEVICE
:
1134 /* source is hardware */
1135 pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
1136 __func__
, devaddr
, hwcfg
);
1137 dma_wrreg(chan
, S3C2410_DMA_DISRCC
, hwcfg
& 3);
1138 dma_wrreg(chan
, S3C2410_DMA_DISRC
, devaddr
);
1139 dma_wrreg(chan
, S3C2410_DMA_DIDSTC
, (0<<1) | (0<<0));
1141 chan
->addr_reg
= dma_regaddr(chan
, S3C2410_DMA_DIDST
);
1145 /* source is memory */
1146 pr_debug("%s: mem source, devaddr=%08lx, hwcfg=%d\n",
1147 __func__
, devaddr
, hwcfg
);
1148 dma_wrreg(chan
, S3C2410_DMA_DISRCC
, (0<<1) | (0<<0));
1149 dma_wrreg(chan
, S3C2410_DMA_DIDST
, devaddr
);
1150 dma_wrreg(chan
, S3C2410_DMA_DIDSTC
, hwcfg
& 3);
1152 chan
->addr_reg
= dma_regaddr(chan
, S3C2410_DMA_DISRC
);
1156 printk(KERN_ERR
"dma%d: invalid source type (%d)\n",
1165 EXPORT_SYMBOL(s3c2410_dma_devconfig
);
1167 /* s3c2410_dma_getposition
1169 * returns the current transfer points for the dma source and destination
1172 int s3c2410_dma_getposition(enum dma_ch channel
, dma_addr_t
*src
, dma_addr_t
*dst
)
1174 struct s3c2410_dma_chan
*chan
= s3c_dma_lookup_channel(channel
);
1180 *src
= dma_rdreg(chan
, S3C2410_DMA_DCSRC
);
1183 *dst
= dma_rdreg(chan
, S3C2410_DMA_DCDST
);
1188 EXPORT_SYMBOL(s3c2410_dma_getposition
);
1190 /* system core operations */
1194 static void s3c2410_dma_suspend_chan(struct s3c2410_dma_chan
*cp
)
1196 printk(KERN_DEBUG
"suspending dma channel %d\n", cp
->number
);
1198 if (dma_rdreg(cp
, S3C2410_DMA_DMASKTRIG
) & S3C2410_DMASKTRIG_ON
) {
1199 /* the dma channel is still working, which is probably
1200 * a bad thing to do over suspend/resume. We stop the
1201 * channel and assume that the client is either going to
1202 * retry after resume, or that it is broken.
1205 printk(KERN_INFO
"dma: stopping channel %d due to suspend\n",
1208 s3c2410_dma_dostop(cp
);
1212 static int s3c2410_dma_suspend(void)
1214 struct s3c2410_dma_chan
*cp
= s3c2410_chans
;
1217 for (channel
= 0; channel
< dma_channels
; cp
++, channel
++)
1218 s3c2410_dma_suspend_chan(cp
);
1223 static void s3c2410_dma_resume_chan(struct s3c2410_dma_chan
*cp
)
1225 unsigned int no
= cp
->number
| DMACH_LOW_LEVEL
;
1227 /* restore channel's hardware configuration */
1232 printk(KERN_INFO
"dma%d: restoring configuration\n", cp
->number
);
1234 s3c2410_dma_config(no
, cp
->xfer_unit
);
1235 s3c2410_dma_devconfig(no
, cp
->source
, cp
->dev_addr
);
1237 /* re-select the dma source for this channel */
1239 if (cp
->map
!= NULL
)
1240 dma_sel
.select(cp
, cp
->map
);
1243 static void s3c2410_dma_resume(void)
1245 struct s3c2410_dma_chan
*cp
= s3c2410_chans
+ dma_channels
- 1;
1248 for (channel
= dma_channels
- 1; channel
>= 0; cp
--, channel
--)
1249 s3c2410_dma_resume_chan(cp
);
1253 #define s3c2410_dma_suspend NULL
1254 #define s3c2410_dma_resume NULL
1255 #endif /* CONFIG_PM */
1257 struct syscore_ops dma_syscore_ops
= {
1258 .suspend
= s3c2410_dma_suspend
,
1259 .resume
= s3c2410_dma_resume
,
1262 /* kmem cache implementation */
1264 static void s3c2410_dma_cache_ctor(void *p
)
1266 memset(p
, 0, sizeof(struct s3c2410_dma_buf
));
1269 /* initialisation code */
1271 static int __init
s3c24xx_dma_syscore_init(void)
1273 register_syscore_ops(&dma_syscore_ops
);
1278 late_initcall(s3c24xx_dma_syscore_init
);
1280 int __init
s3c24xx_dma_init(unsigned int channels
, unsigned int irq
,
1281 unsigned int stride
)
1283 struct s3c2410_dma_chan
*cp
;
1287 printk("S3C24XX DMA Driver, Copyright 2003-2006 Simtec Electronics\n");
1289 dma_channels
= channels
;
1291 dma_base
= ioremap(S3C24XX_PA_DMA
, stride
* channels
);
1292 if (dma_base
== NULL
) {
1293 printk(KERN_ERR
"dma failed to remap register block\n");
1297 dma_kmem
= kmem_cache_create("dma_desc",
1298 sizeof(struct s3c2410_dma_buf
), 0,
1300 s3c2410_dma_cache_ctor
);
1302 if (dma_kmem
== NULL
) {
1303 printk(KERN_ERR
"dma failed to make kmem cache\n");
1308 for (channel
= 0; channel
< channels
; channel
++) {
1309 cp
= &s3c2410_chans
[channel
];
1311 memset(cp
, 0, sizeof(struct s3c2410_dma_chan
));
1313 /* dma channel irqs are in order.. */
1314 cp
->number
= channel
;
1315 cp
->irq
= channel
+ irq
;
1316 cp
->regs
= dma_base
+ (channel
* stride
);
1318 /* point current stats somewhere */
1319 cp
->stats
= &cp
->stats_store
;
1320 cp
->stats_store
.timeout_shortest
= LONG_MAX
;
1322 /* basic channel configuration */
1324 cp
->load_timeout
= 1<<18;
1326 printk("DMA channel %d at %p, irq %d\n",
1327 cp
->number
, cp
->regs
, cp
->irq
);
1333 kmem_cache_destroy(dma_kmem
);
1339 int __init
s3c2410_dma_init(void)
1341 return s3c24xx_dma_init(4, IRQ_DMA0
, 0x40);
1344 static inline int is_channel_valid(unsigned int channel
)
1346 return (channel
& DMA_CH_VALID
);
1349 static struct s3c24xx_dma_order
*dma_order
;
1352 /* s3c2410_dma_map_channel()
1354 * turn the virtual channel number into a real, and un-used hardware
1357 * first, try the dma ordering given to us by either the relevant
1358 * dma code, or the board. Then just find the first usable free
1362 static struct s3c2410_dma_chan
*s3c2410_dma_map_channel(int channel
)
1364 struct s3c24xx_dma_order_ch
*ord
= NULL
;
1365 struct s3c24xx_dma_map
*ch_map
;
1366 struct s3c2410_dma_chan
*dmach
;
1369 if (dma_sel
.map
== NULL
|| channel
> dma_sel
.map_size
)
1372 ch_map
= dma_sel
.map
+ channel
;
1374 /* first, try the board mapping */
1377 ord
= &dma_order
->channels
[channel
];
1379 for (ch
= 0; ch
< dma_channels
; ch
++) {
1381 if (!is_channel_valid(ord
->list
[ch
]))
1384 tmp
= ord
->list
[ch
] & ~DMA_CH_VALID
;
1385 if (s3c2410_chans
[tmp
].in_use
== 0) {
1391 if (ord
->flags
& DMA_CH_NEVER
)
1395 /* second, search the channel map for first free */
1397 for (ch
= 0; ch
< dma_channels
; ch
++) {
1398 if (!is_channel_valid(ch_map
->channels
[ch
]))
1401 if (s3c2410_chans
[ch
].in_use
== 0) {
1402 printk("mapped channel %d to %d\n", channel
, ch
);
1407 if (ch
>= dma_channels
)
1410 /* update our channel mapping */
1413 dmach
= &s3c2410_chans
[ch
];
1414 dmach
->map
= ch_map
;
1415 dmach
->req_ch
= channel
;
1416 s3c_dma_chan_map
[channel
] = dmach
;
1418 /* select the channel */
1420 (dma_sel
.select
)(dmach
, ch_map
);
1425 static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map
*map
, int ch
)
1430 int __init
s3c24xx_dma_init_map(struct s3c24xx_dma_selection
*sel
)
1432 struct s3c24xx_dma_map
*nmap
;
1433 size_t map_sz
= sizeof(*nmap
) * sel
->map_size
;
1436 nmap
= kmemdup(sel
->map
, map_sz
, GFP_KERNEL
);
1440 memcpy(&dma_sel
, sel
, sizeof(*sel
));
1444 for (ptr
= 0; ptr
< sel
->map_size
; ptr
++)
1445 s3c24xx_dma_check_entry(nmap
+ptr
, ptr
);
1450 int __init
s3c24xx_dma_order_set(struct s3c24xx_dma_order
*ord
)
1452 struct s3c24xx_dma_order
*nord
= dma_order
;
1455 nord
= kmalloc(sizeof(struct s3c24xx_dma_order
), GFP_KERNEL
);
1458 printk(KERN_ERR
"no memory to store dma channel order\n");
1463 memcpy(nord
, ord
, sizeof(struct s3c24xx_dma_order
));