arch/arm/mach-s3c24xx/mach-jive.c

   1 /* linux/arch/arm/mach-s3c2410/mach-jive.c
   2  *
   3  * Copyright 2007 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * http://armlinux.simtec.co.uk/
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/list.h>
  17 #include <linux/timer.h>
  18 #include <linux/init.h>
  19 #include <linux/gpio.h>
  20 #include <linux/syscore_ops.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/serial_s3c.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/i2c.h>
  25
  26 #include <video/ili9320.h>
  27
  28 #include <linux/spi/spi.h>
  29 #include <linux/spi/spi_gpio.h>
  30
  31 #include <asm/mach/arch.h>
  32 #include <asm/mach/map.h>
  33 #include <asm/mach/irq.h>
  34
  35 #include <linux/platform_data/mtd-nand-s3c2410.h>
  36 #include <linux/platform_data/i2c-s3c2410.h>
  37
  38 #include <mach/regs-gpio.h>
  39 #include <mach/regs-lcd.h>
  40 #include <mach/fb.h>
  41 #include <mach/gpio-samsung.h>
  42
  43 #include <asm/mach-types.h>
  44
  45 #include <linux/mtd/mtd.h>
  46 #include <linux/mtd/nand.h>
  47 #include <linux/mtd/nand_ecc.h>
  48 #include <linux/mtd/partitions.h>
  49
  50 #include <plat/gpio-cfg.h>
  51 #include <plat/clock.h>
  52 #include <plat/devs.h>
  53 #include <plat/cpu.h>
  54 #include <plat/pm.h>
  55 #include <linux/platform_data/usb-s3c2410_udc.h>
  56 #include <plat/samsung-time.h>
  57
  58 #include "common.h"
  59 #include "s3c2412-power.h"
  60
  61 static struct map_desc jive_iodesc[] __initdata = {
  62 };
  63
  64 #define UCON S3C2410_UCON_DEFAULT
  65 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
  66 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  67
  68 static struct s3c2410_uartcfg jive_uartcfgs[] = {
  69         [0] = {
  70                 .hwport      = 0,
  71                 .flags       = 0,
  72                 .ucon        = UCON,
  73                 .ulcon       = ULCON,
  74                 .ufcon       = UFCON,
  75         },
  76         [1] = {
  77                 .hwport      = 1,
  78                 .flags       = 0,
  79                 .ucon        = UCON,
  80                 .ulcon       = ULCON,
  81                 .ufcon       = UFCON,
  82         },
  83         [2] = {
  84                 .hwport      = 2,
  85                 .flags       = 0,
  86                 .ucon        = UCON,
  87                 .ulcon       = ULCON,
  88                 .ufcon       = UFCON,
  89         }
  90 };
  91
  92 /* Jive flash assignment
  93  *
  94  * 0x00000000-0x00028000 : uboot
  95  * 0x00028000-0x0002c000 : uboot env
  96  * 0x0002c000-0x00030000 : spare
  97  * 0x00030000-0x00200000 : zimage A
  98  * 0x00200000-0x01600000 : cramfs A
  99  * 0x01600000-0x017d0000 : zimage B
 100  * 0x017d0000-0x02bd0000 : cramfs B
 101  * 0x02bd0000-0x03fd0000 : yaffs
 102  */
 103 static struct mtd_partition __initdata jive_imageA_nand_part[] = {
 104
 105 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
 106         /* Don't allow access to the bootloader from linux */
 107         {
 108                 .name           = "uboot",
 109                 .offset         = 0,
 110                 .size           = (160 * SZ_1K),
 111                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 112         },
 113
 114         /* spare */
 115         {
 116                 .name           = "spare",
 117                 .offset         = (176 * SZ_1K),
 118                 .size           = (16 * SZ_1K),
 119         },
 120 #endif
 121
 122         /* booted images */
 123         {
 124                 .name           = "kernel (ro)",
 125                 .offset         = (192 * SZ_1K),
 126                 .size           = (SZ_2M) - (192 * SZ_1K),
 127                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 128         }, {
 129                 .name           = "root (ro)",
 130                 .offset         = (SZ_2M),
 131                 .size           = (20 * SZ_1M),
 132                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 133         },
 134
 135         /* yaffs */
 136         {
 137                 .name           = "yaffs",
 138                 .offset         = (44 * SZ_1M),
 139                 .size           = (20 * SZ_1M),
 140         },
 141
 142         /* bootloader environment */
 143         {
 144                 .name           = "env",
 145                 .offset         = (160 * SZ_1K),
 146                 .size           = (16 * SZ_1K),
 147         },
 148
 149         /* upgrade images */
 150         {
 151                 .name           = "zimage",
 152                 .offset         = (22 * SZ_1M),
 153                 .size           = (2 * SZ_1M) - (192 * SZ_1K),
 154         }, {
 155                 .name           = "cramfs",
 156                 .offset         = (24 * SZ_1M) - (192*SZ_1K),
 157                 .size           = (20 * SZ_1M),
 158         },
 159 };
 160
 161 static struct mtd_partition __initdata jive_imageB_nand_part[] = {
 162
 163 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
 164         /* Don't allow access to the bootloader from linux */
 165         {
 166                 .name           = "uboot",
 167                 .offset         = 0,
 168                 .size           = (160 * SZ_1K),
 169                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 170         },
 171
 172         /* spare */
 173         {
 174                 .name           = "spare",
 175                 .offset         = (176 * SZ_1K),
 176                 .size           = (16 * SZ_1K),
 177         },
 178 #endif
 179
 180         /* booted images */
 181         {
 182                 .name           = "kernel (ro)",
 183                 .offset         = (22 * SZ_1M),
 184                 .size           = (2 * SZ_1M) - (192 * SZ_1K),
 185                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 186         },
 187         {
 188                 .name           = "root (ro)",
 189                 .offset         = (24 * SZ_1M) - (192 * SZ_1K),
 190                 .size           = (20 * SZ_1M),
 191                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 192         },
 193
 194         /* yaffs */
 195         {
 196                 .name           = "yaffs",
 197                 .offset         = (44 * SZ_1M),
 198                 .size           = (20 * SZ_1M),
 199         },
 200
 201         /* bootloader environment */
 202         {
 203                 .name           = "env",
 204                 .offset         = (160 * SZ_1K),
 205                 .size           = (16 * SZ_1K),
 206         },
 207
 208         /* upgrade images */
 209         {
 210                 .name           = "zimage",
 211                 .offset         = (192 * SZ_1K),
 212                 .size           = (2 * SZ_1M) - (192 * SZ_1K),
 213         }, {
 214                 .name           = "cramfs",
 215                 .offset         = (2 * SZ_1M),
 216                 .size           = (20 * SZ_1M),
 217         },
 218 };
 219
 220 static struct s3c2410_nand_set __initdata jive_nand_sets[] = {
 221         [0] = {
 222                 .name           = "flash",
 223                 .nr_chips       = 1,
 224                 .nr_partitions  = ARRAY_SIZE(jive_imageA_nand_part),
 225                 .partitions     = jive_imageA_nand_part,
 226         },
 227 };
 228
 229 static struct s3c2410_platform_nand __initdata jive_nand_info = {
 230         /* set taken from osiris nand timings, possibly still conservative */
 231         .tacls          = 30,
 232         .twrph0         = 55,
 233         .twrph1         = 40,
 234         .sets           = jive_nand_sets,
 235         .nr_sets        = ARRAY_SIZE(jive_nand_sets),
 236 };
 237
 238 static int __init jive_mtdset(char *options)
 239 {
 240         struct s3c2410_nand_set *nand = &jive_nand_sets[0];
 241         unsigned long set;
 242
 243         if (options == NULL || options[0] == '\0')
 244                 return 0;
 245
 246         if (strict_strtoul(options, 10, &set)) {
 247                 printk(KERN_ERR "failed to parse mtdset=%s\n", options);
 248                 return 0;
 249         }
 250
 251         switch (set) {
 252         case 1:
 253                 nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
 254                 nand->partitions = jive_imageB_nand_part;
 255         case 0:
 256                 /* this is already setup in the nand info */
 257                 break;
 258         default:
 259                 printk(KERN_ERR "Unknown mtd set %ld specified,"
 260                        "using default.", set);
 261         }
 262
 263         return 0;
 264 }
 265
 266 /* parse the mtdset= option given to the kernel command line */
 267 __setup("mtdset=", jive_mtdset);
 268
 269 /* LCD timing and setup */
 270
 271 #define LCD_XRES         (240)
 272 #define LCD_YRES         (320)
 273 #define LCD_LEFT_MARGIN  (12)
 274 #define LCD_RIGHT_MARGIN (12)
 275 #define LCD_LOWER_MARGIN (12)
 276 #define LCD_UPPER_MARGIN (12)
 277 #define LCD_VSYNC        (2)
 278 #define LCD_HSYNC        (2)
 279
 280 #define LCD_REFRESH      (60)
 281
 282 #define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
 283 #define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
 284
 285 static struct s3c2410fb_display jive_vgg2432a4_display[] = {
 286         [0] = {
 287                 .width          = LCD_XRES,
 288                 .height         = LCD_YRES,
 289                 .xres           = LCD_XRES,
 290                 .yres           = LCD_YRES,
 291                 .left_margin    = LCD_LEFT_MARGIN,
 292                 .right_margin   = LCD_RIGHT_MARGIN,
 293                 .upper_margin   = LCD_UPPER_MARGIN,
 294                 .lower_margin   = LCD_LOWER_MARGIN,
 295                 .hsync_len      = LCD_HSYNC,
 296                 .vsync_len      = LCD_VSYNC,
 297
 298                 .pixclock       = (1000000000000LL /
 299                                    (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
 300
 301                 .bpp            = 16,
 302                 .type           = (S3C2410_LCDCON1_TFT16BPP |
 303                                    S3C2410_LCDCON1_TFT),
 304
 305                 .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
 306                                    S3C2410_LCDCON5_INVVLINE |
 307                                    S3C2410_LCDCON5_INVVFRAME |
 308                                    S3C2410_LCDCON5_INVVDEN |
 309                                    S3C2410_LCDCON5_PWREN),
 310         },
 311 };
 312
 313 /* todo - put into gpio header */
 314
 315 #define S3C2410_GPCCON_MASK(x)  (3 << ((x) * 2))
 316 #define S3C2410_GPDCON_MASK(x)  (3 << ((x) * 2))
 317
 318 static struct s3c2410fb_mach_info jive_lcd_config = {
 319         .displays        = jive_vgg2432a4_display,
 320         .num_displays    = ARRAY_SIZE(jive_vgg2432a4_display),
 321         .default_display = 0,
 322
 323         /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
 324          * and disable the pull down resistors on pins we are using for LCD
 325          * data. */
 326
 327         .gpcup          = (0xf << 1) | (0x3f << 10),
 328
 329         .gpccon         = (S3C2410_GPC1_VCLK   | S3C2410_GPC2_VLINE |
 330                            S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
 331                            S3C2410_GPC10_VD2   | S3C2410_GPC11_VD3 |
 332                            S3C2410_GPC12_VD4   | S3C2410_GPC13_VD5 |
 333                            S3C2410_GPC14_VD6   | S3C2410_GPC15_VD7),
 334
 335         .gpccon_mask    = (S3C2410_GPCCON_MASK(1)  | S3C2410_GPCCON_MASK(2)  |
 336                            S3C2410_GPCCON_MASK(3)  | S3C2410_GPCCON_MASK(4)  |
 337                            S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
 338                            S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
 339                            S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
 340
 341         .gpdup          = (0x3f << 2) | (0x3f << 10),
 342
 343         .gpdcon         = (S3C2410_GPD2_VD10  | S3C2410_GPD3_VD11 |
 344                            S3C2410_GPD4_VD12  | S3C2410_GPD5_VD13 |
 345                            S3C2410_GPD6_VD14  | S3C2410_GPD7_VD15 |
 346                            S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
 347                            S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
 348                            S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
 349
 350         .gpdcon_mask    = (S3C2410_GPDCON_MASK(2)  | S3C2410_GPDCON_MASK(3) |
 351                            S3C2410_GPDCON_MASK(4)  | S3C2410_GPDCON_MASK(5) |
 352                            S3C2410_GPDCON_MASK(6)  | S3C2410_GPDCON_MASK(7) |
 353                            S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
 354                            S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
 355                            S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
 356 };
 357
 358 /* ILI9320 support. */
 359
 360 static void jive_lcm_reset(unsigned int set)
 361 {
 362         printk(KERN_DEBUG "%s(%d)\n", __func__, set);
 363
 364         gpio_set_value(S3C2410_GPG(13), set);
 365 }
 366
 367 #undef LCD_UPPER_MARGIN
 368 #define LCD_UPPER_MARGIN 2
 369
 370 static struct ili9320_platdata jive_lcm_config = {
 371         .hsize          = LCD_XRES,
 372         .vsize          = LCD_YRES,
 373
 374         .reset          = jive_lcm_reset,
 375         .suspend        = ILI9320_SUSPEND_DEEP,
 376
 377         .entry_mode     = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
 378         .display2       = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
 379                            ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
 380         .display3       = 0x0,
 381         .display4       = 0x0,
 382         .rgb_if1        = (ILI9320_RGBIF1_RIM_RGB18 |
 383                            ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
 384         .rgb_if2        = ILI9320_RGBIF2_DPL,
 385         .interface2     = 0x0,
 386         .interface3     = 0x3,
 387         .interface4     = (ILI9320_INTERFACE4_RTNE(16) |
 388                            ILI9320_INTERFACE4_DIVE(1)),
 389         .interface5     = 0x0,
 390         .interface6     = 0x0,
 391 };
 392
 393 /* LCD SPI support */
 394
 395 static struct spi_gpio_platform_data jive_lcd_spi = {
 396         .sck            = S3C2410_GPG(8),
 397         .mosi           = S3C2410_GPB(8),
 398         .miso           = SPI_GPIO_NO_MISO,
 399 };
 400
 401 static struct platform_device jive_device_lcdspi = {
 402         .name           = "spi-gpio",
 403         .id             = 1,
 404         .dev.platform_data = &jive_lcd_spi,
 405 };
 406
 407
 408 /* WM8750 audio code SPI definition */
 409
 410 static struct spi_gpio_platform_data jive_wm8750_spi = {
 411         .sck            = S3C2410_GPB(4),
 412         .mosi           = S3C2410_GPB(9),
 413         .miso           = SPI_GPIO_NO_MISO,
 414 };
 415
 416 static struct platform_device jive_device_wm8750 = {
 417         .name           = "spi-gpio",
 418         .id             = 2,
 419         .dev.platform_data = &jive_wm8750_spi,
 420 };
 421
 422 /* JIVE SPI devices. */
 423
 424 static struct spi_board_info __initdata jive_spi_devs[] = {
 425         [0] = {
 426                 .modalias       = "VGG2432A4",
 427                 .bus_num        = 1,
 428                 .chip_select    = 0,
 429                 .mode           = SPI_MODE_3,   /* CPOL=1, CPHA=1 */
 430                 .max_speed_hz   = 100000,
 431                 .platform_data  = &jive_lcm_config,
 432                 .controller_data = (void *)S3C2410_GPB(7),
 433         }, {
 434                 .modalias       = "WM8750",
 435                 .bus_num        = 2,
 436                 .chip_select    = 0,
 437                 .mode           = SPI_MODE_0,   /* CPOL=0, CPHA=0 */
 438                 .max_speed_hz   = 100000,
 439                 .controller_data = (void *)S3C2410_GPH(10),
 440         },
 441 };
 442
 443 /* I2C bus and device configuration. */
 444
 445 static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
 446         .frequency      = 80 * 1000,
 447         .flags          = S3C_IICFLG_FILTER,
 448         .sda_delay      = 2,
 449 };
 450
 451 static struct i2c_board_info jive_i2c_devs[] __initdata = {
 452         [0] = {
 453                 I2C_BOARD_INFO("lis302dl", 0x1c),
 454                 .irq    = IRQ_EINT14,
 455         },
 456 };
 457
 458 /* The platform devices being used. */
 459
 460 static struct platform_device *jive_devices[] __initdata = {
 461         &s3c_device_ohci,
 462         &s3c_device_rtc,
 463         &s3c_device_wdt,
 464         &s3c_device_i2c0,
 465         &s3c_device_lcd,
 466         &jive_device_lcdspi,
 467         &jive_device_wm8750,
 468         &s3c_device_nand,
 469         &s3c_device_usbgadget,
 470         &s3c2412_device_dma,
 471 };
 472
 473 static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
 474         .vbus_pin       = S3C2410_GPG(1),               /* detect is on GPG1 */
 475 };
 476
 477 /* Jive power management device */
 478
 479 #ifdef CONFIG_PM
 480 static int jive_pm_suspend(void)
 481 {
 482         /* Write the magic value u-boot uses to check for resume into
 483          * the INFORM0 register, and ensure INFORM1 is set to the
 484          * correct address to resume from. */
 485
 486         __raw_writel(0x2BED, S3C2412_INFORM0);
 487         __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
 488
 489         return 0;
 490 }
 491
 492 static void jive_pm_resume(void)
 493 {
 494         __raw_writel(0x0, S3C2412_INFORM0);
 495 }
 496
 497 #else
 498 #define jive_pm_suspend NULL
 499 #define jive_pm_resume NULL
 500 #endif
 501
 502 static struct syscore_ops jive_pm_syscore_ops = {
 503         .suspend        = jive_pm_suspend,
 504         .resume         = jive_pm_resume,
 505 };
 506
 507 static void __init jive_map_io(void)
 508 {
 509         s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
 510         s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
 511         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 512 }
 513
 514 static void __init jive_init_time(void)
 515 {
 516         s3c2412_init_clocks(12000000);
 517         samsung_timer_init();
 518 }
 519
 520 static void jive_power_off(void)
 521 {
 522         printk(KERN_INFO "powering system down...\n");
 523
 524         gpio_request_one(S3C2410_GPC(5), GPIOF_OUT_INIT_HIGH, NULL);
 525         gpio_free(S3C2410_GPC(5));
 526 }
 527
 528 static void __init jive_machine_init(void)
 529 {
 530         /* register system core operations for managing low level suspend */
 531
 532         register_syscore_ops(&jive_pm_syscore_ops);
 533
 534         /* write our sleep configurations for the IO. Pull down all unused
 535          * IO, ensure that we have turned off all peripherals we do not
 536          * need, and configure the ones we do need. */
 537
 538         /* Port B sleep */
 539
 540         __raw_writel(S3C2412_SLPCON_IN(0)   |
 541                      S3C2412_SLPCON_PULL(1) |
 542                      S3C2412_SLPCON_HIGH(2) |
 543                      S3C2412_SLPCON_PULL(3) |
 544                      S3C2412_SLPCON_PULL(4) |
 545                      S3C2412_SLPCON_PULL(5) |
 546                      S3C2412_SLPCON_PULL(6) |
 547                      S3C2412_SLPCON_HIGH(7) |
 548                      S3C2412_SLPCON_PULL(8) |
 549                      S3C2412_SLPCON_PULL(9) |
 550                      S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
 551
 552         /* Port C sleep */
 553
 554         __raw_writel(S3C2412_SLPCON_PULL(0) |
 555                      S3C2412_SLPCON_PULL(1) |
 556                      S3C2412_SLPCON_PULL(2) |
 557                      S3C2412_SLPCON_PULL(3) |
 558                      S3C2412_SLPCON_PULL(4) |
 559                      S3C2412_SLPCON_PULL(5) |
 560                      S3C2412_SLPCON_LOW(6)  |
 561                      S3C2412_SLPCON_PULL(6) |
 562                      S3C2412_SLPCON_PULL(7) |
 563                      S3C2412_SLPCON_PULL(8) |
 564                      S3C2412_SLPCON_PULL(9) |
 565                      S3C2412_SLPCON_PULL(10) |
 566                      S3C2412_SLPCON_PULL(11) |
 567                      S3C2412_SLPCON_PULL(12) |
 568                      S3C2412_SLPCON_PULL(13) |
 569                      S3C2412_SLPCON_PULL(14) |
 570                      S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
 571
 572         /* Port D sleep */
 573
 574         __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
 575
 576         /* Port F sleep */
 577
 578         __raw_writel(S3C2412_SLPCON_LOW(0)  |
 579                      S3C2412_SLPCON_LOW(1)  |
 580                      S3C2412_SLPCON_LOW(2)  |
 581                      S3C2412_SLPCON_EINT(3) |
 582                      S3C2412_SLPCON_EINT(4) |
 583                      S3C2412_SLPCON_EINT(5) |
 584                      S3C2412_SLPCON_EINT(6) |
 585                      S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
 586
 587         /* Port G sleep */
 588
 589         __raw_writel(S3C2412_SLPCON_IN(0)    |
 590                      S3C2412_SLPCON_IN(1)    |
 591                      S3C2412_SLPCON_IN(2)    |
 592                      S3C2412_SLPCON_IN(3)    |
 593                      S3C2412_SLPCON_IN(4)    |
 594                      S3C2412_SLPCON_IN(5)    |
 595                      S3C2412_SLPCON_IN(6)    |
 596                      S3C2412_SLPCON_IN(7)    |
 597                      S3C2412_SLPCON_PULL(8)  |
 598                      S3C2412_SLPCON_PULL(9)  |
 599                      S3C2412_SLPCON_IN(10)   |
 600                      S3C2412_SLPCON_PULL(11) |
 601                      S3C2412_SLPCON_PULL(12) |
 602                      S3C2412_SLPCON_PULL(13) |
 603                      S3C2412_SLPCON_IN(14)   |
 604                      S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
 605
 606         /* Port H sleep */
 607
 608         __raw_writel(S3C2412_SLPCON_PULL(0) |
 609                      S3C2412_SLPCON_PULL(1) |
 610                      S3C2412_SLPCON_PULL(2) |
 611                      S3C2412_SLPCON_PULL(3) |
 612                      S3C2412_SLPCON_PULL(4) |
 613                      S3C2412_SLPCON_PULL(5) |
 614                      S3C2412_SLPCON_PULL(6) |
 615                      S3C2412_SLPCON_IN(7)   |
 616                      S3C2412_SLPCON_IN(8)   |
 617                      S3C2412_SLPCON_PULL(9) |
 618                      S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
 619
 620         /* initialise the power management now we've setup everything. */
 621
 622         s3c_pm_init();
 623
 624         /** TODO - check that this is after the cmdline option! */
 625         s3c_nand_set_platdata(&jive_nand_info);
 626
 627         /* initialise the spi */
 628
 629         gpio_request(S3C2410_GPG(13), "lcm reset");
 630         gpio_direction_output(S3C2410_GPG(13), 0);
 631
 632         gpio_request(S3C2410_GPB(7), "jive spi");
 633         gpio_direction_output(S3C2410_GPB(7), 1);
 634
 635         gpio_request_one(S3C2410_GPB(6), GPIOF_OUT_INIT_LOW, NULL);
 636         gpio_free(S3C2410_GPB(6));
 637
 638         gpio_request_one(S3C2410_GPG(8), GPIOF_OUT_INIT_HIGH, NULL);
 639         gpio_free(S3C2410_GPG(8));
 640
 641         /* initialise the WM8750 spi */
 642
 643         gpio_request(S3C2410_GPH(10), "jive wm8750 spi");
 644         gpio_direction_output(S3C2410_GPH(10), 1);
 645
 646         /* Turn off suspend on both USB ports, and switch the
 647          * selectable USB port to USB device mode. */
 648
 649         s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
 650                               S3C2410_MISCCR_USBSUSPND0 |
 651                               S3C2410_MISCCR_USBSUSPND1, 0x0);
 652
 653         s3c24xx_udc_set_platdata(&jive_udc_cfg);
 654         s3c24xx_fb_set_platdata(&jive_lcd_config);
 655
 656         spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
 657
 658         s3c_i2c0_set_platdata(&jive_i2c_cfg);
 659         i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
 660
 661         pm_power_off = jive_power_off;
 662
 663         platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
 664 }
 665
 666 MACHINE_START(JIVE, "JIVE")
 667         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
 668         .atag_offset    = 0x100,
 669
 670         .init_irq       = s3c2412_init_irq,
 671         .map_io         = jive_map_io,
 672         .init_machine   = jive_machine_init,
 673         .init_time      = jive_init_time,
 674         .restart        = s3c2412_restart,
 675 MACHINE_END