Merge tag 'locks-v3.16-2' of git://git.samba.org/jlayton/linux
[linux/fpc-iii.git] / arch / arm / mach-s3c64xx / include / mach / irqs.h
blob67bbd1dd04c2f6c557017b1f60760add20db74f8
1 /* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C64XX - IRQ support
9 */
11 #ifndef __ASM_MACH_S3C64XX_IRQS_H
12 #define __ASM_MACH_S3C64XX_IRQS_H __FILE__
14 /* we keep the first set of CPU IRQs out of the range of
15 * the ISA space, so that the PC104 has them to itself
16 * and we don't end up having to do horrible things to the
17 * standard ISA drivers....
19 * note, since we're using the VICs, our start must be a
20 * mulitple of 32 to allow the common code to work
23 #define S3C_IRQ_OFFSET (32)
25 #define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET)
27 #define IRQ_VIC0_BASE S3C_IRQ(0)
28 #define IRQ_VIC1_BASE S3C_IRQ(32)
30 /* VIC based IRQs */
32 #define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x))
33 #define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x))
35 /* VIC0 */
37 #define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0)
38 #define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1)
39 #define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2)
40 #define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3)
41 #define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4)
42 #define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5)
43 #define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5)
44 #define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6)
45 #define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6)
46 #define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7)
47 #define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8)
48 #define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8)
49 #define IRQ_POST0 S3C64XX_IRQ_VIC0(9)
50 #define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10)
51 #define IRQ_2D S3C64XX_IRQ_VIC0(11)
52 #define IRQ_TVENC S3C64XX_IRQ_VIC0(12)
53 #define IRQ_SCALER S3C64XX_IRQ_VIC0(13)
54 #define IRQ_BATF S3C64XX_IRQ_VIC0(14)
55 #define IRQ_JPEG S3C64XX_IRQ_VIC0(15)
56 #define IRQ_MFC S3C64XX_IRQ_VIC0(16)
57 #define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17)
58 #define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18)
59 #define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19)
60 #define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20)
61 #define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21)
62 #define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22)
63 #define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23)
64 #define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24)
65 #define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25)
66 #define IRQ_WDT S3C64XX_IRQ_VIC0(26)
67 #define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27)
68 #define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28)
69 #define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29)
70 #define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30)
71 #define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31)
73 /* VIC1 */
75 #define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0)
76 #define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1)
77 #define IRQ_PCM0 S3C64XX_IRQ_VIC1(2)
78 #define IRQ_PCM1 S3C64XX_IRQ_VIC1(3)
79 #define IRQ_AC97 S3C64XX_IRQ_VIC1(4)
80 #define IRQ_UART0 S3C64XX_IRQ_VIC1(5)
81 #define IRQ_UART1 S3C64XX_IRQ_VIC1(6)
82 #define IRQ_UART2 S3C64XX_IRQ_VIC1(7)
83 #define IRQ_UART3 S3C64XX_IRQ_VIC1(8)
84 #define IRQ_DMA0 S3C64XX_IRQ_VIC1(9)
85 #define IRQ_DMA1 S3C64XX_IRQ_VIC1(10)
86 #define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11)
87 #define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12)
88 #define IRQ_NFC S3C64XX_IRQ_VIC1(13)
89 #define IRQ_CFCON S3C64XX_IRQ_VIC1(14)
90 #define IRQ_USBH S3C64XX_IRQ_VIC1(15)
91 #define IRQ_SPI0 S3C64XX_IRQ_VIC1(16)
92 #define IRQ_SPI1 S3C64XX_IRQ_VIC1(17)
93 #define IRQ_IIC S3C64XX_IRQ_VIC1(18)
94 #define IRQ_HSItx S3C64XX_IRQ_VIC1(19)
95 #define IRQ_HSIrx S3C64XX_IRQ_VIC1(20)
96 #define IRQ_RESERVED S3C64XX_IRQ_VIC1(21)
97 #define IRQ_MSM S3C64XX_IRQ_VIC1(22)
98 #define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23)
99 #define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24)
100 #define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25)
101 #define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */
102 #define IRQ_OTG S3C64XX_IRQ_VIC1(26)
103 #define IRQ_IRDA S3C64XX_IRQ_VIC1(27)
104 #define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28)
105 #define IRQ_SEC S3C64XX_IRQ_VIC1(29)
106 #define IRQ_PENDN S3C64XX_IRQ_VIC1(30)
107 #define IRQ_TC IRQ_PENDN
108 #define IRQ_ADC S3C64XX_IRQ_VIC1(31)
110 /* compatibility for device defines */
112 #define IRQ_IIC1 IRQ_S3C6410_IIC1
114 /* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
115 * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
116 * which we place after the pair of VICs. */
118 #define S3C_IRQ_EINT_BASE S3C_IRQ(64+5)
120 #define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE)
121 #define IRQ_EINT(x) S3C_EINT(x)
122 #define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0))
124 /* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
125 * that they are sourced from the GPIO pins but with a different scheme for
126 * priority and source indication.
128 * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
129 * interrupts, but for historical reasons they are kept apart from these
130 * next interrupts.
132 * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
133 * machine specific support files.
136 #define IRQ_EINT_GROUP1_NR (15)
137 #define IRQ_EINT_GROUP2_NR (8)
138 #define IRQ_EINT_GROUP3_NR (5)
139 #define IRQ_EINT_GROUP4_NR (14)
140 #define IRQ_EINT_GROUP5_NR (7)
141 #define IRQ_EINT_GROUP6_NR (10)
142 #define IRQ_EINT_GROUP7_NR (16)
143 #define IRQ_EINT_GROUP8_NR (15)
144 #define IRQ_EINT_GROUP9_NR (9)
146 #define IRQ_EINT_GROUP_BASE S3C_EINT(28)
147 #define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00)
148 #define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
149 #define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
150 #define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR)
151 #define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR)
152 #define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
153 #define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
154 #define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR)
155 #define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR)
157 #define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no))
159 /* Define a group of interrupts for board-specific use (eg, for MFD
160 * interrupt controllers). */
161 #define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
163 #ifdef CONFIG_MACH_WLF_CRAGG_6410
164 #define IRQ_BOARD_NR 160
165 #elif defined(CONFIG_SMDK6410_WM1190_EV1)
166 #define IRQ_BOARD_NR 64
167 #elif defined(CONFIG_SMDK6410_WM1192_EV1)
168 #define IRQ_BOARD_NR 64
169 #else
170 #define IRQ_BOARD_NR 16
171 #endif
173 #define IRQ_BOARD_END (IRQ_BOARD_START + IRQ_BOARD_NR)
175 /* Set the default NR_IRQS */
177 #define NR_IRQS (IRQ_BOARD_END + 1)
179 /* Compatibility */
181 #define IRQ_ONENAND IRQ_ONENAND0
182 #define IRQ_I2S0 IRQ_S3C6410_IIS
184 #endif /* __ASM_MACH_S3C64XX_IRQS_H */