arch/arm/mach-s3c64xx/include/mach/regs-gpio.h

   1 /* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h
   2  *
   3  * Copyright 2008 Openmoko, Inc.
   4  * Copyright 2008 Simtec Electronics
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *      http://armlinux.simtec.co.uk/
   7  *
   8  * S3C64XX - GPIO register definitions
   9  */
  10
  11 #ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H
  12 #define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__
  13
  14 /* Base addresses for each of the banks */
  15
  16 #define S3C64XX_GPIOREG(reg)    (S3C64XX_VA_GPIO + (reg))
  17
  18 #define S3C64XX_GPA_BASE        S3C64XX_GPIOREG(0x0000)
  19 #define S3C64XX_GPB_BASE        S3C64XX_GPIOREG(0x0020)
  20 #define S3C64XX_GPC_BASE        S3C64XX_GPIOREG(0x0040)
  21 #define S3C64XX_GPD_BASE        S3C64XX_GPIOREG(0x0060)
  22 #define S3C64XX_GPE_BASE        S3C64XX_GPIOREG(0x0080)
  23 #define S3C64XX_GPF_BASE        S3C64XX_GPIOREG(0x00A0)
  24 #define S3C64XX_GPG_BASE        S3C64XX_GPIOREG(0x00C0)
  25 #define S3C64XX_GPH_BASE        S3C64XX_GPIOREG(0x00E0)
  26 #define S3C64XX_GPI_BASE        S3C64XX_GPIOREG(0x0100)
  27 #define S3C64XX_GPJ_BASE        S3C64XX_GPIOREG(0x0120)
  28 #define S3C64XX_GPK_BASE        S3C64XX_GPIOREG(0x0800)
  29 #define S3C64XX_GPL_BASE        S3C64XX_GPIOREG(0x0810)
  30 #define S3C64XX_GPM_BASE        S3C64XX_GPIOREG(0x0820)
  31 #define S3C64XX_GPN_BASE        S3C64XX_GPIOREG(0x0830)
  32 #define S3C64XX_GPO_BASE        S3C64XX_GPIOREG(0x0140)
  33 #define S3C64XX_GPP_BASE        S3C64XX_GPIOREG(0x0160)
  34 #define S3C64XX_GPQ_BASE        S3C64XX_GPIOREG(0x0180)
  35
  36 /* SPCON */
  37
  38 #define S3C64XX_SPCON           S3C64XX_GPIOREG(0x1A0)
  39
  40 #define S3C64XX_SPCON_DRVCON_CAM_MASK           (0x3 << 30)
  41 #define S3C64XX_SPCON_DRVCON_CAM_SHIFT          (30)
  42 #define S3C64XX_SPCON_DRVCON_CAM_2mA            (0x0 << 30)
  43 #define S3C64XX_SPCON_DRVCON_CAM_4mA            (0x1 << 30)
  44 #define S3C64XX_SPCON_DRVCON_CAM_7mA            (0x2 << 30)
  45 #define S3C64XX_SPCON_DRVCON_CAM_9mA            (0x3 << 30)
  46
  47 #define S3C64XX_SPCON_DRVCON_HSSPI_MASK         (0x3 << 28)
  48 #define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT        (28)
  49 #define S3C64XX_SPCON_DRVCON_HSSPI_2mA          (0x0 << 28)
  50 #define S3C64XX_SPCON_DRVCON_HSSPI_4mA          (0x1 << 28)
  51 #define S3C64XX_SPCON_DRVCON_HSSPI_7mA          (0x2 << 28)
  52 #define S3C64XX_SPCON_DRVCON_HSSPI_9mA          (0x3 << 28)
  53
  54 #define S3C64XX_SPCON_DRVCON_HSMMC_MASK         (0x3 << 26)
  55 #define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT        (26)
  56 #define S3C64XX_SPCON_DRVCON_HSMMC_2mA          (0x0 << 26)
  57 #define S3C64XX_SPCON_DRVCON_HSMMC_4mA          (0x1 << 26)
  58 #define S3C64XX_SPCON_DRVCON_HSMMC_7mA          (0x2 << 26)
  59 #define S3C64XX_SPCON_DRVCON_HSMMC_9mA          (0x3 << 26)
  60
  61 #define S3C64XX_SPCON_DRVCON_LCD_MASK           (0x3 << 24)
  62 #define S3C64XX_SPCON_DRVCON_LCD_SHIFT          (24)
  63 #define S3C64XX_SPCON_DRVCON_LCD_2mA            (0x0 << 24)
  64 #define S3C64XX_SPCON_DRVCON_LCD_4mA            (0x1 << 24)
  65 #define S3C64XX_SPCON_DRVCON_LCD_7mA            (0x2 << 24)
  66 #define S3C64XX_SPCON_DRVCON_LCD_9mA            (0x3 << 24)
  67
  68 #define S3C64XX_SPCON_DRVCON_MODEM_MASK         (0x3 << 22)
  69 #define S3C64XX_SPCON_DRVCON_MODEM_SHIFT        (22)
  70 #define S3C64XX_SPCON_DRVCON_MODEM_2mA          (0x0 << 22)
  71 #define S3C64XX_SPCON_DRVCON_MODEM_4mA          (0x1 << 22)
  72 #define S3C64XX_SPCON_DRVCON_MODEM_7mA          (0x2 << 22)
  73 #define S3C64XX_SPCON_DRVCON_MODEM_9mA          (0x3 << 22)
  74
  75 #define S3C64XX_SPCON_nRSTOUT_OEN               (1 << 21)
  76
  77 #define S3C64XX_SPCON_DRVCON_SPICLK1_MASK       (0x3 << 18)
  78 #define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT      (18)
  79 #define S3C64XX_SPCON_DRVCON_SPICLK1_2mA        (0x0 << 18)
  80 #define S3C64XX_SPCON_DRVCON_SPICLK1_4mA        (0x1 << 18)
  81 #define S3C64XX_SPCON_DRVCON_SPICLK1_7mA        (0x2 << 18)
  82 #define S3C64XX_SPCON_DRVCON_SPICLK1_9mA        (0x3 << 18)
  83
  84 #define S3C64XX_SPCON_MEM1_DQS_PUD_MASK         (0x3 << 16)
  85 #define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT        (16)
  86 #define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED     (0x0 << 16)
  87 #define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN         (0x1 << 16)
  88 #define S3C64XX_SPCON_MEM1_DQS_PUD_UP           (0x2 << 16)
  89
  90 #define S3C64XX_SPCON_MEM1_D_PUD1_MASK          (0x3 << 14)
  91 #define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT         (14)
  92 #define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED      (0x0 << 14)
  93 #define S3C64XX_SPCON_MEM1_D_PUD1_DOWN          (0x1 << 14)
  94 #define S3C64XX_SPCON_MEM1_D_PUD1_UP            (0x2 << 14)
  95
  96 #define S3C64XX_SPCON_MEM1_D_PUD0_MASK          (0x3 << 12)
  97 #define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT         (12)
  98 #define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED      (0x0 << 12)
  99 #define S3C64XX_SPCON_MEM1_D_PUD0_DOWN          (0x1 << 12)
 100 #define S3C64XX_SPCON_MEM1_D_PUD0_UP            (0x2 << 12)
 101
 102 #define S3C64XX_SPCON_MEM0_D_PUD_MASK           (0x3 << 8)
 103 #define S3C64XX_SPCON_MEM0_D_PUD_SHIFT          (8)
 104 #define S3C64XX_SPCON_MEM0_D_PUD_DISABLED       (0x0 << 8)
 105 #define S3C64XX_SPCON_MEM0_D_PUD_DOWN           (0x1 << 8)
 106 #define S3C64XX_SPCON_MEM0_D_PUD_UP             (0x2 << 8)
 107
 108 #define S3C64XX_SPCON_USBH_DMPD                 (1 << 7)
 109 #define S3C64XX_SPCON_USBH_DPPD                 (1 << 6)
 110 #define S3C64XX_SPCON_USBH_PUSW2                (1 << 5)
 111 #define S3C64XX_SPCON_USBH_PUSW1                (1 << 4)
 112 #define S3C64XX_SPCON_USBH_SUSPND               (1 << 3)
 113
 114 #define S3C64XX_SPCON_LCD_SEL_MASK              (0x3 << 0)
 115 #define S3C64XX_SPCON_LCD_SEL_SHIFT             (0)
 116 #define S3C64XX_SPCON_LCD_SEL_HOST              (0x0 << 0)
 117 #define S3C64XX_SPCON_LCD_SEL_RGB               (0x1 << 0)
 118 #define S3C64XX_SPCON_LCD_SEL_606_656           (0x2 << 0)
 119
 120
 121 /* External interrupt registers */
 122
 123 #define S3C64XX_EINT12CON       S3C64XX_GPIOREG(0x200)
 124 #define S3C64XX_EINT34CON       S3C64XX_GPIOREG(0x204)
 125 #define S3C64XX_EINT56CON       S3C64XX_GPIOREG(0x208)
 126 #define S3C64XX_EINT78CON       S3C64XX_GPIOREG(0x20C)
 127 #define S3C64XX_EINT9CON        S3C64XX_GPIOREG(0x210)
 128
 129 #define S3C64XX_EINT12FLTCON    S3C64XX_GPIOREG(0x220)
 130 #define S3C64XX_EINT34FLTCON    S3C64XX_GPIOREG(0x224)
 131 #define S3C64XX_EINT56FLTCON    S3C64XX_GPIOREG(0x228)
 132 #define S3C64XX_EINT78FLTCON    S3C64XX_GPIOREG(0x22C)
 133 #define S3C64XX_EINT9FLTCON     S3C64XX_GPIOREG(0x230)
 134
 135 #define S3C64XX_EINT12MASK      S3C64XX_GPIOREG(0x240)
 136 #define S3C64XX_EINT34MASK      S3C64XX_GPIOREG(0x244)
 137 #define S3C64XX_EINT56MASK      S3C64XX_GPIOREG(0x248)
 138 #define S3C64XX_EINT78MASK      S3C64XX_GPIOREG(0x24C)
 139 #define S3C64XX_EINT9MASK       S3C64XX_GPIOREG(0x250)
 140
 141 #define S3C64XX_EINT12PEND      S3C64XX_GPIOREG(0x260)
 142 #define S3C64XX_EINT34PEND      S3C64XX_GPIOREG(0x264)
 143 #define S3C64XX_EINT56PEND      S3C64XX_GPIOREG(0x268)
 144 #define S3C64XX_EINT78PEND      S3C64XX_GPIOREG(0x26C)
 145 #define S3C64XX_EINT9PEND       S3C64XX_GPIOREG(0x270)
 146
 147 #define S3C64XX_PRIORITY        S3C64XX_GPIOREG(0x280)
 148 #define S3C64XX_PRIORITY_ARB(x) (1 << (x))
 149
 150 #define S3C64XX_SERVICE         S3C64XX_GPIOREG(0x284)
 151 #define S3C64XX_SERVICEPEND     S3C64XX_GPIOREG(0x288)
 152
 153 #define S3C64XX_EINT0CON0       S3C64XX_GPIOREG(0x900)
 154 #define S3C64XX_EINT0CON1       S3C64XX_GPIOREG(0x904)
 155 #define S3C64XX_EINT0FLTCON0    S3C64XX_GPIOREG(0x910)
 156 #define S3C64XX_EINT0FLTCON1    S3C64XX_GPIOREG(0x914)
 157 #define S3C64XX_EINT0FLTCON2    S3C64XX_GPIOREG(0x918)
 158 #define S3C64XX_EINT0FLTCON3    S3C64XX_GPIOREG(0x91C)
 159
 160 #define S3C64XX_EINT0MASK       S3C64XX_GPIOREG(0x920)
 161 #define S3C64XX_EINT0PEND       S3C64XX_GPIOREG(0x924)
 162
 163 /* GPIO sleep configuration */
 164
 165 #define S3C64XX_SPCONSLP        S3C64XX_GPIOREG(0x880)
 166
 167 #define S3C64XX_SPCONSLP_TDO_PULLDOWN   (1 << 14)
 168 #define S3C64XX_SPCONSLP_CKE1INIT       (1 << 5)
 169
 170 #define S3C64XX_SPCONSLP_RSTOUT_MASK    (0x3 << 12)
 171 #define S3C64XX_SPCONSLP_RSTOUT_OUT0    (0x0 << 12)
 172 #define S3C64XX_SPCONSLP_RSTOUT_OUT1    (0x1 << 12)
 173 #define S3C64XX_SPCONSLP_RSTOUT_HIZ     (0x2 << 12)
 174
 175 #define S3C64XX_SPCONSLP_KPCOL_MASK     (0x3 << 0)
 176 #define S3C64XX_SPCONSLP_KPCOL_OUT0     (0x0 << 0)
 177 #define S3C64XX_SPCONSLP_KPCOL_OUT1     (0x1 << 0)
 178 #define S3C64XX_SPCONSLP_KPCOL_INP      (0x2 << 0)
 179
 180
 181 #define S3C64XX_SLPEN           S3C64XX_GPIOREG(0x930)
 182
 183 #define S3C64XX_SLPEN_USE_xSLP          (1 << 0)
 184 #define S3C64XX_SLPEN_CFG_BYSLPEN       (1 << 1)
 185
 186 #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */
 187