Merge tag 'locks-v3.16-2' of git://git.samba.org/jlayton/linux
[linux/fpc-iii.git] / arch / arm / mach-shmobile / clock-r8a7740.c
blob50931e3c97c776b07c627584cfd206295dbbc52d
1 /*
2 * R8A7740 processor support
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/io.h>
23 #include <linux/sh_clk.h>
24 #include <linux/clkdev.h>
25 #include <mach/clock.h>
26 #include <mach/common.h>
27 #include <mach/r8a7740.h>
30 * | MDx | XTAL1/EXTAL1 | System | EXTALR |
31 * Clock |-------+-----------------+ clock | 32.768 | RCLK
32 * Mode | 2/1/0 | src MHz | source | KHz | source
33 * -------+-------+-----------------+-----------+--------+----------
34 * 0 | 0 0 0 | External 20~50 | XTAL1 | O | EXTALR
35 * 1 | 0 0 1 | Crystal 20~30 | XTAL1 | O | EXTALR
36 * 2 | 0 1 0 | External 40~50 | XTAL1 / 2 | O | EXTALR
37 * 3 | 0 1 1 | Crystal 40~50 | XTAL1 / 2 | O | EXTALR
38 * 4 | 1 0 0 | External 20~50 | XTAL1 | x | XTAL1 / 1024
39 * 5 | 1 0 1 | Crystal 20~30 | XTAL1 | x | XTAL1 / 1024
40 * 6 | 1 1 0 | External 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
41 * 7 | 1 1 1 | Crystal 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
44 /* CPG registers */
45 #define FRQCRA IOMEM(0xe6150000)
46 #define FRQCRB IOMEM(0xe6150004)
47 #define VCLKCR1 IOMEM(0xE6150008)
48 #define VCLKCR2 IOMEM(0xE615000c)
49 #define FRQCRC IOMEM(0xe61500e0)
50 #define FSIACKCR IOMEM(0xe6150018)
51 #define PLLC01CR IOMEM(0xe6150028)
53 #define SUBCKCR IOMEM(0xe6150080)
54 #define USBCKCR IOMEM(0xe615008c)
56 #define MSTPSR0 IOMEM(0xe6150030)
57 #define MSTPSR1 IOMEM(0xe6150038)
58 #define MSTPSR2 IOMEM(0xe6150040)
59 #define MSTPSR3 IOMEM(0xe6150048)
60 #define MSTPSR4 IOMEM(0xe615004c)
61 #define FSIBCKCR IOMEM(0xe6150090)
62 #define HDMICKCR IOMEM(0xe6150094)
63 #define SMSTPCR0 IOMEM(0xe6150130)
64 #define SMSTPCR1 IOMEM(0xe6150134)
65 #define SMSTPCR2 IOMEM(0xe6150138)
66 #define SMSTPCR3 IOMEM(0xe615013c)
67 #define SMSTPCR4 IOMEM(0xe6150140)
69 #define FSIDIVA IOMEM(0xFE1F8000)
70 #define FSIDIVB IOMEM(0xFE1F8008)
72 /* Fixed 32 KHz root clock from EXTALR pin */
73 static struct clk extalr_clk = {
74 .rate = 32768,
78 * 25MHz default rate for the EXTAL1 root input clock.
79 * If needed, reset this with clk_set_rate() from the platform code.
81 static struct clk extal1_clk = {
82 .rate = 25000000,
86 * 48MHz default rate for the EXTAL2 root input clock.
87 * If needed, reset this with clk_set_rate() from the platform code.
89 static struct clk extal2_clk = {
90 .rate = 48000000,
94 * 27MHz default rate for the DV_CLKI root input clock.
95 * If needed, reset this with clk_set_rate() from the platform code.
97 static struct clk dv_clk = {
98 .rate = 27000000,
101 SH_CLK_RATIO(div2, 1, 2);
102 SH_CLK_RATIO(div1k, 1, 1024);
104 SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2);
105 SH_FIXED_RATIO_CLK(extal1_div1024_clk, extal1_clk, div1k);
106 SH_FIXED_RATIO_CLK(extal1_div2048_clk, extal1_div2_clk, div1k);
107 SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2);
109 static struct sh_clk_ops followparent_clk_ops = {
110 .recalc = followparent_recalc,
113 /* Main clock */
114 static struct clk system_clk = {
115 .ops = &followparent_clk_ops,
118 SH_FIXED_RATIO_CLK(system_div2_clk, system_clk, div2);
120 /* r_clk */
121 static struct clk r_clk = {
122 .ops = &followparent_clk_ops,
125 /* PLLC0/PLLC1 */
126 static unsigned long pllc01_recalc(struct clk *clk)
128 unsigned long mult = 1;
130 if (__raw_readl(PLLC01CR) & (1 << 14))
131 mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1;
133 return clk->parent->rate * mult;
136 static struct sh_clk_ops pllc01_clk_ops = {
137 .recalc = pllc01_recalc,
140 static struct clk pllc0_clk = {
141 .ops = &pllc01_clk_ops,
142 .flags = CLK_ENABLE_ON_INIT,
143 .parent = &system_clk,
144 .enable_reg = (void __iomem *)FRQCRC,
147 static struct clk pllc1_clk = {
148 .ops = &pllc01_clk_ops,
149 .flags = CLK_ENABLE_ON_INIT,
150 .parent = &system_div2_clk,
151 .enable_reg = (void __iomem *)FRQCRA,
154 /* PLLC1 / 2 */
155 SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2);
157 /* USB clock */
159 * USBCKCR is controlling usb24 clock
160 * bit[7] : parent clock
161 * bit[6] : clock divide rate
162 * And this bit[7] is used as a "usb24s" from other devices.
163 * (Video clock / Sub clock / SPU clock)
164 * You can controll this clock as a below.
166 * struct clk *usb24 = clk_get(dev, "usb24");
167 * struct clk *usb24s = clk_get(NULL, "usb24s");
168 * struct clk *system = clk_get(NULL, "system_clk");
169 * int rate = clk_get_rate(system);
171 * clk_set_parent(usb24s, system); // for bit[7]
172 * clk_set_rate(usb24, rate / 2); // for bit[6]
174 static struct clk *usb24s_parents[] = {
175 [0] = &system_clk,
176 [1] = &extal2_clk
179 static int usb24s_enable(struct clk *clk)
181 __raw_writel(__raw_readl(USBCKCR) & ~(1 << 8), USBCKCR);
183 return 0;
186 static void usb24s_disable(struct clk *clk)
188 __raw_writel(__raw_readl(USBCKCR) | (1 << 8), USBCKCR);
191 static int usb24s_set_parent(struct clk *clk, struct clk *parent)
193 int i, ret;
194 u32 val;
196 if (!clk->parent_table || !clk->parent_num)
197 return -EINVAL;
199 /* Search the parent */
200 for (i = 0; i < clk->parent_num; i++)
201 if (clk->parent_table[i] == parent)
202 break;
204 if (i == clk->parent_num)
205 return -ENODEV;
207 ret = clk_reparent(clk, parent);
208 if (ret < 0)
209 return ret;
211 val = __raw_readl(USBCKCR);
212 val &= ~(1 << 7);
213 val |= i << 7;
214 __raw_writel(val, USBCKCR);
216 return 0;
219 static struct sh_clk_ops usb24s_clk_ops = {
220 .recalc = followparent_recalc,
221 .enable = usb24s_enable,
222 .disable = usb24s_disable,
223 .set_parent = usb24s_set_parent,
226 static struct clk usb24s_clk = {
227 .ops = &usb24s_clk_ops,
228 .parent_table = usb24s_parents,
229 .parent_num = ARRAY_SIZE(usb24s_parents),
230 .parent = &system_clk,
233 static unsigned long usb24_recalc(struct clk *clk)
235 return clk->parent->rate /
236 ((__raw_readl(USBCKCR) & (1 << 6)) ? 1 : 2);
239 static int usb24_set_rate(struct clk *clk, unsigned long rate)
241 u32 val;
243 /* closer to which ? parent->rate or parent->rate/2 */
244 val = __raw_readl(USBCKCR);
245 val &= ~(1 << 6);
246 val |= (rate > (clk->parent->rate / 4) * 3) << 6;
247 __raw_writel(val, USBCKCR);
249 return 0;
252 static struct sh_clk_ops usb24_clk_ops = {
253 .recalc = usb24_recalc,
254 .set_rate = usb24_set_rate,
257 static struct clk usb24_clk = {
258 .ops = &usb24_clk_ops,
259 .parent = &usb24s_clk,
262 /* External FSIACK/FSIBCK clock */
263 static struct clk fsiack_clk = {
266 static struct clk fsibck_clk = {
269 static struct clk *main_clks[] = {
270 &extalr_clk,
271 &extal1_clk,
272 &extal2_clk,
273 &extal1_div2_clk,
274 &extal1_div1024_clk,
275 &extal1_div2048_clk,
276 &extal2_div2_clk,
277 &dv_clk,
278 &system_clk,
279 &system_div2_clk,
280 &r_clk,
281 &pllc0_clk,
282 &pllc1_clk,
283 &pllc1_div2_clk,
284 &usb24s_clk,
285 &usb24_clk,
286 &fsiack_clk,
287 &fsibck_clk,
290 /* DIV4 clocks */
291 static void div4_kick(struct clk *clk)
293 unsigned long value;
295 /* set KICK bit in FRQCRB to update hardware setting */
296 value = __raw_readl(FRQCRB);
297 value |= (1 << 31);
298 __raw_writel(value, FRQCRB);
301 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
302 24, 32, 36, 48, 0, 72, 96, 0 };
304 static struct clk_div_mult_table div4_div_mult_table = {
305 .divisors = divisors,
306 .nr_divisors = ARRAY_SIZE(divisors),
309 static struct clk_div4_table div4_table = {
310 .div_mult_table = &div4_div_mult_table,
311 .kick = div4_kick,
314 enum {
315 DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
316 DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
317 DIV4_NR
320 static struct clk div4_clks[DIV4_NR] = {
321 [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
322 [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
323 [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
324 [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
325 [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
326 [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
327 [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0),
328 [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
329 [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
330 [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
331 [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
334 /* DIV6 reparent */
335 enum {
336 DIV6_HDMI,
337 DIV6_VCLK1, DIV6_VCLK2,
338 DIV6_FSIA, DIV6_FSIB,
339 DIV6_REPARENT_NR,
342 static struct clk *hdmi_parent[] = {
343 [0] = &pllc1_div2_clk,
344 [1] = &system_clk,
345 [2] = &dv_clk
348 static struct clk *vclk_parents[8] = {
349 [0] = &pllc1_div2_clk,
350 [2] = &dv_clk,
351 [3] = &usb24s_clk,
352 [4] = &extal1_div2_clk,
353 [5] = &extalr_clk,
356 static struct clk *fsia_parents[] = {
357 [0] = &pllc1_div2_clk,
358 [1] = &fsiack_clk, /* external clock */
361 static struct clk *fsib_parents[] = {
362 [0] = &pllc1_div2_clk,
363 [1] = &fsibck_clk, /* external clock */
366 static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
367 [DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0,
368 hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
369 [DIV6_VCLK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0,
370 vclk_parents, ARRAY_SIZE(vclk_parents), 12, 3),
371 [DIV6_VCLK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0,
372 vclk_parents, ARRAY_SIZE(vclk_parents), 12, 3),
373 [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
374 fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
375 [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
376 fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
379 /* DIV6 clocks */
380 enum {
381 DIV6_SUB,
382 DIV6_NR
385 static struct clk div6_clks[DIV6_NR] = {
386 [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
389 /* HDMI1/2 clock */
390 static unsigned long hdmi12_recalc(struct clk *clk)
392 u32 val = __raw_readl(HDMICKCR);
393 int shift = (int)clk->priv;
395 val >>= shift;
396 val &= 0x3;
398 return clk->parent->rate / (1 << val);
401 static int hdmi12_set_rate(struct clk *clk, unsigned long rate)
403 u32 val, mask;
404 int i, shift;
406 for (i = 0; i < 3; i++)
407 if (rate == clk->parent->rate / (1 << i))
408 goto find;
409 return -ENODEV;
411 find:
412 shift = (int)clk->priv;
414 val = __raw_readl(HDMICKCR);
415 mask = ~(0x3 << shift);
416 val = (val & mask) | i << shift;
417 __raw_writel(val, HDMICKCR);
419 return 0;
422 static struct sh_clk_ops hdmi12_clk_ops = {
423 .recalc = hdmi12_recalc,
424 .set_rate = hdmi12_set_rate,
427 static struct clk hdmi1_clk = {
428 .ops = &hdmi12_clk_ops,
429 .priv = (void *)9,
430 .parent = &div6_reparent_clks[DIV6_HDMI], /* late install */
433 static struct clk hdmi2_clk = {
434 .ops = &hdmi12_clk_ops,
435 .priv = (void *)11,
436 .parent = &div6_reparent_clks[DIV6_HDMI], /* late install */
439 static struct clk *late_main_clks[] = {
440 &hdmi1_clk,
441 &hdmi2_clk,
444 /* FSI DIV */
445 enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
447 static struct clk fsidivs[] = {
448 [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
449 [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
452 /* MSTP */
453 enum {
454 MSTP128, MSTP127, MSTP125,
455 MSTP116, MSTP111, MSTP100, MSTP117,
457 MSTP230,
458 MSTP222,
459 MSTP218, MSTP217, MSTP216, MSTP214,
460 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
462 MSTP329, MSTP328, MSTP323, MSTP320,
463 MSTP314, MSTP313, MSTP312,
464 MSTP309, MSTP304,
466 MSTP416, MSTP415, MSTP407, MSTP406,
468 MSTP_NR
471 static struct clk mstp_clks[MSTP_NR] = {
472 [MSTP128] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 28, 0), /* CEU21 */
473 [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 27, 0), /* CEU20 */
474 [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
475 [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
476 [MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
477 [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
478 [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
480 [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
481 [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
482 [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
483 [MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
484 [MSTP216] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
485 [MSTP214] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
486 [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
487 [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
488 [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
489 [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
490 [MSTP202] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
491 [MSTP201] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
492 [MSTP200] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
494 [MSTP329] = SH_CLK_MSTP32(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
495 [MSTP328] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 28, 0), /* FSI */
496 [MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
497 [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 20, 0), /* USBF */
498 [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
499 [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
500 [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
501 [MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 9, 0), /* GEther */
502 [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_CP], SMSTPCR3, 4, 0), /* TPU0 */
504 [MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 16, 0), /* USBHOST */
505 [MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
506 [MSTP407] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-Func */
507 [MSTP406] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 6, 0), /* USB Phy */
510 static struct clk_lookup lookups[] = {
511 /* main clocks */
512 CLKDEV_CON_ID("extalr", &extalr_clk),
513 CLKDEV_CON_ID("extal1", &extal1_clk),
514 CLKDEV_CON_ID("extal2", &extal2_clk),
515 CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
516 CLKDEV_CON_ID("extal1_div1024", &extal1_div1024_clk),
517 CLKDEV_CON_ID("extal1_div2048", &extal1_div2048_clk),
518 CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
519 CLKDEV_CON_ID("dv_clk", &dv_clk),
520 CLKDEV_CON_ID("system_clk", &system_clk),
521 CLKDEV_CON_ID("system_div2_clk", &system_div2_clk),
522 CLKDEV_CON_ID("r_clk", &r_clk),
523 CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
524 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
525 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
526 CLKDEV_CON_ID("usb24s", &usb24s_clk),
527 CLKDEV_CON_ID("hdmi1", &hdmi1_clk),
528 CLKDEV_CON_ID("hdmi2", &hdmi2_clk),
529 CLKDEV_CON_ID("video1", &div6_reparent_clks[DIV6_VCLK1]),
530 CLKDEV_CON_ID("video2", &div6_reparent_clks[DIV6_VCLK2]),
531 CLKDEV_CON_ID("fsiack", &fsiack_clk),
532 CLKDEV_CON_ID("fsibck", &fsibck_clk),
534 /* DIV4 clocks */
535 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
536 CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
537 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
538 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
539 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
540 CLKDEV_CON_ID("hpp_clk", &div4_clks[DIV4_HPP]),
541 CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
542 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
543 CLKDEV_CON_ID("m3_clk", &div4_clks[DIV4_M3]),
544 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
546 /* DIV6 clocks */
547 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
549 /* MSTP32 clocks */
550 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]),
551 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]),
552 CLKDEV_DEV_ID("fff20000.i2c", &mstp_clks[MSTP116]),
553 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]),
554 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]),
555 CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP128]),
557 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]),
558 CLKDEV_DEV_ID("e6c80000.sci", &mstp_clks[MSTP200]),
559 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]),
560 CLKDEV_DEV_ID("e6c70000.sci", &mstp_clks[MSTP201]),
561 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]),
562 CLKDEV_DEV_ID("e6c60000.sci", &mstp_clks[MSTP202]),
563 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
564 CLKDEV_DEV_ID("e6c50000.sci", &mstp_clks[MSTP203]),
565 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
566 CLKDEV_DEV_ID("e6c40000.sci", &mstp_clks[MSTP204]),
567 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]),
568 CLKDEV_DEV_ID("e6c30000.sci", &mstp_clks[MSTP206]),
569 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]),
570 CLKDEV_DEV_ID("e6cb0000.sci", &mstp_clks[MSTP207]),
571 CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]),
572 CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]),
573 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]),
574 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
575 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
576 CLKDEV_DEV_ID("e6cd0000.sci", &mstp_clks[MSTP222]),
577 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
578 CLKDEV_DEV_ID("e6cc0000.sci", &mstp_clks[MSTP230]),
580 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]),
581 CLKDEV_DEV_ID("fe1f0000.sound", &mstp_clks[MSTP328]),
582 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
583 CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]),
584 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]),
585 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
586 CLKDEV_DEV_ID("e6850000.sd", &mstp_clks[MSTP314]),
587 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
588 CLKDEV_DEV_ID("e6860000.sd", &mstp_clks[MSTP313]),
589 CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]),
590 CLKDEV_DEV_ID("e6bd0000.mmc", &mstp_clks[MSTP312]),
591 CLKDEV_DEV_ID("r8a7740-gether", &mstp_clks[MSTP309]),
592 CLKDEV_DEV_ID("e9a00000.ethernet", &mstp_clks[MSTP309]),
593 CLKDEV_DEV_ID("renesas-tpu-pwm", &mstp_clks[MSTP304]),
594 CLKDEV_DEV_ID("e6600000.pwm", &mstp_clks[MSTP304]),
596 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]),
597 CLKDEV_DEV_ID("e6870000.sd", &mstp_clks[MSTP415]),
599 /* ICK */
600 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP111]),
601 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]),
602 CLKDEV_ICK_ID("fck", "sh-cmt-48.1", &mstp_clks[MSTP329]),
603 CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]),
604 CLKDEV_ICK_ID("func", "renesas_usbhs", &mstp_clks[MSTP407]),
605 CLKDEV_ICK_ID("phy", "renesas_usbhs", &mstp_clks[MSTP406]),
606 CLKDEV_ICK_ID("pci", "renesas_usbhs", &div4_clks[DIV4_USBP]),
607 CLKDEV_ICK_ID("usb24", "renesas_usbhs", &usb24_clk),
608 CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
610 CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
611 CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
612 CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
613 CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
614 CLKDEV_ICK_ID("xcka", "sh_fsi2", &fsiack_clk),
615 CLKDEV_ICK_ID("xckb", "sh_fsi2", &fsibck_clk),
618 void __init r8a7740_clock_init(u8 md_ck)
620 int k, ret = 0;
622 /* detect system clock parent */
623 if (md_ck & MD_CK1)
624 system_clk.parent = &extal1_div2_clk;
625 else
626 system_clk.parent = &extal1_clk;
628 /* detect RCLK parent */
629 switch (md_ck & (MD_CK2 | MD_CK1)) {
630 case MD_CK2 | MD_CK1:
631 r_clk.parent = &extal1_div2048_clk;
632 break;
633 case MD_CK2:
634 r_clk.parent = &extal1_div1024_clk;
635 break;
636 case MD_CK1:
637 default:
638 r_clk.parent = &extalr_clk;
639 break;
642 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
643 ret = clk_register(main_clks[k]);
645 if (!ret)
646 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
648 if (!ret)
649 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
651 if (!ret)
652 ret = sh_clk_div6_reparent_register(div6_reparent_clks,
653 DIV6_REPARENT_NR);
655 if (!ret)
656 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
658 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
659 ret = clk_register(late_main_clks[k]);
661 if (!ret)
662 ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
664 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
666 if (!ret)
667 shmobile_clk_init();
668 else
669 panic("failed to setup r8a7740 clocks\n");