arch/arm/mach-shmobile/clock-r8a7791.c

   1 /*
   2  * r8a7791 clock framework support
   3  *
   4  * Copyright (C) 2013  Renesas Electronics Corporation
   5  * Copyright (C) 2013  Renesas Solutions Corp.
   6  * Copyright (C) 2013  Magnus Damm
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/io.h>
  23 #include <linux/kernel.h>
  24 #include <linux/sh_clk.h>
  25 #include <linux/clkdev.h>
  26 #include <mach/clock.h>
  27 #include <mach/common.h>
  28 #include <mach/rcar-gen2.h>
  29
  30 /*
  31  *   MD         EXTAL           PLL0    PLL1    PLL3
  32  * 14 13 19     (MHz)           *1      *1
  33  *---------------------------------------------------
  34  * 0  0  0      15 x 1          x172/2  x208/2  x106
  35  * 0  0  1      15 x 1          x172/2  x208/2  x88
  36  * 0  1  0      20 x 1          x130/2  x156/2  x80
  37  * 0  1  1      20 x 1          x130/2  x156/2  x66
  38  * 1  0  0      26 / 2          x200/2  x240/2  x122
  39  * 1  0  1      26 / 2          x200/2  x240/2  x102
  40  * 1  1  0      30 / 2          x172/2  x208/2  x106
  41  * 1  1  1      30 / 2          x172/2  x208/2  x88
  42  *
  43  * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
  44  *      see "p1 / 2" on R8A7791_CLOCK_ROOT() below
  45  */
  46
  47 #define CPG_BASE 0xe6150000
  48 #define CPG_LEN 0x1000
  49
  50 #define SMSTPCR0        0xE6150130
  51 #define SMSTPCR1        0xE6150134
  52 #define SMSTPCR2        0xe6150138
  53 #define SMSTPCR3        0xE615013C
  54 #define SMSTPCR5        0xE6150144
  55 #define SMSTPCR7        0xe615014c
  56 #define SMSTPCR8        0xE6150990
  57 #define SMSTPCR9        0xE6150994
  58 #define SMSTPCR10       0xE6150998
  59 #define SMSTPCR11       0xE615099C
  60
  61 #define MSTPSR1         IOMEM(0xe6150038)
  62 #define MSTPSR2         IOMEM(0xe6150040)
  63 #define MSTPSR3         IOMEM(0xe6150048)
  64 #define MSTPSR5         IOMEM(0xe615003c)
  65 #define MSTPSR7         IOMEM(0xe61501c4)
  66 #define MSTPSR8         IOMEM(0xe61509a0)
  67 #define MSTPSR9         IOMEM(0xe61509a4)
  68 #define MSTPSR11        IOMEM(0xe61509ac)
  69
  70 #define SDCKCR          0xE6150074
  71 #define SD1CKCR         0xE6150078
  72 #define SD2CKCR         0xE615026c
  73 #define MMC0CKCR        0xE6150240
  74 #define MMC1CKCR        0xE6150244
  75 #define SSPCKCR         0xE6150248
  76 #define SSPRSCKCR       0xE615024C
  77
  78 static struct clk_mapping cpg_mapping = {
  79         .phys   = CPG_BASE,
  80         .len    = CPG_LEN,
  81 };
  82
  83 static struct clk extal_clk = {
  84         /* .rate will be updated on r8a7791_clock_init() */
  85         .mapping        = &cpg_mapping,
  86 };
  87
  88 static struct sh_clk_ops followparent_clk_ops = {
  89         .recalc = followparent_recalc,
  90 };
  91
  92 static struct clk main_clk = {
  93         /* .parent will be set r8a73a4_clock_init */
  94         .ops    = &followparent_clk_ops,
  95 };
  96
  97 /*
  98  * clock ratio of these clock will be updated
  99  * on r8a7791_clock_init()
 100  */
 101 SH_FIXED_RATIO_CLK_SET(pll1_clk,                main_clk,       1, 1);
 102 SH_FIXED_RATIO_CLK_SET(pll3_clk,                main_clk,       1, 1);
 103 SH_FIXED_RATIO_CLK_SET(qspi_clk,                pll1_clk,       1, 1);
 104
 105 /* fixed ratio clock */
 106 SH_FIXED_RATIO_CLK_SET(extal_div2_clk,          extal_clk,      1, 2);
 107 SH_FIXED_RATIO_CLK_SET(cp_clk,                  extal_clk,      1, 2);
 108
 109 SH_FIXED_RATIO_CLK_SET(pll1_div2_clk,           pll1_clk,       1, 2);
 110 SH_FIXED_RATIO_CLK_SET(hp_clk,                  pll1_clk,       1, 12);
 111 SH_FIXED_RATIO_CLK_SET(p_clk,                   pll1_clk,       1, 24);
 112 SH_FIXED_RATIO_CLK_SET(rclk_clk,                pll1_clk,       1, (48 * 1024));
 113 SH_FIXED_RATIO_CLK_SET(mp_clk,                  pll1_div2_clk,  1, 15);
 114 SH_FIXED_RATIO_CLK_SET(zg_clk,                  pll1_clk,       1, 3);
 115 SH_FIXED_RATIO_CLK_SET(zx_clk,                  pll1_clk,       1, 3);
 116 SH_FIXED_RATIO_CLK_SET(zs_clk,                  pll1_clk,       1, 6);
 117
 118 static struct clk *main_clks[] = {
 119         &extal_clk,
 120         &extal_div2_clk,
 121         &main_clk,
 122         &pll1_clk,
 123         &pll1_div2_clk,
 124         &pll3_clk,
 125         &hp_clk,
 126         &p_clk,
 127         &qspi_clk,
 128         &rclk_clk,
 129         &mp_clk,
 130         &cp_clk,
 131         &zg_clk,
 132         &zx_clk,
 133         &zs_clk,
 134 };
 135
 136 /* SDHI (DIV4) clock */
 137 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
 138
 139 static struct clk_div_mult_table div4_div_mult_table = {
 140         .divisors = divisors,
 141         .nr_divisors = ARRAY_SIZE(divisors),
 142 };
 143
 144 static struct clk_div4_table div4_table = {
 145         .div_mult_table = &div4_div_mult_table,
 146 };
 147
 148 enum {
 149         DIV4_SDH, DIV4_SD0,
 150         DIV4_NR
 151 };
 152
 153 static struct clk div4_clks[DIV4_NR] = {
 154         [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
 155         [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
 156 };
 157
 158 /* DIV6 clocks */
 159 enum {
 160         DIV6_SD1, DIV6_SD2,
 161         DIV6_NR
 162 };
 163
 164 static struct clk div6_clks[DIV6_NR] = {
 165         [DIV6_SD1]      = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
 166         [DIV6_SD2]      = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
 167 };
 168
 169 /* MSTP */
 170 enum {
 171         MSTP1108, MSTP1107, MSTP1106,
 172         MSTP931, MSTP930, MSTP929, MSTP928, MSTP927, MSTP925,
 173         MSTP917,
 174         MSTP815, MSTP814,
 175         MSTP813,
 176         MSTP811, MSTP810, MSTP809,
 177         MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
 178         MSTP719, MSTP718, MSTP715, MSTP714,
 179         MSTP522,
 180         MSTP314, MSTP312, MSTP311,
 181         MSTP216, MSTP207, MSTP206,
 182         MSTP204, MSTP203, MSTP202,
 183         MSTP124,
 184         MSTP_NR
 185 };
 186
 187 static struct clk mstp_clks[MSTP_NR] = {
 188         [MSTP1108] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 8, MSTPSR11, 0), /* SCIFA5 */
 189         [MSTP1107] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 7, MSTPSR11, 0), /* SCIFA4 */
 190         [MSTP1106] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 6, MSTPSR11, 0), /* SCIFA3 */
 191         [MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
 192         [MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
 193         [MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
 194         [MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
 195         [MSTP927] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */
 196         [MSTP925] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */
 197         [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
 198         [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
 199         [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
 200         [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
 201         [MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
 202         [MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
 203         [MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 9, MSTPSR8, 0), /* VIN2 */
 204         [MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
 205         [MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
 206         [MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
 207         [MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
 208         [MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
 209         [MSTP719] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 19, MSTPSR7, 0), /* SCIF2 */
 210         [MSTP718] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 18, MSTPSR7, 0), /* SCIF3 */
 211         [MSTP715] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 15, MSTPSR7, 0), /* SCIF4 */
 212         [MSTP714] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 14, MSTPSR7, 0), /* SCIF5 */
 213         [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
 214         [MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
 215         [MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD1], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI1 */
 216         [MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI2 */
 217         [MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
 218         [MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
 219         [MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
 220         [MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
 221         [MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
 222         [MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
 223         [MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
 224 };
 225
 226 static struct clk_lookup lookups[] = {
 227
 228         /* main clocks */
 229         CLKDEV_CON_ID("extal",          &extal_clk),
 230         CLKDEV_CON_ID("extal_div2",     &extal_div2_clk),
 231         CLKDEV_CON_ID("main",           &main_clk),
 232         CLKDEV_CON_ID("pll1",           &pll1_clk),
 233         CLKDEV_CON_ID("pll1_div2",      &pll1_div2_clk),
 234         CLKDEV_CON_ID("pll3",           &pll3_clk),
 235         CLKDEV_CON_ID("zg",             &zg_clk),
 236         CLKDEV_CON_ID("zs",             &zs_clk),
 237         CLKDEV_CON_ID("hp",             &hp_clk),
 238         CLKDEV_CON_ID("p",              &p_clk),
 239         CLKDEV_CON_ID("qspi",           &qspi_clk),
 240         CLKDEV_CON_ID("rclk",           &rclk_clk),
 241         CLKDEV_CON_ID("mp",             &mp_clk),
 242         CLKDEV_CON_ID("cp",             &cp_clk),
 243         CLKDEV_CON_ID("peripheral_clk", &hp_clk),
 244
 245         /* MSTP */
 246         CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7791", &mstp_clks[MSTP726]),
 247         CLKDEV_ICK_ID("du.0", "rcar-du-r8a7791", &mstp_clks[MSTP724]),
 248         CLKDEV_ICK_ID("du.1", "rcar-du-r8a7791", &mstp_clks[MSTP723]),
 249         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
 250         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
 251         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */
 252         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), /* SCIFB1 */
 253         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), /* SCIFB2 */
 254         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), /* SCIFA2 */
 255         CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), /* SCIF0 */
 256         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), /* SCIF1 */
 257         CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP719]), /* SCIF2 */
 258         CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP718]), /* SCIF3 */
 259         CLKDEV_DEV_ID("sh-sci.10", &mstp_clks[MSTP715]), /* SCIF4 */
 260         CLKDEV_DEV_ID("sh-sci.11", &mstp_clks[MSTP714]), /* SCIF5 */
 261         CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1106]), /* SCIFA3 */
 262         CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1107]), /* SCIFA4 */
 263         CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1108]), /* SCIFA5 */
 264         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
 265         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP312]),
 266         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]),
 267         CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.0", &mstp_clks[MSTP124]),
 268         CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
 269         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
 270         CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
 271         CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
 272         CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
 273         CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
 274         CLKDEV_DEV_ID("i2c-rcar_gen2.4", &mstp_clks[MSTP927]),
 275         CLKDEV_DEV_ID("i2c-rcar_gen2.5", &mstp_clks[MSTP925]),
 276         CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */
 277         CLKDEV_DEV_ID("r8a7791-vin.0", &mstp_clks[MSTP811]),
 278         CLKDEV_DEV_ID("r8a7791-vin.1", &mstp_clks[MSTP810]),
 279         CLKDEV_DEV_ID("r8a7791-vin.2", &mstp_clks[MSTP809]),
 280         CLKDEV_DEV_ID("sata-r8a7791.0", &mstp_clks[MSTP815]),
 281         CLKDEV_DEV_ID("sata-r8a7791.1", &mstp_clks[MSTP814]),
 282 };
 283
 284 #define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31)              \
 285         extal_clk.rate  = e * 1000 * 1000;                      \
 286         main_clk.parent = m;                                    \
 287         SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1);           \
 288         if (mode & MD(19))                                      \
 289                 SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1);      \
 290         else                                                    \
 291                 SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
 292
 293
 294 void __init r8a7791_clock_init(void)
 295 {
 296         u32 mode = rcar_gen2_read_mode_pins();
 297         int k, ret = 0;
 298
 299         switch (mode & (MD(14) | MD(13))) {
 300         case 0:
 301                 R8A7791_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
 302                 break;
 303         case MD(13):
 304                 R8A7791_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
 305                 break;
 306         case MD(14):
 307                 R8A7791_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
 308                 break;
 309         case MD(13) | MD(14):
 310                 R8A7791_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
 311                 break;
 312         }
 313
 314         if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
 315                 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
 316         else
 317                 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
 318
 319         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 320                 ret = clk_register(main_clks[k]);
 321
 322         if (!ret)
 323                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 324
 325         if (!ret)
 326                 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 327
 328         if (!ret)
 329                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 330
 331         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 332
 333         if (!ret)
 334                 shmobile_clk_init();
 335         else
 336                 goto epanic;
 337
 338         return;
 339
 340 epanic:
 341         panic("failed to setup r8a7791 clocks\n");
 342 }