2 * sh73a0 processor support
4 * Copyright (C) 2010 Takashi Yoshii
5 * Copyright (C) 2010 Magnus Damm
6 * Copyright (C) 2008 Yoshihiro Shimoda
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/platform_device.h>
26 #include <linux/of_platform.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_intc.h>
33 #include <linux/sh_timer.h>
34 #include <linux/platform_data/sh_ipmmu.h>
35 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
36 #include <mach/dma-register.h>
37 #include <mach/irqs.h>
38 #include <mach/sh73a0.h>
39 #include <mach/common.h>
40 #include <asm/mach-types.h>
41 #include <asm/mach/map.h>
42 #include <asm/mach/arch.h>
43 #include <asm/mach/time.h>
45 static struct map_desc sh73a0_io_desc
[] __initdata
= {
46 /* create a 1:1 entity map for 0xe6xxxxxx
47 * used by CPGA, INTC and PFC.
50 .virtual = 0xe6000000,
51 .pfn
= __phys_to_pfn(0xe6000000),
53 .type
= MT_DEVICE_NONSHARED
57 void __init
sh73a0_map_io(void)
59 iotable_init(sh73a0_io_desc
, ARRAY_SIZE(sh73a0_io_desc
));
63 static struct resource pfc_resources
[] __initdata
= {
64 DEFINE_RES_MEM(0xe6050000, 0x8000),
65 DEFINE_RES_MEM(0xe605801c, 0x000c),
68 void __init
sh73a0_pinmux_init(void)
70 platform_device_register_simple("pfc-sh73a0", -1, pfc_resources
,
71 ARRAY_SIZE(pfc_resources
));
75 #define SH73A0_SCIF(scif_type, index, baseaddr, irq) \
76 static struct plat_sci_port scif##index##_platform_data = { \
78 .flags = UPF_BOOT_AUTOCONF, \
79 .scscr = SCSCR_RE | SCSCR_TE, \
82 static struct resource scif##index##_resources[] = { \
83 DEFINE_RES_MEM(baseaddr, 0x100), \
84 DEFINE_RES_IRQ(irq), \
87 static struct platform_device scif##index##_device = { \
90 .resource = scif##index##_resources, \
91 .num_resources = ARRAY_SIZE(scif##index##_resources), \
93 .platform_data = &scif##index##_platform_data, \
97 SH73A0_SCIF(PORT_SCIFA
, 0, 0xe6c40000, gic_spi(72));
98 SH73A0_SCIF(PORT_SCIFA
, 1, 0xe6c50000, gic_spi(73));
99 SH73A0_SCIF(PORT_SCIFA
, 2, 0xe6c60000, gic_spi(74));
100 SH73A0_SCIF(PORT_SCIFA
, 3, 0xe6c70000, gic_spi(75));
101 SH73A0_SCIF(PORT_SCIFA
, 4, 0xe6c80000, gic_spi(78));
102 SH73A0_SCIF(PORT_SCIFA
, 5, 0xe6cb0000, gic_spi(79));
103 SH73A0_SCIF(PORT_SCIFA
, 6, 0xe6cc0000, gic_spi(156));
104 SH73A0_SCIF(PORT_SCIFA
, 7, 0xe6cd0000, gic_spi(143));
105 SH73A0_SCIF(PORT_SCIFB
, 8, 0xe6c30000, gic_spi(80));
107 static struct sh_timer_config cmt1_platform_data
= {
108 .channels_mask
= 0x3f,
111 static struct resource cmt1_resources
[] = {
112 DEFINE_RES_MEM(0xe6138000, 0x200),
113 DEFINE_RES_IRQ(gic_spi(65)),
116 static struct platform_device cmt1_device
= {
120 .platform_data
= &cmt1_platform_data
,
122 .resource
= cmt1_resources
,
123 .num_resources
= ARRAY_SIZE(cmt1_resources
),
127 static struct sh_timer_config tmu0_platform_data
= {
131 static struct resource tmu0_resources
[] = {
132 DEFINE_RES_MEM(0xfff60000, 0x2c),
133 DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
134 DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
135 DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
138 static struct platform_device tmu0_device
= {
142 .platform_data
= &tmu0_platform_data
,
144 .resource
= tmu0_resources
,
145 .num_resources
= ARRAY_SIZE(tmu0_resources
),
148 static struct resource i2c0_resources
[] = {
149 [0] = DEFINE_RES_MEM(0xe6820000, 0x426),
151 .start
= gic_spi(167),
153 .flags
= IORESOURCE_IRQ
,
157 static struct resource i2c1_resources
[] = {
158 [0] = DEFINE_RES_MEM(0xe6822000, 0x426),
160 .start
= gic_spi(51),
162 .flags
= IORESOURCE_IRQ
,
166 static struct resource i2c2_resources
[] = {
167 [0] = DEFINE_RES_MEM(0xe6824000, 0x426),
169 .start
= gic_spi(171),
171 .flags
= IORESOURCE_IRQ
,
175 static struct resource i2c3_resources
[] = {
176 [0] = DEFINE_RES_MEM(0xe6826000, 0x426),
178 .start
= gic_spi(183),
180 .flags
= IORESOURCE_IRQ
,
184 static struct resource i2c4_resources
[] = {
185 [0] = DEFINE_RES_MEM(0xe6828000, 0x426),
187 .start
= gic_spi(187),
189 .flags
= IORESOURCE_IRQ
,
193 static struct platform_device i2c0_device
= {
194 .name
= "i2c-sh_mobile",
196 .resource
= i2c0_resources
,
197 .num_resources
= ARRAY_SIZE(i2c0_resources
),
200 static struct platform_device i2c1_device
= {
201 .name
= "i2c-sh_mobile",
203 .resource
= i2c1_resources
,
204 .num_resources
= ARRAY_SIZE(i2c1_resources
),
207 static struct platform_device i2c2_device
= {
208 .name
= "i2c-sh_mobile",
210 .resource
= i2c2_resources
,
211 .num_resources
= ARRAY_SIZE(i2c2_resources
),
214 static struct platform_device i2c3_device
= {
215 .name
= "i2c-sh_mobile",
217 .resource
= i2c3_resources
,
218 .num_resources
= ARRAY_SIZE(i2c3_resources
),
221 static struct platform_device i2c4_device
= {
222 .name
= "i2c-sh_mobile",
224 .resource
= i2c4_resources
,
225 .num_resources
= ARRAY_SIZE(i2c4_resources
),
228 static const struct sh_dmae_slave_config sh73a0_dmae_slaves
[] = {
230 .slave_id
= SHDMA_SLAVE_SCIF0_TX
,
232 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
235 .slave_id
= SHDMA_SLAVE_SCIF0_RX
,
237 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
240 .slave_id
= SHDMA_SLAVE_SCIF1_TX
,
242 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
245 .slave_id
= SHDMA_SLAVE_SCIF1_RX
,
247 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
250 .slave_id
= SHDMA_SLAVE_SCIF2_TX
,
252 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
255 .slave_id
= SHDMA_SLAVE_SCIF2_RX
,
257 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
260 .slave_id
= SHDMA_SLAVE_SCIF3_TX
,
262 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
265 .slave_id
= SHDMA_SLAVE_SCIF3_RX
,
267 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
270 .slave_id
= SHDMA_SLAVE_SCIF4_TX
,
272 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
275 .slave_id
= SHDMA_SLAVE_SCIF4_RX
,
277 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
280 .slave_id
= SHDMA_SLAVE_SCIF5_TX
,
282 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
285 .slave_id
= SHDMA_SLAVE_SCIF5_RX
,
287 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
290 .slave_id
= SHDMA_SLAVE_SCIF6_TX
,
292 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
295 .slave_id
= SHDMA_SLAVE_SCIF6_RX
,
297 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
300 .slave_id
= SHDMA_SLAVE_SCIF7_TX
,
302 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
305 .slave_id
= SHDMA_SLAVE_SCIF7_RX
,
307 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
310 .slave_id
= SHDMA_SLAVE_SCIF8_TX
,
312 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
315 .slave_id
= SHDMA_SLAVE_SCIF8_RX
,
317 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
320 .slave_id
= SHDMA_SLAVE_SDHI0_TX
,
322 .chcr
= CHCR_TX(XMIT_SZ_16BIT
),
325 .slave_id
= SHDMA_SLAVE_SDHI0_RX
,
327 .chcr
= CHCR_RX(XMIT_SZ_16BIT
),
330 .slave_id
= SHDMA_SLAVE_SDHI1_TX
,
332 .chcr
= CHCR_TX(XMIT_SZ_16BIT
),
335 .slave_id
= SHDMA_SLAVE_SDHI1_RX
,
337 .chcr
= CHCR_RX(XMIT_SZ_16BIT
),
340 .slave_id
= SHDMA_SLAVE_SDHI2_TX
,
342 .chcr
= CHCR_TX(XMIT_SZ_16BIT
),
345 .slave_id
= SHDMA_SLAVE_SDHI2_RX
,
347 .chcr
= CHCR_RX(XMIT_SZ_16BIT
),
350 .slave_id
= SHDMA_SLAVE_MMCIF_TX
,
352 .chcr
= CHCR_TX(XMIT_SZ_32BIT
),
355 .slave_id
= SHDMA_SLAVE_MMCIF_RX
,
357 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
362 #define DMAE_CHANNEL(_offset) \
364 .offset = _offset - 0x20, \
365 .dmars = _offset - 0x20 + 0x40, \
368 static const struct sh_dmae_channel sh73a0_dmae_channels
[] = {
369 DMAE_CHANNEL(0x8000),
370 DMAE_CHANNEL(0x8080),
371 DMAE_CHANNEL(0x8100),
372 DMAE_CHANNEL(0x8180),
373 DMAE_CHANNEL(0x8200),
374 DMAE_CHANNEL(0x8280),
375 DMAE_CHANNEL(0x8300),
376 DMAE_CHANNEL(0x8380),
377 DMAE_CHANNEL(0x8400),
378 DMAE_CHANNEL(0x8480),
379 DMAE_CHANNEL(0x8500),
380 DMAE_CHANNEL(0x8580),
381 DMAE_CHANNEL(0x8600),
382 DMAE_CHANNEL(0x8680),
383 DMAE_CHANNEL(0x8700),
384 DMAE_CHANNEL(0x8780),
385 DMAE_CHANNEL(0x8800),
386 DMAE_CHANNEL(0x8880),
387 DMAE_CHANNEL(0x8900),
388 DMAE_CHANNEL(0x8980),
391 static struct sh_dmae_pdata sh73a0_dmae_platform_data
= {
392 .slave
= sh73a0_dmae_slaves
,
393 .slave_num
= ARRAY_SIZE(sh73a0_dmae_slaves
),
394 .channel
= sh73a0_dmae_channels
,
395 .channel_num
= ARRAY_SIZE(sh73a0_dmae_channels
),
396 .ts_low_shift
= TS_LOW_SHIFT
,
397 .ts_low_mask
= TS_LOW_BIT
<< TS_LOW_SHIFT
,
398 .ts_high_shift
= TS_HI_SHIFT
,
399 .ts_high_mask
= TS_HI_BIT
<< TS_HI_SHIFT
,
400 .ts_shift
= dma_ts_shift
,
401 .ts_shift_num
= ARRAY_SIZE(dma_ts_shift
),
402 .dmaor_init
= DMAOR_DME
,
405 static struct resource sh73a0_dmae_resources
[] = {
406 DEFINE_RES_MEM(0xfe000020, 0x89e0),
409 .start
= gic_spi(129),
411 .flags
= IORESOURCE_IRQ
,
414 /* IRQ for channels 0-19 */
415 .start
= gic_spi(109),
417 .flags
= IORESOURCE_IRQ
,
421 static struct platform_device dma0_device
= {
422 .name
= "sh-dma-engine",
424 .resource
= sh73a0_dmae_resources
,
425 .num_resources
= ARRAY_SIZE(sh73a0_dmae_resources
),
427 .platform_data
= &sh73a0_dmae_platform_data
,
432 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves
[] = {
434 .slave_id
= SHDMA_SLAVE_FSI2A_RX
,
436 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
437 .mid_rid
= 0xd6, /* CHECK ME */
439 .slave_id
= SHDMA_SLAVE_FSI2A_TX
,
441 .chcr
= CHCR_TX(XMIT_SZ_32BIT
),
442 .mid_rid
= 0xd5, /* CHECK ME */
444 .slave_id
= SHDMA_SLAVE_FSI2C_RX
,
446 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
447 .mid_rid
= 0xda, /* CHECK ME */
449 .slave_id
= SHDMA_SLAVE_FSI2C_TX
,
451 .chcr
= CHCR_TX(XMIT_SZ_32BIT
),
452 .mid_rid
= 0xd9, /* CHECK ME */
454 .slave_id
= SHDMA_SLAVE_FSI2B_RX
,
456 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
457 .mid_rid
= 0x8e, /* CHECK ME */
459 .slave_id
= SHDMA_SLAVE_FSI2B_TX
,
461 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
462 .mid_rid
= 0x8d, /* CHECK ME */
464 .slave_id
= SHDMA_SLAVE_FSI2D_RX
,
466 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
467 .mid_rid
= 0x9a, /* CHECK ME */
471 #define MPDMA_CHANNEL(a, b, c) \
476 .chclr_offset = (0x220 - 0x20) + a \
479 static const struct sh_dmae_channel sh73a0_mpdma_channels
[] = {
480 MPDMA_CHANNEL(0x00, 0, 0),
481 MPDMA_CHANNEL(0x10, 0, 8),
482 MPDMA_CHANNEL(0x20, 4, 0),
483 MPDMA_CHANNEL(0x30, 4, 8),
484 MPDMA_CHANNEL(0x50, 8, 0),
485 MPDMA_CHANNEL(0x70, 8, 8),
488 static struct sh_dmae_pdata sh73a0_mpdma_platform_data
= {
489 .slave
= sh73a0_mpdma_slaves
,
490 .slave_num
= ARRAY_SIZE(sh73a0_mpdma_slaves
),
491 .channel
= sh73a0_mpdma_channels
,
492 .channel_num
= ARRAY_SIZE(sh73a0_mpdma_channels
),
493 .ts_low_shift
= TS_LOW_SHIFT
,
494 .ts_low_mask
= TS_LOW_BIT
<< TS_LOW_SHIFT
,
495 .ts_high_shift
= TS_HI_SHIFT
,
496 .ts_high_mask
= TS_HI_BIT
<< TS_HI_SHIFT
,
497 .ts_shift
= dma_ts_shift
,
498 .ts_shift_num
= ARRAY_SIZE(dma_ts_shift
),
499 .dmaor_init
= DMAOR_DME
,
503 /* Resource order important! */
504 static struct resource sh73a0_mpdma_resources
[] = {
505 /* Channel registers and DMAOR */
506 DEFINE_RES_MEM(0xec618020, 0x270),
508 DEFINE_RES_MEM(0xec619000, 0xc),
511 .start
= gic_spi(181),
513 .flags
= IORESOURCE_IRQ
,
516 /* IRQ for channels 0-5 */
517 .start
= gic_spi(175),
519 .flags
= IORESOURCE_IRQ
,
523 static struct platform_device mpdma0_device
= {
524 .name
= "sh-dma-engine",
526 .resource
= sh73a0_mpdma_resources
,
527 .num_resources
= ARRAY_SIZE(sh73a0_mpdma_resources
),
529 .platform_data
= &sh73a0_mpdma_platform_data
,
533 static struct resource pmu_resources
[] = {
535 .start
= gic_spi(55),
537 .flags
= IORESOURCE_IRQ
,
540 .start
= gic_spi(56),
542 .flags
= IORESOURCE_IRQ
,
546 static struct platform_device pmu_device
= {
549 .num_resources
= ARRAY_SIZE(pmu_resources
),
550 .resource
= pmu_resources
,
553 /* an IPMMU module for ICB */
554 static struct resource ipmmu_resources
[] = {
555 DEFINE_RES_MEM(0xfe951000, 0x100),
558 static const char * const ipmmu_dev_names
[] = {
559 "sh_mobile_lcdc_fb.0",
562 static struct shmobile_ipmmu_platform_data ipmmu_platform_data
= {
563 .dev_names
= ipmmu_dev_names
,
564 .num_dev_names
= ARRAY_SIZE(ipmmu_dev_names
),
567 static struct platform_device ipmmu_device
= {
571 .platform_data
= &ipmmu_platform_data
,
573 .resource
= ipmmu_resources
,
574 .num_resources
= ARRAY_SIZE(ipmmu_resources
),
577 static struct renesas_intc_irqpin_config irqpin0_platform_data
= {
578 .irq_base
= irq_pin(0), /* IRQ0 -> IRQ7 */
581 static struct resource irqpin0_resources
[] = {
582 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
583 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
584 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
585 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
586 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
587 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
588 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
589 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
590 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
591 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
592 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
593 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
594 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
597 static struct platform_device irqpin0_device
= {
598 .name
= "renesas_intc_irqpin",
600 .resource
= irqpin0_resources
,
601 .num_resources
= ARRAY_SIZE(irqpin0_resources
),
603 .platform_data
= &irqpin0_platform_data
,
607 static struct renesas_intc_irqpin_config irqpin1_platform_data
= {
608 .irq_base
= irq_pin(8), /* IRQ8 -> IRQ15 */
609 .control_parent
= true, /* Disable spurious IRQ10 */
612 static struct resource irqpin1_resources
[] = {
613 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
614 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
615 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
616 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
617 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
618 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
619 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
620 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
621 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
622 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
623 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
624 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
625 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
628 static struct platform_device irqpin1_device
= {
629 .name
= "renesas_intc_irqpin",
631 .resource
= irqpin1_resources
,
632 .num_resources
= ARRAY_SIZE(irqpin1_resources
),
634 .platform_data
= &irqpin1_platform_data
,
638 static struct renesas_intc_irqpin_config irqpin2_platform_data
= {
639 .irq_base
= irq_pin(16), /* IRQ16 -> IRQ23 */
642 static struct resource irqpin2_resources
[] = {
643 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
644 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
645 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
646 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
647 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
648 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
649 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
650 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
651 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
652 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
653 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
654 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
655 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
658 static struct platform_device irqpin2_device
= {
659 .name
= "renesas_intc_irqpin",
661 .resource
= irqpin2_resources
,
662 .num_resources
= ARRAY_SIZE(irqpin2_resources
),
664 .platform_data
= &irqpin2_platform_data
,
668 static struct renesas_intc_irqpin_config irqpin3_platform_data
= {
669 .irq_base
= irq_pin(24), /* IRQ24 -> IRQ31 */
672 static struct resource irqpin3_resources
[] = {
673 DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
674 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
675 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
676 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
677 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
678 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
679 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
680 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
681 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
682 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
683 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
684 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
685 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
688 static struct platform_device irqpin3_device
= {
689 .name
= "renesas_intc_irqpin",
691 .resource
= irqpin3_resources
,
692 .num_resources
= ARRAY_SIZE(irqpin3_resources
),
694 .platform_data
= &irqpin3_platform_data
,
698 static struct platform_device
*sh73a0_devices_dt
[] __initdata
= {
711 static struct platform_device
*sh73a0_early_devices
[] __initdata
= {
716 static struct platform_device
*sh73a0_late_devices
[] __initdata
= {
731 #define SRCR2 IOMEM(0xe61580b0)
733 void __init
sh73a0_add_standard_devices(void)
735 /* Clear software reset bit on SY-DMAC module */
736 __raw_writel(__raw_readl(SRCR2
) & ~(1 << 18), SRCR2
);
738 platform_add_devices(sh73a0_devices_dt
,
739 ARRAY_SIZE(sh73a0_devices_dt
));
740 platform_add_devices(sh73a0_early_devices
,
741 ARRAY_SIZE(sh73a0_early_devices
));
742 platform_add_devices(sh73a0_late_devices
,
743 ARRAY_SIZE(sh73a0_late_devices
));
746 void __init
sh73a0_init_delay(void)
748 shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
751 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
752 void __init __weak
sh73a0_register_twd(void) { }
754 void __init
sh73a0_earlytimer_init(void)
758 shmobile_earlytimer_init();
759 sh73a0_register_twd();
762 void __init
sh73a0_add_early_devices(void)
764 early_platform_add_devices(sh73a0_devices_dt
,
765 ARRAY_SIZE(sh73a0_devices_dt
));
766 early_platform_add_devices(sh73a0_early_devices
,
767 ARRAY_SIZE(sh73a0_early_devices
));
769 /* setup early console here as well */
770 shmobile_setup_console();
775 void __init
sh73a0_add_standard_devices_dt(void)
777 struct platform_device_info devinfo
= { .name
= "cpufreq-cpu0", .id
= -1, };
779 /* clocks are setup late during boot in the case of DT */
782 platform_add_devices(sh73a0_devices_dt
,
783 ARRAY_SIZE(sh73a0_devices_dt
));
784 of_platform_populate(NULL
, of_default_bus_match_table
, NULL
, NULL
);
786 /* Instantiate cpufreq-cpu0 */
787 platform_device_register_full(&devinfo
);
790 static const char *sh73a0_boards_compat_dt
[] __initdata
= {
795 DT_MACHINE_START(SH73A0_DT
, "Generic SH73A0 (Flattened Device Tree)")
796 .smp
= smp_ops(sh73a0_smp_ops
),
797 .map_io
= sh73a0_map_io
,
798 .init_early
= sh73a0_init_delay
,
799 .nr_irqs
= NR_IRQS_LEGACY
,
800 .init_machine
= sh73a0_add_standard_devices_dt
,
801 .dt_compat
= sh73a0_boards_compat_dt
,
803 #endif /* CONFIG_USE_OF */