Merge tag 'locks-v3.16-2' of git://git.samba.org/jlayton/linux
[linux/fpc-iii.git] / arch / arm / mach-tegra / powergate.c
blob4cefc5cd6bedcc50ddc345c857270fda1ad17d49
1 /*
2 * drivers/powergate/tegra-powergate.c
4 * Copyright (c) 2010 Google, Inc
6 * Author:
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/clk.h>
22 #include <linux/debugfs.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/export.h>
26 #include <linux/init.h>
27 #include <linux/io.h>
28 #include <linux/reset.h>
29 #include <linux/seq_file.h>
30 #include <linux/spinlock.h>
31 #include <linux/clk/tegra.h>
32 #include <linux/tegra-powergate.h>
34 #include "fuse.h"
35 #include "iomap.h"
37 #define DPD_SAMPLE 0x020
38 #define DPD_SAMPLE_ENABLE (1 << 0)
39 #define DPD_SAMPLE_DISABLE (0 << 0)
41 #define PWRGATE_TOGGLE 0x30
42 #define PWRGATE_TOGGLE_START (1 << 8)
44 #define REMOVE_CLAMPING 0x34
46 #define PWRGATE_STATUS 0x38
48 #define IO_DPD_REQ 0x1b8
49 #define IO_DPD_REQ_CODE_IDLE (0 << 30)
50 #define IO_DPD_REQ_CODE_OFF (1 << 30)
51 #define IO_DPD_REQ_CODE_ON (2 << 30)
52 #define IO_DPD_REQ_CODE_MASK (3 << 30)
54 #define IO_DPD_STATUS 0x1bc
55 #define IO_DPD2_REQ 0x1c0
56 #define IO_DPD2_STATUS 0x1c4
57 #define SEL_DPD_TIM 0x1c8
59 #define GPU_RG_CNTRL 0x2d4
61 static int tegra_num_powerdomains;
62 static int tegra_num_cpu_domains;
63 static const u8 *tegra_cpu_domains;
65 static const u8 tegra30_cpu_domains[] = {
66 TEGRA_POWERGATE_CPU,
67 TEGRA_POWERGATE_CPU1,
68 TEGRA_POWERGATE_CPU2,
69 TEGRA_POWERGATE_CPU3,
72 static const u8 tegra114_cpu_domains[] = {
73 TEGRA_POWERGATE_CPU0,
74 TEGRA_POWERGATE_CPU1,
75 TEGRA_POWERGATE_CPU2,
76 TEGRA_POWERGATE_CPU3,
79 static const u8 tegra124_cpu_domains[] = {
80 TEGRA_POWERGATE_CPU0,
81 TEGRA_POWERGATE_CPU1,
82 TEGRA_POWERGATE_CPU2,
83 TEGRA_POWERGATE_CPU3,
86 static DEFINE_SPINLOCK(tegra_powergate_lock);
88 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
90 static u32 pmc_read(unsigned long reg)
92 return readl(pmc + reg);
95 static void pmc_write(u32 val, unsigned long reg)
97 writel(val, pmc + reg);
100 static int tegra_powergate_set(int id, bool new_state)
102 bool status;
103 unsigned long flags;
105 spin_lock_irqsave(&tegra_powergate_lock, flags);
107 status = pmc_read(PWRGATE_STATUS) & (1 << id);
109 if (status == new_state) {
110 spin_unlock_irqrestore(&tegra_powergate_lock, flags);
111 return 0;
114 pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
116 spin_unlock_irqrestore(&tegra_powergate_lock, flags);
118 return 0;
121 int tegra_powergate_power_on(int id)
123 if (id < 0 || id >= tegra_num_powerdomains)
124 return -EINVAL;
126 return tegra_powergate_set(id, true);
129 int tegra_powergate_power_off(int id)
131 if (id < 0 || id >= tegra_num_powerdomains)
132 return -EINVAL;
134 return tegra_powergate_set(id, false);
136 EXPORT_SYMBOL(tegra_powergate_power_off);
138 int tegra_powergate_is_powered(int id)
140 u32 status;
142 if (id < 0 || id >= tegra_num_powerdomains)
143 return -EINVAL;
145 status = pmc_read(PWRGATE_STATUS) & (1 << id);
146 return !!status;
149 int tegra_powergate_remove_clamping(int id)
151 u32 mask;
153 if (id < 0 || id >= tegra_num_powerdomains)
154 return -EINVAL;
157 * The Tegra124 GPU has a separate register (with different semantics)
158 * to remove clamps.
160 if (tegra_chip_id == TEGRA124) {
161 if (id == TEGRA_POWERGATE_3D) {
162 pmc_write(0, GPU_RG_CNTRL);
163 return 0;
168 * Tegra 2 has a bug where PCIE and VDE clamping masks are
169 * swapped relatively to the partition ids
171 if (id == TEGRA_POWERGATE_VDEC)
172 mask = (1 << TEGRA_POWERGATE_PCIE);
173 else if (id == TEGRA_POWERGATE_PCIE)
174 mask = (1 << TEGRA_POWERGATE_VDEC);
175 else
176 mask = (1 << id);
178 pmc_write(mask, REMOVE_CLAMPING);
180 return 0;
182 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
184 /* Must be called with clk disabled, and returns with clk enabled */
185 int tegra_powergate_sequence_power_up(int id, struct clk *clk,
186 struct reset_control *rst)
188 int ret;
190 reset_control_assert(rst);
192 ret = tegra_powergate_power_on(id);
193 if (ret)
194 goto err_power;
196 ret = clk_prepare_enable(clk);
197 if (ret)
198 goto err_clk;
200 udelay(10);
202 ret = tegra_powergate_remove_clamping(id);
203 if (ret)
204 goto err_clamp;
206 udelay(10);
207 reset_control_deassert(rst);
209 return 0;
211 err_clamp:
212 clk_disable_unprepare(clk);
213 err_clk:
214 tegra_powergate_power_off(id);
215 err_power:
216 return ret;
218 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
220 int tegra_cpu_powergate_id(int cpuid)
222 if (cpuid > 0 && cpuid < tegra_num_cpu_domains)
223 return tegra_cpu_domains[cpuid];
225 return -EINVAL;
228 int __init tegra_powergate_init(void)
230 switch (tegra_chip_id) {
231 case TEGRA20:
232 tegra_num_powerdomains = 7;
233 break;
234 case TEGRA30:
235 tegra_num_powerdomains = 14;
236 tegra_num_cpu_domains = 4;
237 tegra_cpu_domains = tegra30_cpu_domains;
238 break;
239 case TEGRA114:
240 tegra_num_powerdomains = 23;
241 tegra_num_cpu_domains = 4;
242 tegra_cpu_domains = tegra114_cpu_domains;
243 break;
244 case TEGRA124:
245 tegra_num_powerdomains = 25;
246 tegra_num_cpu_domains = 4;
247 tegra_cpu_domains = tegra124_cpu_domains;
248 break;
249 default:
250 /* Unknown Tegra variant. Disable powergating */
251 tegra_num_powerdomains = 0;
252 break;
255 return 0;
258 #ifdef CONFIG_DEBUG_FS
260 static const char * const *powergate_name;
262 static const char * const powergate_name_t20[] = {
263 [TEGRA_POWERGATE_CPU] = "cpu",
264 [TEGRA_POWERGATE_3D] = "3d",
265 [TEGRA_POWERGATE_VENC] = "venc",
266 [TEGRA_POWERGATE_VDEC] = "vdec",
267 [TEGRA_POWERGATE_PCIE] = "pcie",
268 [TEGRA_POWERGATE_L2] = "l2",
269 [TEGRA_POWERGATE_MPE] = "mpe",
272 static const char * const powergate_name_t30[] = {
273 [TEGRA_POWERGATE_CPU] = "cpu0",
274 [TEGRA_POWERGATE_3D] = "3d0",
275 [TEGRA_POWERGATE_VENC] = "venc",
276 [TEGRA_POWERGATE_VDEC] = "vdec",
277 [TEGRA_POWERGATE_PCIE] = "pcie",
278 [TEGRA_POWERGATE_L2] = "l2",
279 [TEGRA_POWERGATE_MPE] = "mpe",
280 [TEGRA_POWERGATE_HEG] = "heg",
281 [TEGRA_POWERGATE_SATA] = "sata",
282 [TEGRA_POWERGATE_CPU1] = "cpu1",
283 [TEGRA_POWERGATE_CPU2] = "cpu2",
284 [TEGRA_POWERGATE_CPU3] = "cpu3",
285 [TEGRA_POWERGATE_CELP] = "celp",
286 [TEGRA_POWERGATE_3D1] = "3d1",
289 static const char * const powergate_name_t114[] = {
290 [TEGRA_POWERGATE_CPU] = "crail",
291 [TEGRA_POWERGATE_3D] = "3d",
292 [TEGRA_POWERGATE_VENC] = "venc",
293 [TEGRA_POWERGATE_VDEC] = "vdec",
294 [TEGRA_POWERGATE_MPE] = "mpe",
295 [TEGRA_POWERGATE_HEG] = "heg",
296 [TEGRA_POWERGATE_CPU1] = "cpu1",
297 [TEGRA_POWERGATE_CPU2] = "cpu2",
298 [TEGRA_POWERGATE_CPU3] = "cpu3",
299 [TEGRA_POWERGATE_CELP] = "celp",
300 [TEGRA_POWERGATE_CPU0] = "cpu0",
301 [TEGRA_POWERGATE_C0NC] = "c0nc",
302 [TEGRA_POWERGATE_C1NC] = "c1nc",
303 [TEGRA_POWERGATE_DIS] = "dis",
304 [TEGRA_POWERGATE_DISB] = "disb",
305 [TEGRA_POWERGATE_XUSBA] = "xusba",
306 [TEGRA_POWERGATE_XUSBB] = "xusbb",
307 [TEGRA_POWERGATE_XUSBC] = "xusbc",
310 static const char * const powergate_name_t124[] = {
311 [TEGRA_POWERGATE_CPU] = "crail",
312 [TEGRA_POWERGATE_3D] = "3d",
313 [TEGRA_POWERGATE_VENC] = "venc",
314 [TEGRA_POWERGATE_PCIE] = "pcie",
315 [TEGRA_POWERGATE_VDEC] = "vdec",
316 [TEGRA_POWERGATE_L2] = "l2",
317 [TEGRA_POWERGATE_MPE] = "mpe",
318 [TEGRA_POWERGATE_HEG] = "heg",
319 [TEGRA_POWERGATE_SATA] = "sata",
320 [TEGRA_POWERGATE_CPU1] = "cpu1",
321 [TEGRA_POWERGATE_CPU2] = "cpu2",
322 [TEGRA_POWERGATE_CPU3] = "cpu3",
323 [TEGRA_POWERGATE_CELP] = "celp",
324 [TEGRA_POWERGATE_CPU0] = "cpu0",
325 [TEGRA_POWERGATE_C0NC] = "c0nc",
326 [TEGRA_POWERGATE_C1NC] = "c1nc",
327 [TEGRA_POWERGATE_SOR] = "sor",
328 [TEGRA_POWERGATE_DIS] = "dis",
329 [TEGRA_POWERGATE_DISB] = "disb",
330 [TEGRA_POWERGATE_XUSBA] = "xusba",
331 [TEGRA_POWERGATE_XUSBB] = "xusbb",
332 [TEGRA_POWERGATE_XUSBC] = "xusbc",
333 [TEGRA_POWERGATE_VIC] = "vic",
334 [TEGRA_POWERGATE_IRAM] = "iram",
337 static int powergate_show(struct seq_file *s, void *data)
339 int i;
341 seq_printf(s, " powergate powered\n");
342 seq_printf(s, "------------------\n");
344 for (i = 0; i < tegra_num_powerdomains; i++) {
345 if (!powergate_name[i])
346 continue;
348 seq_printf(s, " %9s %7s\n", powergate_name[i],
349 tegra_powergate_is_powered(i) ? "yes" : "no");
352 return 0;
355 static int powergate_open(struct inode *inode, struct file *file)
357 return single_open(file, powergate_show, inode->i_private);
360 static const struct file_operations powergate_fops = {
361 .open = powergate_open,
362 .read = seq_read,
363 .llseek = seq_lseek,
364 .release = single_release,
367 int __init tegra_powergate_debugfs_init(void)
369 struct dentry *d;
371 switch (tegra_chip_id) {
372 case TEGRA20:
373 powergate_name = powergate_name_t20;
374 break;
375 case TEGRA30:
376 powergate_name = powergate_name_t30;
377 break;
378 case TEGRA114:
379 powergate_name = powergate_name_t114;
380 break;
381 case TEGRA124:
382 powergate_name = powergate_name_t124;
383 break;
386 if (powergate_name) {
387 d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
388 &powergate_fops);
389 if (!d)
390 return -ENOMEM;
393 return 0;
396 #endif
398 static int tegra_io_rail_prepare(int id, unsigned long *request,
399 unsigned long *status, unsigned int *bit)
401 unsigned long rate, value;
402 struct clk *clk;
404 *bit = id % 32;
407 * There are two sets of 30 bits to select IO rails, but bits 30 and
408 * 31 are control bits rather than IO rail selection bits.
410 if (id > 63 || *bit == 30 || *bit == 31)
411 return -EINVAL;
413 if (id < 32) {
414 *status = IO_DPD_STATUS;
415 *request = IO_DPD_REQ;
416 } else {
417 *status = IO_DPD2_STATUS;
418 *request = IO_DPD2_REQ;
421 clk = clk_get_sys(NULL, "pclk");
422 if (IS_ERR(clk))
423 return PTR_ERR(clk);
425 rate = clk_get_rate(clk);
426 clk_put(clk);
428 pmc_write(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
430 /* must be at least 200 ns, in APB (PCLK) clock cycles */
431 value = DIV_ROUND_UP(1000000000, rate);
432 value = DIV_ROUND_UP(200, value);
433 pmc_write(value, SEL_DPD_TIM);
435 return 0;
438 static int tegra_io_rail_poll(unsigned long offset, unsigned long mask,
439 unsigned long val, unsigned long timeout)
441 unsigned long value;
443 timeout = jiffies + msecs_to_jiffies(timeout);
445 while (time_after(timeout, jiffies)) {
446 value = pmc_read(offset);
447 if ((value & mask) == val)
448 return 0;
450 usleep_range(250, 1000);
453 return -ETIMEDOUT;
456 static void tegra_io_rail_unprepare(void)
458 pmc_write(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
461 int tegra_io_rail_power_on(int id)
463 unsigned long request, status, value;
464 unsigned int bit, mask;
465 int err;
467 err = tegra_io_rail_prepare(id, &request, &status, &bit);
468 if (err < 0)
469 return err;
471 mask = 1 << bit;
473 value = pmc_read(request);
474 value |= mask;
475 value &= ~IO_DPD_REQ_CODE_MASK;
476 value |= IO_DPD_REQ_CODE_OFF;
477 pmc_write(value, request);
479 err = tegra_io_rail_poll(status, mask, 0, 250);
480 if (err < 0)
481 return err;
483 tegra_io_rail_unprepare();
485 return 0;
487 EXPORT_SYMBOL(tegra_io_rail_power_on);
489 int tegra_io_rail_power_off(int id)
491 unsigned long request, status, value;
492 unsigned int bit, mask;
493 int err;
495 err = tegra_io_rail_prepare(id, &request, &status, &bit);
496 if (err < 0)
497 return err;
499 mask = 1 << bit;
501 value = pmc_read(request);
502 value |= mask;
503 value &= ~IO_DPD_REQ_CODE_MASK;
504 value |= IO_DPD_REQ_CODE_ON;
505 pmc_write(value, request);
507 err = tegra_io_rail_poll(status, mask, mask, 250);
508 if (err < 0)
509 return err;
511 tegra_io_rail_unprepare();
513 return 0;
515 EXPORT_SYMBOL(tegra_io_rail_power_off);