arch/arm/mach-vexpress/ct-ca9x4.c

   1 /*
   2  * Versatile Express Core Tile Cortex A9x4 Support
   3  */
   4 #include <linux/init.h>
   5 #include <linux/gfp.h>
   6 #include <linux/device.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/amba/bus.h>
  10 #include <linux/amba/clcd.h>
  11 #include <linux/clkdev.h>
  12 #include <linux/vexpress.h>
  13 #include <linux/irqchip/arm-gic.h>
  14
  15 #include <asm/hardware/arm_timer.h>
  16 #include <asm/hardware/cache-l2x0.h>
  17 #include <asm/smp_scu.h>
  18 #include <asm/smp_twd.h>
  19
  20 #include <mach/ct-ca9x4.h>
  21
  22 #include <asm/hardware/timer-sp.h>
  23
  24 #include <asm/mach/map.h>
  25 #include <asm/mach/time.h>
  26
  27 #include "core.h"
  28
  29 #include <mach/motherboard.h>
  30 #include <mach/irqs.h>
  31
  32 #include <plat/clcd.h>
  33
  34 static struct map_desc ct_ca9x4_io_desc[] __initdata = {
  35         {
  36                 .virtual        = V2T_PERIPH,
  37                 .pfn            = __phys_to_pfn(CT_CA9X4_MPIC),
  38                 .length         = SZ_8K,
  39                 .type           = MT_DEVICE,
  40         },
  41 };
  42
  43 static void __init ct_ca9x4_map_io(void)
  44 {
  45         iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
  46 }
  47
  48 static void __init ca9x4_l2_init(void)
  49 {
  50 #ifdef CONFIG_CACHE_L2X0
  51         void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
  52
  53         if (l2x0_base) {
  54                 /* set RAM latencies to 1 cycle for this core tile. */
  55                 writel(0, l2x0_base + L310_TAG_LATENCY_CTRL);
  56                 writel(0, l2x0_base + L310_DATA_LATENCY_CTRL);
  57
  58                 l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
  59         } else {
  60                 pr_err("L2C: unable to map L2 cache controller\n");
  61         }
  62 #endif
  63 }
  64
  65 #ifdef CONFIG_HAVE_ARM_TWD
  66 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);
  67
  68 static void __init ca9x4_twd_init(void)
  69 {
  70         int err = twd_local_timer_register(&twd_local_timer);
  71         if (err)
  72                 pr_err("twd_local_timer_register failed %d\n", err);
  73 }
  74 #else
  75 #define ca9x4_twd_init()        do {} while(0)
  76 #endif
  77
  78 static void __init ct_ca9x4_init_irq(void)
  79 {
  80         gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
  81                  ioremap(A9_MPCORE_GIC_CPU, SZ_256));
  82         ca9x4_twd_init();
  83         ca9x4_l2_init();
  84 }
  85
  86 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
  87 {
  88         unsigned long framesize = 1024 * 768 * 2;
  89
  90         fb->panel = versatile_clcd_get_panel("XVGA");
  91         if (!fb->panel)
  92                 return -EINVAL;
  93
  94         return versatile_clcd_setup_dma(fb, framesize);
  95 }
  96
  97 static struct clcd_board ct_ca9x4_clcd_data = {
  98         .name           = "CT-CA9X4",
  99         .caps           = CLCD_CAP_5551 | CLCD_CAP_565,
 100         .check          = clcdfb_check,
 101         .decode         = clcdfb_decode,
 102         .setup          = ct_ca9x4_clcd_setup,
 103         .mmap           = versatile_clcd_mmap_dma,
 104         .remove         = versatile_clcd_remove_dma,
 105 };
 106
 107 static AMBA_AHB_DEVICE(clcd, "ct:clcd", 0, CT_CA9X4_CLCDC, IRQ_CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
 108 static AMBA_APB_DEVICE(dmc, "ct:dmc", 0, CT_CA9X4_DMC, IRQ_CT_CA9X4_DMC, NULL);
 109 static AMBA_APB_DEVICE(smc, "ct:smc", 0, CT_CA9X4_SMC, IRQ_CT_CA9X4_SMC, NULL);
 110 static AMBA_APB_DEVICE(gpio, "ct:gpio", 0, CT_CA9X4_GPIO, IRQ_CT_CA9X4_GPIO, NULL);
 111
 112 static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
 113         &clcd_device,
 114         &dmc_device,
 115         &smc_device,
 116         &gpio_device,
 117 };
 118
 119 static struct resource pmu_resources[] = {
 120         [0] = {
 121                 .start  = IRQ_CT_CA9X4_PMU_CPU0,
 122                 .end    = IRQ_CT_CA9X4_PMU_CPU0,
 123                 .flags  = IORESOURCE_IRQ,
 124         },
 125         [1] = {
 126                 .start  = IRQ_CT_CA9X4_PMU_CPU1,
 127                 .end    = IRQ_CT_CA9X4_PMU_CPU1,
 128                 .flags  = IORESOURCE_IRQ,
 129         },
 130         [2] = {
 131                 .start  = IRQ_CT_CA9X4_PMU_CPU2,
 132                 .end    = IRQ_CT_CA9X4_PMU_CPU2,
 133                 .flags  = IORESOURCE_IRQ,
 134         },
 135         [3] = {
 136                 .start  = IRQ_CT_CA9X4_PMU_CPU3,
 137                 .end    = IRQ_CT_CA9X4_PMU_CPU3,
 138                 .flags  = IORESOURCE_IRQ,
 139         },
 140 };
 141
 142 static struct platform_device pmu_device = {
 143         .name           = "arm-pmu",
 144         .id             = -1,
 145         .num_resources  = ARRAY_SIZE(pmu_resources),
 146         .resource       = pmu_resources,
 147 };
 148
 149 static struct clk_lookup osc1_lookup = {
 150         .dev_id         = "ct:clcd",
 151 };
 152
 153 static struct platform_device osc1_device = {
 154         .name           = "vexpress-osc",
 155         .id             = 1,
 156         .num_resources  = 1,
 157         .resource       = (struct resource []) {
 158                 VEXPRESS_RES_FUNC(0xf, 1),
 159         },
 160         .dev.platform_data = &osc1_lookup,
 161 };
 162
 163 static void __init ct_ca9x4_init(void)
 164 {
 165         int i;
 166
 167         for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
 168                 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
 169
 170         platform_device_register(&pmu_device);
 171         vexpress_syscfg_device_register(&osc1_device);
 172 }
 173
 174 #ifdef CONFIG_SMP
 175 static void *ct_ca9x4_scu_base __initdata;
 176
 177 static void __init ct_ca9x4_init_cpu_map(void)
 178 {
 179         int i, ncores;
 180
 181         ct_ca9x4_scu_base = ioremap(A9_MPCORE_SCU, SZ_128);
 182         if (WARN_ON(!ct_ca9x4_scu_base))
 183                 return;
 184
 185         ncores = scu_get_core_count(ct_ca9x4_scu_base);
 186
 187         if (ncores > nr_cpu_ids) {
 188                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
 189                         ncores, nr_cpu_ids);
 190                 ncores = nr_cpu_ids;
 191         }
 192
 193         for (i = 0; i < ncores; ++i)
 194                 set_cpu_possible(i, true);
 195 }
 196
 197 static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)
 198 {
 199         scu_enable(ct_ca9x4_scu_base);
 200 }
 201 #endif
 202
 203 struct ct_desc ct_ca9x4_desc __initdata = {
 204         .id             = V2M_CT_ID_CA9,
 205         .name           = "CA9x4",
 206         .map_io         = ct_ca9x4_map_io,
 207         .init_irq       = ct_ca9x4_init_irq,
 208         .init_tile      = ct_ca9x4_init,
 209 #ifdef CONFIG_SMP
 210         .init_cpu_map   = ct_ca9x4_init_cpu_map,
 211         .smp_enable     = ct_ca9x4_smp_enable,
 212 #endif
 213 };