| blob | 3db2c2f04a303711e3c154a0ea2ebb5a3c17faa2 |
1 /*
2 * linux/arch/arm/mm/proc-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is the "shell" of the ARMv7 processor support.
11 */
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #ifdef CONFIG_ARM_LPAE
23 #include "proc-v7-3level.S"
24 #else
25 #include "proc-v7-2level.S"
26 #endif
28 ENTRY(cpu_v7_proc_init)
29 mov pc, lr
30 ENDPROC(cpu_v7_proc_init)
32 ENTRY(cpu_v7_proc_fin)
33 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
34 bic r0, r0, #0x1000 @ ...i............
35 bic r0, r0, #0x0006 @ .............ca.
36 mcr p15, 0, r0, c1, c0, 0 @ disable caches
37 mov pc, lr
38 ENDPROC(cpu_v7_proc_fin)
40 /*
41 * cpu_v7_reset(loc)
42 *
43 * Perform a soft reset of the system. Put the CPU into the
44 * same state as it would be if it had been reset, and branch
45 * to what would be the reset vector.
46 *
47 * - loc - location to jump to for soft reset
48 *
49 * This code must be executed using a flat identity mapping with
50 * caches disabled.
51 */
52 .align 5
53 .pushsection .idmap.text, "ax"
54 ENTRY(cpu_v7_reset)
55 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
56 bic r1, r1, #0x1 @ ...............m
57 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
58 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
59 isb
60 bx r0
61 ENDPROC(cpu_v7_reset)
62 .popsection
64 /*
65 * cpu_v7_do_idle()
66 *
67 * Idle the processor (eg, wait for interrupt).
68 *
69 * IRQs are already disabled.
70 */
71 ENTRY(cpu_v7_do_idle)
72 dsb @ WFI may enter a low-power mode
73 wfi
74 mov pc, lr
75 ENDPROC(cpu_v7_do_idle)
77 ENTRY(cpu_v7_dcache_clean_area)
78 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
79 ALT_UP_B(1f)
80 mov pc, lr
81 1: dcache_line_size r2, r3
82 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
83 add r0, r0, r2
84 subs r1, r1, r2
85 bhi 2b
86 dsb ishst
87 mov pc, lr
88 ENDPROC(cpu_v7_dcache_clean_area)
90 string cpu_v7_name, "ARMv7 Processor"
91 .align
93 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
94 .globl cpu_v7_suspend_size
95 .equ cpu_v7_suspend_size, 4 * 9
96 #ifdef CONFIG_ARM_CPU_SUSPEND
97 ENTRY(cpu_v7_do_suspend)
98 stmfd sp!, {r4 - r10, lr}
99 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
100 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
101 stmia r0!, {r4 - r5}
102 #ifdef CONFIG_MMU
103 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
104 #ifdef CONFIG_ARM_LPAE
105 mrrc p15, 1, r5, r7, c2 @ TTB 1
106 #else
107 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
108 #endif
109 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
110 #endif
111 mrc p15, 0, r8, c1, c0, 0 @ Control register
112 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
113 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
114 stmia r0, {r5 - r11}
115 ldmfd sp!, {r4 - r10, pc}
116 ENDPROC(cpu_v7_do_suspend)
118 ENTRY(cpu_v7_do_resume)
119 mov ip, #0
120 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
121 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
122 ldmia r0!, {r4 - r5}
123 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
124 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
125 ldmia r0, {r5 - r11}
126 #ifdef CONFIG_MMU
127 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
128 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
129 #ifdef CONFIG_ARM_LPAE
130 mcrr p15, 0, r1, ip, c2 @ TTB 0
131 mcrr p15, 1, r5, r7, c2 @ TTB 1
132 #else
133 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
134 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
135 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
136 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
137 #endif
138 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
139 ldr r4, =PRRR @ PRRR
140 ldr r5, =NMRR @ NMRR
141 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
142 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
143 #endif /* CONFIG_MMU */
144 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
145 teq r4, r9 @ Is it already set?
146 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
147 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
148 isb
149 dsb
150 mov r0, r8 @ control register
151 b cpu_resume_mmu
152 ENDPROC(cpu_v7_do_resume)
153 #endif
155 #ifdef CONFIG_CPU_PJ4B
156 globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
157 globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
158 globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
159 globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
160 globl_equ cpu_pj4b_reset, cpu_v7_reset
161 #ifdef CONFIG_PJ4B_ERRATA_4742
162 ENTRY(cpu_pj4b_do_idle)
163 dsb @ WFI may enter a low-power mode
164 wfi
165 dsb @barrier
166 mov pc, lr
167 ENDPROC(cpu_pj4b_do_idle)
168 #else
169 globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
170 #endif
171 globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
172 #ifdef CONFIG_ARM_CPU_SUSPEND
173 ENTRY(cpu_pj4b_do_suspend)
174 stmfd sp!, {r6 - r10}
175 mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features
176 mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0
177 mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
178 mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1
179 mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC
180 stmia r0!, {r6 - r10}
181 ldmfd sp!, {r6 - r10}
182 b cpu_v7_do_suspend
183 ENDPROC(cpu_pj4b_do_suspend)
185 ENTRY(cpu_pj4b_do_resume)
186 ldmia r0!, {r6 - r10}
187 mcr p15, 1, r6, c15, c1, 0 @ save CP15 - extra features
188 mcr p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0
189 mcr p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
190 mcr p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1
191 mcr p15, 0, r10, c9, c14, 0 @ save CP15 - PMC
192 b cpu_v7_do_resume
193 ENDPROC(cpu_pj4b_do_resume)
194 #endif
195 .globl cpu_pj4b_suspend_size
196 .equ cpu_pj4b_suspend_size, 4 * 14
198 #endif
200 /*
201 * __v7_setup
202 *
203 * Initialise TLB, Caches, and MMU state ready to switch the MMU
204 * on. Return in r0 the new CP15 C1 control register setting.
205 *
206 * This should be able to cover all ARMv7 cores.
207 *
208 * It is assumed that:
209 * - cache type register is implemented
210 */
211 __v7_ca5mp_setup:
212 __v7_ca9mp_setup:
213 __v7_cr7mp_setup:
214 mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
215 b 1f
216 __v7_ca7mp_setup:
217 __v7_ca12mp_setup:
218 __v7_ca15mp_setup:
219 __v7_ca17mp_setup:
220 mov r10, #0
221 1:
222 #ifdef CONFIG_SMP
223 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
224 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
225 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
226 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
227 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
228 mcreq p15, 0, r0, c1, c0, 1
229 #endif
230 b __v7_setup
232 __v7_pj4b_setup:
233 #ifdef CONFIG_CPU_PJ4B
235 /* Auxiliary Debug Modes Control 1 Register */
236 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
237 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
238 #define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
239 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
241 /* Auxiliary Debug Modes Control 2 Register */
242 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
243 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
244 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
245 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
246 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
247 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
248 PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
250 /* Auxiliary Functional Modes Control Register 0 */
251 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
252 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
253 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
255 /* Auxiliary Debug Modes Control 0 Register */
256 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
258 /* Auxiliary Debug Modes Control 1 Register */
259 mrc p15, 1, r0, c15, c1, 1
260 orr r0, r0, #PJ4B_CLEAN_LINE
261 orr r0, r0, #PJ4B_BCK_OFF_STREX
262 orr r0, r0, #PJ4B_INTER_PARITY
263 bic r0, r0, #PJ4B_STATIC_BP
264 mcr p15, 1, r0, c15, c1, 1
266 /* Auxiliary Debug Modes Control 2 Register */
267 mrc p15, 1, r0, c15, c1, 2
268 bic r0, r0, #PJ4B_FAST_LDR
269 orr r0, r0, #PJ4B_AUX_DBG_CTRL2
270 mcr p15, 1, r0, c15, c1, 2
272 /* Auxiliary Functional Modes Control Register 0 */
273 mrc p15, 1, r0, c15, c2, 0
274 #ifdef CONFIG_SMP
275 orr r0, r0, #PJ4B_SMP_CFB
276 #endif
277 orr r0, r0, #PJ4B_L1_PAR_CHK
278 orr r0, r0, #PJ4B_BROADCAST_CACHE
279 mcr p15, 1, r0, c15, c2, 0
281 /* Auxiliary Debug Modes Control 0 Register */
282 mrc p15, 1, r0, c15, c1, 0
283 orr r0, r0, #PJ4B_WFI_WFE
284 mcr p15, 1, r0, c15, c1, 0
286 #endif /* CONFIG_CPU_PJ4B */
288 __v7_setup:
289 adr r12, __v7_setup_stack @ the local stack
290 stmia r12, {r0-r5, r7, r9, r11, lr}
291 bl v7_flush_dcache_louis
292 ldmia r12, {r0-r5, r7, r9, r11, lr}
294 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
295 and r10, r0, #0xff000000 @ ARM?
296 teq r10, #0x41000000
297 bne 3f
298 and r5, r0, #0x00f00000 @ variant
299 and r6, r0, #0x0000000f @ revision
300 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
301 ubfx r0, r0, #4, #12 @ primary part number
303 /* Cortex-A8 Errata */
304 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
305 teq r0, r10
306 bne 2f
307 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
309 teq r5, #0x00100000 @ only present in r1p*
310 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
311 orreq r10, r10, #(1 << 6) @ set IBE to 1
312 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
313 #endif
314 #ifdef CONFIG_ARM_ERRATA_458693
315 teq r6, #0x20 @ only present in r2p0
316 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
317 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
318 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
319 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
320 #endif
321 #ifdef CONFIG_ARM_ERRATA_460075
322 teq r6, #0x20 @ only present in r2p0
323 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
324 tsteq r10, #1 << 22
325 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
326 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
327 #endif
328 b 3f
330 /* Cortex-A9 Errata */
331 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
332 teq r0, r10
333 bne 3f
334 #ifdef CONFIG_ARM_ERRATA_742230
335 cmp r6, #0x22 @ only present up to r2p2
336 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
337 orrle r10, r10, #1 << 4 @ set bit #4
338 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
339 #endif
340 #ifdef CONFIG_ARM_ERRATA_742231
341 teq r6, #0x20 @ present in r2p0
342 teqne r6, #0x21 @ present in r2p1
343 teqne r6, #0x22 @ present in r2p2
344 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
345 orreq r10, r10, #1 << 12 @ set bit #12
346 orreq r10, r10, #1 << 22 @ set bit #22
347 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
348 #endif
349 #ifdef CONFIG_ARM_ERRATA_743622
350 teq r5, #0x00200000 @ only present in r2p*
351 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
352 orreq r10, r10, #1 << 6 @ set bit #6
353 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
354 #endif
355 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
356 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
357 ALT_UP_B(1f)
358 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
359 orrlt r10, r10, #1 << 11 @ set bit #11
360 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
361 1:
362 #endif
364 /* Cortex-A15 Errata */
365 3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
366 teq r0, r10
367 bne 4f
369 #ifdef CONFIG_ARM_ERRATA_773022
370 cmp r6, #0x4 @ only present up to r0p4
371 mrcle p15, 0, r10, c1, c0, 1 @ read aux control register
372 orrle r10, r10, #1 << 1 @ disable loop buffer
373 mcrle p15, 0, r10, c1, c0, 1 @ write aux control register
374 #endif
376 4: mov r10, #0
377 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
378 #ifdef CONFIG_MMU
379 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
380 v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
381 ldr r5, =PRRR @ PRRR
382 ldr r6, =NMRR @ NMRR
383 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
384 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
385 #endif
386 dsb @ Complete invalidations
387 #ifndef CONFIG_ARM_THUMBEE
388 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
389 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
390 teq r0, #(1 << 12) @ check if ThumbEE is present
391 bne 1f
392 mov r5, #0
393 mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
394 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
395 orr r0, r0, #1 @ set the 1st bit in order to
396 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
397 1:
398 #endif
399 adr r5, v7_crval
400 ldmia r5, {r5, r6}
401 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
402 #ifdef CONFIG_SWP_EMULATE
403 orr r5, r5, #(1 << 10) @ set SW bit in "clear"
404 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
405 #endif
406 mrc p15, 0, r0, c1, c0, 0 @ read control register
407 bic r0, r0, r5 @ clear bits them
408 orr r0, r0, r6 @ set them
409 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
410 mov pc, lr @ return to head.S:__ret
411 ENDPROC(__v7_setup)
413 .align 2
414 __v7_setup_stack:
415 .space 4 * 11 @ 11 registers
417 __INITDATA
419 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
420 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
421 #ifdef CONFIG_CPU_PJ4B
422 define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
423 #endif
425 .section ".rodata"
427 string cpu_arch_name, "armv7"
428 string cpu_elf_name, "v7"
429 .align
431 .section ".proc.info.init", #alloc, #execinstr
433 /*
434 * Standard v7 proc info content
435 */
436 .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
437 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
438 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
439 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
440 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
441 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
442 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
443 W(b) \initfunc
444 .long cpu_arch_name
445 .long cpu_elf_name
446 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
447 HWCAP_EDSP | HWCAP_TLS | \hwcaps
448 .long cpu_v7_name
449 .long \proc_fns
450 .long v7wbi_tlb_fns
451 .long v6_user_fns
452 .long v7_cache_fns
453 .endm
455 #ifndef CONFIG_ARM_LPAE
456 /*
457 * ARM Ltd. Cortex A5 processor.
458 */
459 .type __v7_ca5mp_proc_info, #object
460 __v7_ca5mp_proc_info:
461 .long 0x410fc050
462 .long 0xff0ffff0
463 __v7_proc __v7_ca5mp_setup
464 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
466 /*
467 * ARM Ltd. Cortex A9 processor.
468 */
469 .type __v7_ca9mp_proc_info, #object
470 __v7_ca9mp_proc_info:
471 .long 0x410fc090
472 .long 0xff0ffff0
473 __v7_proc __v7_ca9mp_setup
474 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
476 #endif /* CONFIG_ARM_LPAE */
478 /*
479 * Marvell PJ4B processor.
480 */
481 #ifdef CONFIG_CPU_PJ4B
482 .type __v7_pj4b_proc_info, #object
483 __v7_pj4b_proc_info:
484 .long 0x560f5800
485 .long 0xff0fff00
486 __v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
487 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
488 #endif
490 /*
491 * ARM Ltd. Cortex R7 processor.
492 */
493 .type __v7_cr7mp_proc_info, #object
494 __v7_cr7mp_proc_info:
495 .long 0x410fc170
496 .long 0xff0ffff0
497 __v7_proc __v7_cr7mp_setup
498 .size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
500 /*
501 * ARM Ltd. Cortex A7 processor.
502 */
503 .type __v7_ca7mp_proc_info, #object
504 __v7_ca7mp_proc_info:
505 .long 0x410fc070
506 .long 0xff0ffff0
507 __v7_proc __v7_ca7mp_setup
508 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
510 /*
511 * ARM Ltd. Cortex A12 processor.
512 */
513 .type __v7_ca12mp_proc_info, #object
514 __v7_ca12mp_proc_info:
515 .long 0x410fc0d0
516 .long 0xff0ffff0
517 __v7_proc __v7_ca12mp_setup
518 .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
520 /*
521 * ARM Ltd. Cortex A15 processor.
522 */
523 .type __v7_ca15mp_proc_info, #object
524 __v7_ca15mp_proc_info:
525 .long 0x410fc0f0
526 .long 0xff0ffff0
527 __v7_proc __v7_ca15mp_setup
528 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
530 /*
531 * ARM Ltd. Cortex A17 processor.
532 */
533 .type __v7_ca17mp_proc_info, #object
534 __v7_ca17mp_proc_info:
535 .long 0x410fc0e0
536 .long 0xff0ffff0
537 __v7_proc __v7_ca17mp_setup
538 .size __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
540 /*
541 * Qualcomm Inc. Krait processors.
542 */
543 .type __krait_proc_info, #object
544 __krait_proc_info:
545 .long 0x510f0400 @ Required ID value
546 .long 0xff0ffc00 @ Mask for ID
547 /*
548 * Some Krait processors don't indicate support for SDIV and UDIV
549 * instructions in the ARM instruction set, even though they actually
550 * do support them.
551 */
552 __v7_proc __v7_setup, hwcaps = HWCAP_IDIV
553 .size __krait_proc_info, . - __krait_proc_info
555 /*
556 * Match any ARMv7 processor core.
557 */
558 .type __v7_proc_info, #object
559 __v7_proc_info:
560 .long 0x000f0000 @ Required ID value
561 .long 0x000f0000 @ Mask for ID
562 __v7_proc __v7_setup
563 .size __v7_proc_info, . - __v7_proc_info