1 /* linux/arch/arm/plat-s3c24xx/clock.c
3 * Copyright 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C24XX Core clock control support
8 * Based on, and code from linux/arch/arm/mach-versatile/clock.c
10 ** Copyright (C) 2004 ARM Limited.
11 ** Written by Deep Blue Solutions Limited.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/errno.h>
34 #include <linux/err.h>
35 #include <linux/platform_device.h>
36 #include <linux/device.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/clk.h>
40 #include <linux/spinlock.h>
42 #if defined(CONFIG_DEBUG_FS)
43 #include <linux/debugfs.h>
48 #include <plat/cpu-freq.h>
50 #include <plat/clock.h>
53 #include <linux/serial_core.h>
54 #include <linux/serial_s3c.h> /* for s3c24xx_uart_devs */
56 /* clock information */
58 static LIST_HEAD(clocks
);
60 /* We originally used an mutex here, but some contexts (see resume)
61 * are calling functions such as clk_set_parent() with IRQs disabled
62 * causing an BUG to be triggered.
64 DEFINE_SPINLOCK(clocks_lock
);
66 /* Global watchdog clock used by arch_wtd_reset() callback */
67 struct clk
*s3c2410_wdtclk
;
68 static int __init
s3c_wdt_reset_init(void)
70 s3c2410_wdtclk
= clk_get(NULL
, "watchdog");
71 if (IS_ERR(s3c2410_wdtclk
))
72 printk(KERN_WARNING
"%s: warning: cannot get watchdog clock\n", __func__
);
75 arch_initcall(s3c_wdt_reset_init
);
77 /* enable and disable calls for use with the clk struct */
79 static int clk_null_enable(struct clk
*clk
, int enable
)
84 int clk_enable(struct clk
*clk
)
88 if (IS_ERR(clk
) || clk
== NULL
)
91 clk_enable(clk
->parent
);
93 spin_lock_irqsave(&clocks_lock
, flags
);
95 if ((clk
->usage
++) == 0)
96 (clk
->enable
)(clk
, 1);
98 spin_unlock_irqrestore(&clocks_lock
, flags
);
102 void clk_disable(struct clk
*clk
)
106 if (IS_ERR(clk
) || clk
== NULL
)
109 spin_lock_irqsave(&clocks_lock
, flags
);
111 if ((--clk
->usage
) == 0)
112 (clk
->enable
)(clk
, 0);
114 spin_unlock_irqrestore(&clocks_lock
, flags
);
115 clk_disable(clk
->parent
);
119 unsigned long clk_get_rate(struct clk
*clk
)
121 if (IS_ERR_OR_NULL(clk
))
127 if (clk
->ops
!= NULL
&& clk
->ops
->get_rate
!= NULL
)
128 return (clk
->ops
->get_rate
)(clk
);
130 if (clk
->parent
!= NULL
)
131 return clk_get_rate(clk
->parent
);
136 long clk_round_rate(struct clk
*clk
, unsigned long rate
)
138 if (!IS_ERR_OR_NULL(clk
) && clk
->ops
&& clk
->ops
->round_rate
)
139 return (clk
->ops
->round_rate
)(clk
, rate
);
144 int clk_set_rate(struct clk
*clk
, unsigned long rate
)
149 if (IS_ERR_OR_NULL(clk
))
152 /* We do not default just do a clk->rate = rate as
153 * the clock may have been made this way by choice.
156 WARN_ON(clk
->ops
== NULL
);
157 WARN_ON(clk
->ops
&& clk
->ops
->set_rate
== NULL
);
159 if (clk
->ops
== NULL
|| clk
->ops
->set_rate
== NULL
)
162 spin_lock_irqsave(&clocks_lock
, flags
);
163 ret
= (clk
->ops
->set_rate
)(clk
, rate
);
164 spin_unlock_irqrestore(&clocks_lock
, flags
);
169 struct clk
*clk_get_parent(struct clk
*clk
)
174 int clk_set_parent(struct clk
*clk
, struct clk
*parent
)
179 if (IS_ERR_OR_NULL(clk
) || IS_ERR_OR_NULL(parent
))
182 spin_lock_irqsave(&clocks_lock
, flags
);
184 if (clk
->ops
&& clk
->ops
->set_parent
)
185 ret
= (clk
->ops
->set_parent
)(clk
, parent
);
187 spin_unlock_irqrestore(&clocks_lock
, flags
);
192 EXPORT_SYMBOL(clk_enable
);
193 EXPORT_SYMBOL(clk_disable
);
194 EXPORT_SYMBOL(clk_get_rate
);
195 EXPORT_SYMBOL(clk_round_rate
);
196 EXPORT_SYMBOL(clk_set_rate
);
197 EXPORT_SYMBOL(clk_get_parent
);
198 EXPORT_SYMBOL(clk_set_parent
);
202 int clk_default_setrate(struct clk
*clk
, unsigned long rate
)
208 struct clk_ops clk_ops_def_setrate
= {
209 .set_rate
= clk_default_setrate
,
212 struct clk clk_xtal
= {
219 struct clk clk_ext
= {
223 struct clk clk_epll
= {
227 struct clk clk_mpll
= {
229 .ops
= &clk_ops_def_setrate
,
232 struct clk clk_upll
= {
250 .ops
= &clk_ops_def_setrate
,
258 .ops
= &clk_ops_def_setrate
,
261 struct clk clk_usb_bus
= {
268 struct clk s3c24xx_uclk
= {
272 /* initialise the clock system */
275 * s3c24xx_register_clock() - register a clock
276 * @clk: The clock to register
278 * Add the specified clock to the list of clocks known by the system.
280 int s3c24xx_register_clock(struct clk
*clk
)
282 if (clk
->enable
== NULL
)
283 clk
->enable
= clk_null_enable
;
285 /* fill up the clk_lookup structure and register it*/
286 clk
->lookup
.dev_id
= clk
->devname
;
287 clk
->lookup
.con_id
= clk
->name
;
288 clk
->lookup
.clk
= clk
;
289 clkdev_add(&clk
->lookup
);
295 * s3c24xx_register_clocks() - register an array of clock pointers
296 * @clks: Pointer to an array of struct clk pointers
297 * @nr_clks: The number of clocks in the @clks array.
299 * Call s3c24xx_register_clock() for all the clock pointers contained
300 * in the @clks list. Returns the number of failures.
302 int s3c24xx_register_clocks(struct clk
**clks
, int nr_clks
)
306 for (; nr_clks
> 0; nr_clks
--, clks
++) {
307 if (s3c24xx_register_clock(*clks
) < 0) {
308 struct clk
*clk
= *clks
;
309 printk(KERN_ERR
"%s: failed to register %p: %s\n",
310 __func__
, clk
, clk
->name
);
319 * s3c_register_clocks() - register an array of clocks
320 * @clkp: Pointer to the first clock in the array.
321 * @nr_clks: Number of clocks to register.
323 * Call s3c24xx_register_clock() on the @clkp array given, printing an
324 * error if it fails to register the clock (unlikely).
326 void __init
s3c_register_clocks(struct clk
*clkp
, int nr_clks
)
330 for (; nr_clks
> 0; nr_clks
--, clkp
++) {
331 ret
= s3c24xx_register_clock(clkp
);
334 printk(KERN_ERR
"Failed to register clock %s (%d)\n",
341 * s3c_disable_clocks() - disable an array of clocks
342 * @clkp: Pointer to the first clock in the array.
343 * @nr_clks: Number of clocks to register.
345 * for internal use only at initialisation time. disable the clocks in the
349 void __init
s3c_disable_clocks(struct clk
*clkp
, int nr_clks
)
351 for (; nr_clks
> 0; nr_clks
--, clkp
++)
352 (clkp
->enable
)(clkp
, 0);
355 /* initialise all the clocks */
357 int __init
s3c24xx_register_baseclocks(unsigned long xtal
)
359 printk(KERN_INFO
"S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");
361 clk_xtal
.rate
= xtal
;
363 /* register our clocks */
365 if (s3c24xx_register_clock(&clk_xtal
) < 0)
366 printk(KERN_ERR
"failed to register master xtal\n");
368 if (s3c24xx_register_clock(&clk_mpll
) < 0)
369 printk(KERN_ERR
"failed to register mpll clock\n");
371 if (s3c24xx_register_clock(&clk_upll
) < 0)
372 printk(KERN_ERR
"failed to register upll clock\n");
374 if (s3c24xx_register_clock(&clk_f
) < 0)
375 printk(KERN_ERR
"failed to register cpu fclk\n");
377 if (s3c24xx_register_clock(&clk_h
) < 0)
378 printk(KERN_ERR
"failed to register cpu hclk\n");
380 if (s3c24xx_register_clock(&clk_p
) < 0)
381 printk(KERN_ERR
"failed to register cpu pclk\n");
386 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
387 /* debugfs support to trace clock tree hierarchy and attributes */
389 static struct dentry
*clk_debugfs_root
;
391 static void clock_tree_show_one(struct seq_file
*s
, struct clk
*c
, int level
)
395 char buf
[255] = { 0 };
399 n
= snprintf(buf
, sizeof(buf
) - 1, "%s", c
->name
);
402 n
+= snprintf(buf
+ n
, sizeof(buf
) - 1 - n
, ":%s", c
->devname
);
404 state
= (c
->usage
> 0) ? "on" : "off";
406 seq_printf(s
, "%*s%-*s %-6s %-3d %-10lu\n",
409 state
, c
->usage
, clk_get_rate(c
));
411 list_for_each_entry(child
, &clocks
, list
) {
412 if (child
->parent
!= c
)
415 clock_tree_show_one(s
, child
, level
+ 1);
419 static int clock_tree_show(struct seq_file
*s
, void *data
)
424 seq_printf(s
, " clock state ref rate\n");
425 seq_printf(s
, "----------------------------------------------------\n");
427 spin_lock_irqsave(&clocks_lock
, flags
);
429 list_for_each_entry(c
, &clocks
, list
)
430 if (c
->parent
== NULL
)
431 clock_tree_show_one(s
, c
, 0);
433 spin_unlock_irqrestore(&clocks_lock
, flags
);
437 static int clock_tree_open(struct inode
*inode
, struct file
*file
)
439 return single_open(file
, clock_tree_show
, inode
->i_private
);
442 static const struct file_operations clock_tree_fops
= {
443 .open
= clock_tree_open
,
446 .release
= single_release
,
449 static int clock_rate_show(void *data
, u64
*val
)
451 struct clk
*c
= data
;
452 *val
= clk_get_rate(c
);
455 DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops
, clock_rate_show
, NULL
, "%llu\n");
457 static int clk_debugfs_register_one(struct clk
*c
)
461 struct clk
*pa
= c
->parent
;
465 p
+= sprintf(p
, "%s", c
->devname
);
467 d
= debugfs_create_dir(s
, pa
? pa
->dent
: clk_debugfs_root
);
473 d
= debugfs_create_u8("usecount", S_IRUGO
, c
->dent
, (u8
*)&c
->usage
);
479 d
= debugfs_create_file("rate", S_IRUGO
, c
->dent
, c
, &clock_rate_fops
);
487 debugfs_remove_recursive(c
->dent
);
491 static int clk_debugfs_register(struct clk
*c
)
494 struct clk
*pa
= c
->parent
;
496 if (pa
&& !pa
->dent
) {
497 err
= clk_debugfs_register(pa
);
503 err
= clk_debugfs_register_one(c
);
510 static int __init
clk_debugfs_init(void)
516 d
= debugfs_create_dir("clock", NULL
);
519 clk_debugfs_root
= d
;
521 d
= debugfs_create_file("clock_tree", S_IRUGO
, clk_debugfs_root
, NULL
,
526 list_for_each_entry(c
, &clocks
, list
) {
527 err
= clk_debugfs_register(c
);
534 debugfs_remove_recursive(clk_debugfs_root
);
537 late_initcall(clk_debugfs_init
);
539 #endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */