arch/arm/plat-samsung/pm-debug.c

   1 /*
   2  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   3  *      Tomasz Figa <t.figa@samsung.com>
   4  * Copyright (C) 2008 Openmoko, Inc.
   5  * Copyright (C) 2004-2008 Simtec Electronics
   6  *      Ben Dooks <ben@simtec.co.uk>
   7  *      http://armlinux.simtec.co.uk/
   8  *
   9  * Samsung common power management (suspend to RAM) debug support
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/serial_core.h>
  17 #include <linux/io.h>
  18
  19 #include <asm/mach/map.h>
  20
  21 #include <plat/cpu.h>
  22 #include <plat/pm-common.h>
  23
  24 #ifdef CONFIG_SAMSUNG_ATAGS
  25 #include <mach/pm-core.h>
  26 #else
  27 static inline void s3c_pm_debug_init_uart(void) {}
  28 static inline void s3c_pm_arch_update_uart(void __iomem *regs,
  29                                            struct pm_uart_save *save) {}
  30 #endif
  31
  32 static struct pm_uart_save uart_save;
  33
  34 extern void printascii(const char *);
  35
  36 void s3c_pm_dbg(const char *fmt, ...)
  37 {
  38         va_list va;
  39         char buff[256];
  40
  41         va_start(va, fmt);
  42         vsnprintf(buff, sizeof(buff), fmt, va);
  43         va_end(va);
  44
  45         printascii(buff);
  46 }
  47
  48 void s3c_pm_debug_init(void)
  49 {
  50         /* restart uart clocks so we can use them to output */
  51         s3c_pm_debug_init_uart();
  52 }
  53
  54 static inline void __iomem *s3c_pm_uart_base(void)
  55 {
  56         unsigned long paddr;
  57         unsigned long vaddr;
  58
  59         debug_ll_addr(&paddr, &vaddr);
  60
  61         return (void __iomem *)vaddr;
  62 }
  63
  64 void s3c_pm_save_uarts(void)
  65 {
  66         void __iomem *regs = s3c_pm_uart_base();
  67         struct pm_uart_save *save = &uart_save;
  68
  69         save->ulcon = __raw_readl(regs + S3C2410_ULCON);
  70         save->ucon = __raw_readl(regs + S3C2410_UCON);
  71         save->ufcon = __raw_readl(regs + S3C2410_UFCON);
  72         save->umcon = __raw_readl(regs + S3C2410_UMCON);
  73         save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
  74
  75         if (!soc_is_s3c2410())
  76                 save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
  77
  78         S3C_PMDBG("UART[%p]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
  79                   regs, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
  80 }
  81
  82 void s3c_pm_restore_uarts(void)
  83 {
  84         void __iomem *regs = s3c_pm_uart_base();
  85         struct pm_uart_save *save = &uart_save;
  86
  87         s3c_pm_arch_update_uart(regs, save);
  88
  89         __raw_writel(save->ulcon, regs + S3C2410_ULCON);
  90         __raw_writel(save->ucon,  regs + S3C2410_UCON);
  91         __raw_writel(save->ufcon, regs + S3C2410_UFCON);
  92         __raw_writel(save->umcon, regs + S3C2410_UMCON);
  93         __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
  94
  95         if (!soc_is_s3c2410())
  96                 __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
  97 }