Merge tag 'locks-v3.16-2' of git://git.samba.org/jlayton/linux
[linux/fpc-iii.git] / arch / blackfin / include / asm / bfin_rotary.h
blob8895a750c70c6511c29507c7f6532b30aff3479d
1 /*
2 * board initialization should put one of these structures into platform_data
3 * and place the bfin-rotary onto platform_bus named "bfin-rotary".
5 * Copyright 2008-2010 Analog Devices Inc.
7 * Licensed under the GPL-2 or later.
8 */
10 #ifndef _BFIN_ROTARY_H
11 #define _BFIN_ROTARY_H
13 /* mode bitmasks */
14 #define ROT_QUAD_ENC CNTMODE_QUADENC /* quadrature/grey code encoder mode */
15 #define ROT_BIN_ENC CNTMODE_BINENC /* binary encoder mode */
16 #define ROT_UD_CNT CNTMODE_UDCNT /* rotary counter mode */
17 #define ROT_DIR_CNT CNTMODE_DIRCNT /* direction counter mode */
19 #define ROT_DEBE DEBE /* Debounce Enable */
21 #define ROT_CDGINV CDGINV /* CDG Pin Polarity Invert */
22 #define ROT_CUDINV CUDINV /* CUD Pin Polarity Invert */
23 #define ROT_CZMINV CZMINV /* CZM Pin Polarity Invert */
25 struct bfin_rotary_platform_data {
26 /* set rotary UP KEY_### or BTN_### in case you prefer
27 * bfin-rotary to send EV_KEY otherwise set 0
29 unsigned int rotary_up_key;
30 /* set rotary DOWN KEY_### or BTN_### in case you prefer
31 * bfin-rotary to send EV_KEY otherwise set 0
33 unsigned int rotary_down_key;
34 /* set rotary BUTTON KEY_### or BTN_### */
35 unsigned int rotary_button_key;
36 /* set rotary Relative Axis REL_### in case you prefer
37 * bfin-rotary to send EV_REL otherwise set 0
39 unsigned int rotary_rel_code;
40 unsigned short debounce; /* 0..17 */
41 unsigned short mode;
42 unsigned short pm_wakeup;
45 /* CNT_CONFIG bitmasks */
46 #define CNTE (1 << 0) /* Counter Enable */
47 #define DEBE (1 << 1) /* Debounce Enable */
48 #define CDGINV (1 << 4) /* CDG Pin Polarity Invert */
49 #define CUDINV (1 << 5) /* CUD Pin Polarity Invert */
50 #define CZMINV (1 << 6) /* CZM Pin Polarity Invert */
51 #define CNTMODE_SHIFT 8
52 #define CNTMODE (0x7 << CNTMODE_SHIFT) /* Counter Operating Mode */
53 #define ZMZC (1 << 1) /* CZM Zeroes Counter Enable */
54 #define BNDMODE_SHIFT 12
55 #define BNDMODE (0x3 << BNDMODE_SHIFT) /* Boundary register Mode */
56 #define INPDIS (1 << 15) /* CUG and CDG Input Disable */
58 #define CNTMODE_QUADENC (0 << CNTMODE_SHIFT) /* quadrature encoder mode */
59 #define CNTMODE_BINENC (1 << CNTMODE_SHIFT) /* binary encoder mode */
60 #define CNTMODE_UDCNT (2 << CNTMODE_SHIFT) /* up/down counter mode */
61 #define CNTMODE_DIRCNT (4 << CNTMODE_SHIFT) /* direction counter mode */
62 #define CNTMODE_DIRTMR (5 << CNTMODE_SHIFT) /* direction timer mode */
64 #define BNDMODE_COMP (0 << BNDMODE_SHIFT) /* boundary compare mode */
65 #define BNDMODE_ZERO (1 << BNDMODE_SHIFT) /* boundary compare and zero mode */
66 #define BNDMODE_CAPT (2 << BNDMODE_SHIFT) /* boundary capture mode */
67 #define BNDMODE_AEXT (3 << BNDMODE_SHIFT) /* boundary auto-extend mode */
69 /* CNT_IMASK bitmasks */
70 #define ICIE (1 << 0) /* Illegal Gray/Binary Code Interrupt Enable */
71 #define UCIE (1 << 1) /* Up count Interrupt Enable */
72 #define DCIE (1 << 2) /* Down count Interrupt Enable */
73 #define MINCIE (1 << 3) /* Min Count Interrupt Enable */
74 #define MAXCIE (1 << 4) /* Max Count Interrupt Enable */
75 #define COV31IE (1 << 5) /* Bit 31 Overflow Interrupt Enable */
76 #define COV15IE (1 << 6) /* Bit 15 Overflow Interrupt Enable */
77 #define CZEROIE (1 << 7) /* Count to Zero Interrupt Enable */
78 #define CZMIE (1 << 8) /* CZM Pin Interrupt Enable */
79 #define CZMEIE (1 << 9) /* CZM Error Interrupt Enable */
80 #define CZMZIE (1 << 10) /* CZM Zeroes Counter Interrupt Enable */
82 /* CNT_STATUS bitmasks */
83 #define ICII (1 << 0) /* Illegal Gray/Binary Code Interrupt Identifier */
84 #define UCII (1 << 1) /* Up count Interrupt Identifier */
85 #define DCII (1 << 2) /* Down count Interrupt Identifier */
86 #define MINCII (1 << 3) /* Min Count Interrupt Identifier */
87 #define MAXCII (1 << 4) /* Max Count Interrupt Identifier */
88 #define COV31II (1 << 5) /* Bit 31 Overflow Interrupt Identifier */
89 #define COV15II (1 << 6) /* Bit 15 Overflow Interrupt Identifier */
90 #define CZEROII (1 << 7) /* Count to Zero Interrupt Identifier */
91 #define CZMII (1 << 8) /* CZM Pin Interrupt Identifier */
92 #define CZMEII (1 << 9) /* CZM Error Interrupt Identifier */
93 #define CZMZII (1 << 10) /* CZM Zeroes Counter Interrupt Identifier */
95 /* CNT_COMMAND bitmasks */
96 #define W1LCNT 0xf /* Load Counter Register */
97 #define W1LMIN 0xf0 /* Load Min Register */
98 #define W1LMAX 0xf00 /* Load Max Register */
99 #define W1ZMONCE (1 << 12) /* Enable CZM Clear Counter Once */
101 #define W1LCNT_ZERO (1 << 0) /* write 1 to load CNT_COUNTER with zero */
102 #define W1LCNT_MIN (1 << 2) /* write 1 to load CNT_COUNTER from CNT_MIN */
103 #define W1LCNT_MAX (1 << 3) /* write 1 to load CNT_COUNTER from CNT_MAX */
105 #define W1LMIN_ZERO (1 << 4) /* write 1 to load CNT_MIN with zero */
106 #define W1LMIN_CNT (1 << 5) /* write 1 to load CNT_MIN from CNT_COUNTER */
107 #define W1LMIN_MAX (1 << 7) /* write 1 to load CNT_MIN from CNT_MAX */
109 #define W1LMAX_ZERO (1 << 8) /* write 1 to load CNT_MAX with zero */
110 #define W1LMAX_CNT (1 << 9) /* write 1 to load CNT_MAX from CNT_COUNTER */
111 #define W1LMAX_MIN (1 << 10) /* write 1 to load CNT_MAX from CNT_MIN */
113 /* CNT_DEBOUNCE bitmasks */
114 #define DPRESCALE 0xf /* Load Counter Register */
116 #endif