Merge tag 'locks-v3.16-2' of git://git.samba.org/jlayton/linux
[linux/fpc-iii.git] / arch / blackfin / mach-bf561 / boards / acvilon.c
blob430b16d5ccb1124f6fd896d4c8651050695d9053
1 /*
2 * File: arch/blackfin/mach-bf561/acvilon.c
3 * Based on: arch/blackfin/mach-bf561/ezkit.c
4 * Author:
6 * Created:
7 * Description:
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 * Copyright 2009 CJSC "NII STT"
13 * Bugs:
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 * For more information about Acvilon BF561 SoM please
32 * go to http://www.niistt.ru/
36 #include <linux/device.h>
37 #include <linux/platform_device.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/partitions.h>
40 #include <linux/mtd/physmap.h>
41 #include <linux/mtd/nand.h>
42 #include <linux/mtd/plat-ram.h>
43 #include <linux/spi/spi.h>
44 #include <linux/spi/flash.h>
45 #include <linux/irq.h>
46 #include <linux/interrupt.h>
47 #include <linux/jiffies.h>
48 #include <linux/i2c-pca-platform.h>
49 #include <linux/delay.h>
50 #include <linux/io.h>
51 #include <asm/dma.h>
52 #include <asm/bfin5xx_spi.h>
53 #include <asm/portmux.h>
54 #include <asm/dpmc.h>
55 #include <asm/cacheflush.h>
56 #include <linux/i2c.h>
59 * Name the Board for the /proc/cpuinfo
61 const char bfin_board_name[] = "Acvilon board";
63 #if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
64 #include <linux/usb/isp1760.h>
65 static struct resource bfin_isp1760_resources[] = {
66 [0] = {
67 .start = 0x20000000,
68 .end = 0x20000000 + 0x000fffff,
69 .flags = IORESOURCE_MEM,
71 [1] = {
72 .start = IRQ_PF15,
73 .end = IRQ_PF15,
74 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
78 static struct isp1760_platform_data isp1760_priv = {
79 .is_isp1761 = 0,
80 .port1_disable = 0,
81 .bus_width_16 = 1,
82 .port1_otg = 0,
83 .analog_oc = 0,
84 .dack_polarity_high = 0,
85 .dreq_polarity_high = 0,
88 static struct platform_device bfin_isp1760_device = {
89 .name = "isp1760-hcd",
90 .id = 0,
91 .dev = {
92 .platform_data = &isp1760_priv,
94 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
95 .resource = bfin_isp1760_resources,
97 #endif
99 static struct resource bfin_i2c_pca_resources[] = {
101 .name = "pca9564-regs",
102 .start = 0x2C000000,
103 .end = 0x2C000000 + 16,
104 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
105 }, {
107 .start = IRQ_PF8,
108 .end = IRQ_PF8,
109 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
113 struct i2c_pca9564_pf_platform_data pca9564_platform_data = {
114 .gpio = -1,
115 .i2c_clock_speed = 330000,
116 .timeout = HZ,
119 /* PCA9564 I2C Bus driver */
120 static struct platform_device bfin_i2c_pca_device = {
121 .name = "i2c-pca-platform",
122 .id = 0,
123 .num_resources = ARRAY_SIZE(bfin_i2c_pca_resources),
124 .resource = bfin_i2c_pca_resources,
125 .dev = {
126 .platform_data = &pca9564_platform_data,
130 /* I2C devices fitted. */
131 static struct i2c_board_info acvilon_i2c_devs[] __initdata = {
133 I2C_BOARD_INFO("ds1339", 0x68),
136 I2C_BOARD_INFO("tcn75", 0x49),
140 #if IS_ENABLED(CONFIG_MTD_PLATRAM)
141 static struct platdata_mtd_ram mtd_ram_data = {
142 .mapname = "rootfs(RAM)",
143 .bankwidth = 4,
146 static struct resource mtd_ram_resource = {
147 .start = 0x4000000,
148 .end = 0x5ffffff,
149 .flags = IORESOURCE_MEM,
152 static struct platform_device mtd_ram_device = {
153 .name = "mtd-ram",
154 .id = 0,
155 .dev = {
156 .platform_data = &mtd_ram_data,
158 .num_resources = 1,
159 .resource = &mtd_ram_resource,
161 #endif
163 #if IS_ENABLED(CONFIG_SMSC911X)
164 #include <linux/smsc911x.h>
165 static struct resource smsc911x_resources[] = {
167 .name = "smsc911x-memory",
168 .start = 0x28000000,
169 .end = 0x28000000 + 0xFF,
170 .flags = IORESOURCE_MEM,
173 .start = IRQ_PF7,
174 .end = IRQ_PF7,
175 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
179 static struct smsc911x_platform_config smsc911x_config = {
180 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
181 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
182 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
183 .phy_interface = PHY_INTERFACE_MODE_MII,
186 static struct platform_device smsc911x_device = {
187 .name = "smsc911x",
188 .id = 0,
189 .num_resources = ARRAY_SIZE(smsc911x_resources),
190 .resource = smsc911x_resources,
191 .dev = {
192 .platform_data = &smsc911x_config,
195 #endif
197 #if IS_ENABLED(CONFIG_SERIAL_BFIN)
198 #ifdef CONFIG_SERIAL_BFIN_UART0
199 static struct resource bfin_uart0_resources[] = {
201 .start = BFIN_UART_THR,
202 .end = BFIN_UART_GCTL + 2,
203 .flags = IORESOURCE_MEM,
206 .start = IRQ_UART_TX,
207 .end = IRQ_UART_TX,
208 .flags = IORESOURCE_IRQ,
211 .start = IRQ_UART_RX,
212 .end = IRQ_UART_RX,
213 .flags = IORESOURCE_IRQ,
216 .start = IRQ_UART_ERROR,
217 .end = IRQ_UART_ERROR,
218 .flags = IORESOURCE_IRQ,
221 .start = CH_UART_TX,
222 .end = CH_UART_TX,
223 .flags = IORESOURCE_DMA,
226 .start = CH_UART_RX,
227 .end = CH_UART_RX,
228 .flags = IORESOURCE_DMA,
232 static unsigned short bfin_uart0_peripherals[] = {
233 P_UART0_TX, P_UART0_RX, 0
236 static struct platform_device bfin_uart0_device = {
237 .name = "bfin-uart",
238 .id = 0,
239 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
240 .resource = bfin_uart0_resources,
241 .dev = {
242 /* Passed to driver */
243 .platform_data = &bfin_uart0_peripherals,
246 #endif
247 #endif
249 #if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
251 static struct mtd_partition bfin_plat_nand_partitions[] = {
253 .name = "params(nand)",
254 .size = 32 * 1024 * 1024,
255 .offset = 0,
256 }, {
257 .name = "userfs(nand)",
258 .size = MTDPART_SIZ_FULL,
259 .offset = MTDPART_OFS_APPEND,
263 #define BFIN_NAND_PLAT_CLE 2
264 #define BFIN_NAND_PLAT_ALE 3
266 static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
267 unsigned int ctrl)
269 struct nand_chip *this = mtd->priv;
271 if (cmd == NAND_CMD_NONE)
272 return;
274 if (ctrl & NAND_CLE)
275 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
276 else
277 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
280 #define BFIN_NAND_PLAT_READY GPIO_PF10
281 static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
283 return gpio_get_value(BFIN_NAND_PLAT_READY);
286 static struct platform_nand_data bfin_plat_nand_data = {
287 .chip = {
288 .nr_chips = 1,
289 .chip_delay = 30,
290 .partitions = bfin_plat_nand_partitions,
291 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
293 .ctrl = {
294 .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
295 .dev_ready = bfin_plat_nand_dev_ready,
299 #define MAX(x, y) (x > y ? x : y)
300 static struct resource bfin_plat_nand_resources = {
301 .start = 0x24000000,
302 .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
303 .flags = IORESOURCE_MEM,
306 static struct platform_device bfin_async_nand_device = {
307 .name = "gen_nand",
308 .id = -1,
309 .num_resources = 1,
310 .resource = &bfin_plat_nand_resources,
311 .dev = {
312 .platform_data = &bfin_plat_nand_data,
316 static void bfin_plat_nand_init(void)
318 gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
320 #else
321 static void bfin_plat_nand_init(void)
324 #endif
326 #if IS_ENABLED(CONFIG_MTD_DATAFLASH)
327 static struct mtd_partition bfin_spi_dataflash_partitions[] = {
329 .name = "bootloader",
330 .size = 0x4200,
331 .offset = 0,
332 .mask_flags = MTD_CAP_ROM},
334 .name = "u-boot",
335 .size = 0x42000,
336 .offset = MTDPART_OFS_APPEND,
339 .name = "u-boot(params)",
340 .size = 0x4200,
341 .offset = MTDPART_OFS_APPEND,
344 .name = "kernel",
345 .size = 0x294000,
346 .offset = MTDPART_OFS_APPEND,
349 .name = "params",
350 .size = 0x42000,
351 .offset = MTDPART_OFS_APPEND,
354 .name = "rootfs",
355 .size = MTDPART_SIZ_FULL,
356 .offset = MTDPART_OFS_APPEND,
360 static struct flash_platform_data bfin_spi_dataflash_data = {
361 .name = "SPI Dataflash",
362 .parts = bfin_spi_dataflash_partitions,
363 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
366 /* DataFlash chip */
367 static struct bfin5xx_spi_chip data_flash_chip_info = {
368 .enable_dma = 0, /* use dma transfer with this chip */
370 #endif
372 #if IS_ENABLED(CONFIG_SPI_BFIN5XX)
373 /* SPI (0) */
374 static struct resource bfin_spi0_resource[] = {
375 [0] = {
376 .start = SPI0_REGBASE,
377 .end = SPI0_REGBASE + 0xFF,
378 .flags = IORESOURCE_MEM,
380 [1] = {
381 .start = CH_SPI,
382 .end = CH_SPI,
383 .flags = IORESOURCE_DMA,
385 [2] = {
386 .start = IRQ_SPI,
387 .end = IRQ_SPI,
388 .flags = IORESOURCE_IRQ,
392 /* SPI controller data */
393 static struct bfin5xx_spi_master bfin_spi0_info = {
394 .num_chipselect = 8,
395 .enable_dma = 1, /* master has the ability to do dma transfer */
396 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
399 static struct platform_device bfin_spi0_device = {
400 .name = "bfin-spi",
401 .id = 0, /* Bus number */
402 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
403 .resource = bfin_spi0_resource,
404 .dev = {
405 .platform_data = &bfin_spi0_info, /* Passed to driver */
408 #endif
410 static struct spi_board_info bfin_spi_board_info[] __initdata = {
411 #if IS_ENABLED(CONFIG_SPI_SPIDEV)
413 .modalias = "spidev",
414 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
415 .bus_num = 0,
416 .chip_select = 3,
418 #endif
419 #if IS_ENABLED(CONFIG_MTD_DATAFLASH)
420 { /* DataFlash chip */
421 .modalias = "mtd_dataflash",
422 .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
423 .bus_num = 0, /* Framework bus number */
424 .chip_select = 2, /* Framework chip select */
425 .platform_data = &bfin_spi_dataflash_data,
426 .controller_data = &data_flash_chip_info,
427 .mode = SPI_MODE_3,
429 #endif
432 static struct resource bfin_gpios_resources = {
433 .start = 31,
434 /* .end = MAX_BLACKFIN_GPIOS - 1, */
435 .end = 32,
436 .flags = IORESOURCE_IRQ,
439 static struct platform_device bfin_gpios_device = {
440 .name = "simple-gpio",
441 .id = -1,
442 .num_resources = 1,
443 .resource = &bfin_gpios_resources,
446 static const unsigned int cclk_vlev_datasheet[] = {
447 VRPAIR(VLEV_085, 250000000),
448 VRPAIR(VLEV_090, 300000000),
449 VRPAIR(VLEV_095, 313000000),
450 VRPAIR(VLEV_100, 350000000),
451 VRPAIR(VLEV_105, 400000000),
452 VRPAIR(VLEV_110, 444000000),
453 VRPAIR(VLEV_115, 450000000),
454 VRPAIR(VLEV_120, 475000000),
455 VRPAIR(VLEV_125, 500000000),
456 VRPAIR(VLEV_130, 600000000),
459 static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
460 .tuple_tab = cclk_vlev_datasheet,
461 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
462 .vr_settling_time = 25 /* us */ ,
465 static struct platform_device bfin_dpmc = {
466 .name = "bfin dpmc",
467 .dev = {
468 .platform_data = &bfin_dmpc_vreg_data,
472 static struct platform_device *acvilon_devices[] __initdata = {
473 &bfin_dpmc,
475 #if IS_ENABLED(CONFIG_SPI_BFIN5XX)
476 &bfin_spi0_device,
477 #endif
479 #if IS_ENABLED(CONFIG_SERIAL_BFIN)
480 #ifdef CONFIG_SERIAL_BFIN_UART0
481 &bfin_uart0_device,
482 #endif
483 #endif
485 &bfin_gpios_device,
487 #if IS_ENABLED(CONFIG_SMSC911X)
488 &smsc911x_device,
489 #endif
491 &bfin_i2c_pca_device,
493 #if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
494 &bfin_async_nand_device,
495 #endif
497 #if IS_ENABLED(CONFIG_MTD_PLATRAM)
498 &mtd_ram_device,
499 #endif
503 static int __init acvilon_init(void)
505 int ret;
507 printk(KERN_INFO "%s(): registering device resources\n", __func__);
509 bfin_plat_nand_init();
510 ret =
511 platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices));
512 if (ret < 0)
513 return ret;
515 i2c_register_board_info(0, acvilon_i2c_devs,
516 ARRAY_SIZE(acvilon_i2c_devs));
518 bfin_write_FIO0_FLAG_C(1 << 14);
519 msleep(5);
520 bfin_write_FIO0_FLAG_S(1 << 14);
522 spi_register_board_info(bfin_spi_board_info,
523 ARRAY_SIZE(bfin_spi_board_info));
524 return 0;
527 arch_initcall(acvilon_init);
529 static struct platform_device *acvilon_early_devices[] __initdata = {
530 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
531 #ifdef CONFIG_SERIAL_BFIN_UART0
532 &bfin_uart0_device,
533 #endif
534 #endif
537 void __init native_machine_early_platform_add_devices(void)
539 printk(KERN_INFO "register early platform devices\n");
540 early_platform_add_devices(acvilon_early_devices,
541 ARRAY_SIZE(acvilon_early_devices));