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Merge tag 'locks-v3.16-2' of git://git.samba.org/jlayton/linux
[linux/fpc-iii.git] / arch / blackfin / mach-bf609 / boards / ezkit.c
blob1ba4600de69f72b37ca503f7aab752b9f4dcdb97
1 /*
2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9 #include <linux/device.h>
10 #include <linux/platform_device.h>
11 #include <linux/mtd/mtd.h>
12 #include <linux/mtd/partitions.h>
13 #include <linux/mtd/physmap.h>
14 #include <linux/spi/spi.h>
15 #include <linux/spi/flash.h>
16 #include <linux/irq.h>
17 #include <linux/i2c.h>
18 #include <linux/interrupt.h>
19 #include <linux/usb/musb.h>
20 #include <linux/pinctrl/machine.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include <linux/platform_data/pinctrl-adi2.h>
23 #include <linux/spi/adi_spi3.h>
24 #include <asm/dma.h>
25 #include <asm/gpio.h>
26 #include <asm/nand.h>
27 #include <asm/dpmc.h>
28 #include <asm/portmux.h>
29 #include <asm/bfin_sdh.h>
30 #include <linux/input.h>
31 #include <linux/spi/ad7877.h>
32
33 /*
34 * Name the Board for the /proc/cpuinfo
35 */
36 const char bfin_board_name[] = "ADI BF609-EZKIT";
37
38 /*
39 * Driver needs to know address, irq and flag pin.
40 */
41
42 #if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
43 #include <linux/usb/isp1760.h>
44 static struct resource bfin_isp1760_resources[] = {
45 [0] = {
46 .start = 0x2C0C0000,
47 .end = 0x2C0C0000 + 0xfffff,
48 .flags = IORESOURCE_MEM,
49 },
50 [1] = {
51 .start = IRQ_PG7,
52 .end = IRQ_PG7,
53 .flags = IORESOURCE_IRQ,
54 },
55 };
56
57 static struct isp1760_platform_data isp1760_priv = {
58 .is_isp1761 = 0,
59 .bus_width_16 = 1,
60 .port1_otg = 0,
61 .analog_oc = 0,
62 .dack_polarity_high = 0,
63 .dreq_polarity_high = 0,
64 };
65
66 static struct platform_device bfin_isp1760_device = {
67 .name = "isp1760",
68 .id = 0,
69 .dev = {
70 .platform_data = &isp1760_priv,
71 },
72 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
73 .resource = bfin_isp1760_resources,
74 };
75 #endif
76
77 #if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
78 #include <asm/bfin_rotary.h>
79
80 static struct bfin_rotary_platform_data bfin_rotary_data = {
81 /*.rotary_up_key = KEY_UP,*/
82 /*.rotary_down_key = KEY_DOWN,*/
83 .rotary_rel_code = REL_WHEEL,
84 .rotary_button_key = KEY_ENTER,
85 .debounce = 10, /* 0..17 */
86 .mode = ROT_QUAD_ENC | ROT_DEBE,
87 };
88
89 static struct resource bfin_rotary_resources[] = {
90 {
91 .start = IRQ_CNT,
92 .end = IRQ_CNT,
93 .flags = IORESOURCE_IRQ,
94 },
95 };
96
97 static struct platform_device bfin_rotary_device = {
98 .name = "bfin-rotary",
99 .id = -1,
100 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
101 .resource = bfin_rotary_resources,
102 .dev = {
103 .platform_data = &bfin_rotary_data,
104 },
105 };
106 #endif
107
108 #if IS_ENABLED(CONFIG_STMMAC_ETH)
109 #include <linux/stmmac.h>
110 #include <linux/phy.h>
111
112 static struct stmmac_mdio_bus_data phy_private_data = {
113 .phy_mask = 1,
114 };
115
116 static struct stmmac_dma_cfg eth_dma_cfg = {
117 .pbl = 2,
118 };
119
120 int stmmac_ptp_clk_init(struct platform_device *pdev, void *priv)
121 {
122 bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0);
123 return 0;
124 }
125
126 static struct plat_stmmacenet_data eth_private_data = {
127 .has_gmac = 1,
128 .bus_id = 0,
129 .enh_desc = 1,
130 .phy_addr = 1,
131 .mdio_bus_data = &phy_private_data,
132 .dma_cfg = &eth_dma_cfg,
133 .force_thresh_dma_mode = 1,
134 .interface = PHY_INTERFACE_MODE_RMII,
135 .init = stmmac_ptp_clk_init,
136 };
137
138 static struct platform_device bfin_eth_device = {
139 .name = "stmmaceth",
140 .id = 0,
141 .num_resources = 2,
142 .resource = (struct resource[]) {
143 {
144 .start = EMAC0_MACCFG,
145 .end = EMAC0_MACCFG + 0x1274,
146 .flags = IORESOURCE_MEM,
147 },
148 {
149 .name = "macirq",
150 .start = IRQ_EMAC0_STAT,
151 .end = IRQ_EMAC0_STAT,
152 .flags = IORESOURCE_IRQ,
153 },
154 },
155 .dev = {
156 .power.can_wakeup = 1,
157 .platform_data = &eth_private_data,
158 }
159 };
160 #endif
161
162 #if IS_ENABLED(CONFIG_INPUT_ADXL34X)
163 #include <linux/input/adxl34x.h>
164 static const struct adxl34x_platform_data adxl34x_info = {
165 .x_axis_offset = 0,
166 .y_axis_offset = 0,
167 .z_axis_offset = 0,
168 .tap_threshold = 0x31,
169 .tap_duration = 0x10,
170 .tap_latency = 0x60,
171 .tap_window = 0xF0,
172 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
173 .act_axis_control = 0xFF,
174 .activity_threshold = 5,
175 .inactivity_threshold = 3,
176 .inactivity_time = 4,
177 .free_fall_threshold = 0x7,
178 .free_fall_time = 0x20,
179 .data_rate = 0x8,
180 .data_range = ADXL_FULL_RES,
181
182 .ev_type = EV_ABS,
183 .ev_code_x = ABS_X, /* EV_REL */
184 .ev_code_y = ABS_Y, /* EV_REL */
185 .ev_code_z = ABS_Z, /* EV_REL */
186
187 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
188
189 /* .ev_code_ff = KEY_F,*/ /* EV_KEY */
190 /* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
191 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
192 .fifo_mode = ADXL_FIFO_STREAM,
193 .orientation_enable = ADXL_EN_ORIENTATION_3D,
194 .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
195 .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
196 /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
197 .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
198 };
199 #endif
200
201 #if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
202 static struct platform_device rtc_device = {
203 .name = "rtc-bfin",
204 .id = -1,
205 };
206 #endif
207
208 #if IS_ENABLED(CONFIG_SERIAL_BFIN)
209 #ifdef CONFIG_SERIAL_BFIN_UART0
210 static struct resource bfin_uart0_resources[] = {
211 {
212 .start = UART0_REVID,
213 .end = UART0_RXDIV+4,
214 .flags = IORESOURCE_MEM,
215 },
216 #ifdef CONFIG_EARLY_PRINTK
217 {
218 .start = PORTD_FER,
219 .end = PORTD_FER+2,
220 .flags = IORESOURCE_REG,
221 },
222 {
223 .start = PORTD_MUX,
224 .end = PORTD_MUX+3,
225 .flags = IORESOURCE_REG,
226 },
227 #endif
228 {
229 .start = IRQ_UART0_TX,
230 .end = IRQ_UART0_TX,
231 .flags = IORESOURCE_IRQ,
232 },
233 {
234 .start = IRQ_UART0_RX,
235 .end = IRQ_UART0_RX,
236 .flags = IORESOURCE_IRQ,
237 },
238 {
239 .start = IRQ_UART0_STAT,
240 .end = IRQ_UART0_STAT,
241 .flags = IORESOURCE_IRQ,
242 },
243 {
244 .start = CH_UART0_TX,
245 .end = CH_UART0_TX,
246 .flags = IORESOURCE_DMA,
247 },
248 {
249 .start = CH_UART0_RX,
250 .end = CH_UART0_RX,
251 .flags = IORESOURCE_DMA,
252 },
253 #ifdef CONFIG_BFIN_UART0_CTSRTS
254 { /* CTS pin -- 0 means not supported */
255 .start = GPIO_PD10,
256 .end = GPIO_PD10,
257 .flags = IORESOURCE_IO,
258 },
259 { /* RTS pin -- 0 means not supported */
260 .start = GPIO_PD9,
261 .end = GPIO_PD9,
262 .flags = IORESOURCE_IO,
263 },
264 #endif
265 };
266
267 static unsigned short bfin_uart0_peripherals[] = {
268 P_UART0_TX, P_UART0_RX,
269 #ifdef CONFIG_BFIN_UART0_CTSRTS
270 P_UART0_RTS, P_UART0_CTS,
271 #endif
272 0
273 };
274
275 static struct platform_device bfin_uart0_device = {
276 .name = "bfin-uart",
277 .id = 0,
278 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
279 .resource = bfin_uart0_resources,
280 .dev = {
281 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
282 },
283 };
284 #endif
285 #ifdef CONFIG_SERIAL_BFIN_UART1
286 static struct resource bfin_uart1_resources[] = {
287 {
288 .start = UART1_REVID,
289 .end = UART1_RXDIV+4,
290 .flags = IORESOURCE_MEM,
291 },
292 #ifdef CONFIG_EARLY_PRINTK
293 {
294 .start = PORTG_FER_SET,
295 .end = PORTG_FER_SET+2,
296 .flags = IORESOURCE_REG,
297 },
298 #endif
299 {
300 .start = IRQ_UART1_TX,
301 .end = IRQ_UART1_TX,
302 .flags = IORESOURCE_IRQ,
303 },
304 {
305 .start = IRQ_UART1_RX,
306 .end = IRQ_UART1_RX,
307 .flags = IORESOURCE_IRQ,
308 },
309 {
310 .start = IRQ_UART1_STAT,
311 .end = IRQ_UART1_STAT,
312 .flags = IORESOURCE_IRQ,
313 },
314 {
315 .start = CH_UART1_TX,
316 .end = CH_UART1_TX,
317 .flags = IORESOURCE_DMA,
318 },
319 {
320 .start = CH_UART1_RX,
321 .end = CH_UART1_RX,
322 .flags = IORESOURCE_DMA,
323 },
324 #ifdef CONFIG_BFIN_UART1_CTSRTS
325 { /* CTS pin -- 0 means not supported */
326 .start = GPIO_PG13,
327 .end = GPIO_PG13,
328 .flags = IORESOURCE_IO,
329 },
330 { /* RTS pin -- 0 means not supported */
331 .start = GPIO_PG10,
332 .end = GPIO_PG10,
333 .flags = IORESOURCE_IO,
334 },
335 #endif
336 };
337
338 static unsigned short bfin_uart1_peripherals[] = {
339 P_UART1_TX, P_UART1_RX,
340 #ifdef CONFIG_BFIN_UART1_CTSRTS
341 P_UART1_RTS, P_UART1_CTS,
342 #endif
343 0
344 };
345
346 static struct platform_device bfin_uart1_device = {
347 .name = "bfin-uart",
348 .id = 1,
349 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
350 .resource = bfin_uart1_resources,
351 .dev = {
352 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
353 },
354 };
355 #endif
356 #endif
357
358 #if IS_ENABLED(CONFIG_BFIN_SIR)
359 #ifdef CONFIG_BFIN_SIR0
360 static struct resource bfin_sir0_resources[] = {
361 {
362 .start = 0xFFC00400,
363 .end = 0xFFC004FF,
364 .flags = IORESOURCE_MEM,
365 },
366 {
367 .start = IRQ_UART0_TX,
368 .end = IRQ_UART0_TX+1,
369 .flags = IORESOURCE_IRQ,
370 },
371 {
372 .start = CH_UART0_TX,
373 .end = CH_UART0_TX+1,
374 .flags = IORESOURCE_DMA,
375 },
376 };
377 static struct platform_device bfin_sir0_device = {
378 .name = "bfin_sir",
379 .id = 0,
380 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
381 .resource = bfin_sir0_resources,
382 };
383 #endif
384 #ifdef CONFIG_BFIN_SIR1
385 static struct resource bfin_sir1_resources[] = {
386 {
387 .start = 0xFFC02000,
388 .end = 0xFFC020FF,
389 .flags = IORESOURCE_MEM,
390 },
391 {
392 .start = IRQ_UART1_TX,
393 .end = IRQ_UART1_TX+1,
394 .flags = IORESOURCE_IRQ,
395 },
396 {
397 .start = CH_UART1_TX,
398 .end = CH_UART1_TX+1,
399 .flags = IORESOURCE_DMA,
400 },
401 };
402 static struct platform_device bfin_sir1_device = {
403 .name = "bfin_sir",
404 .id = 1,
405 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
406 .resource = bfin_sir1_resources,
407 };
408 #endif
409 #endif
410
411 #if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
412 static struct resource musb_resources[] = {
413 [0] = {
414 .start = 0xFFCC1000,
415 .end = 0xFFCC1398,
416 .flags = IORESOURCE_MEM,
417 },
418 [1] = { /* general IRQ */
419 .start = IRQ_USB_STAT,
420 .end = IRQ_USB_STAT,
421 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
422 .name = "mc"
423 },
424 [2] = { /* DMA IRQ */
425 .start = IRQ_USB_DMA,
426 .end = IRQ_USB_DMA,
427 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
428 .name = "dma"
429 },
430 };
431
432 static struct musb_hdrc_config musb_config = {
433 .multipoint = 1,
434 .dyn_fifo = 0,
435 .dma = 1,
436 .num_eps = 16,
437 .dma_channels = 8,
438 .clkin = 48, /* musb CLKIN in MHZ */
439 };
440
441 static struct musb_hdrc_platform_data musb_plat = {
442 #if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
443 .mode = MUSB_OTG,
444 #elif defined(CONFIG_USB_MUSB_HDRC)
445 .mode = MUSB_HOST,
446 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
447 .mode = MUSB_PERIPHERAL,
448 #endif
449 .config = &musb_config,
450 };
451
452 static u64 musb_dmamask = ~(u32)0;
453
454 static struct platform_device musb_device = {
455 .name = "musb-blackfin",
456 .id = 0,
457 .dev = {
458 .dma_mask = &musb_dmamask,
459 .coherent_dma_mask = 0xffffffff,
460 .platform_data = &musb_plat,
461 },
462 .num_resources = ARRAY_SIZE(musb_resources),
463 .resource = musb_resources,
464 };
465 #endif
466
467 #if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
468 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
469 static struct resource bfin_sport0_uart_resources[] = {
470 {
471 .start = SPORT0_TCR1,
472 .end = SPORT0_MRCS3+4,
473 .flags = IORESOURCE_MEM,
474 },
475 {
476 .start = IRQ_SPORT0_RX,
477 .end = IRQ_SPORT0_RX+1,
478 .flags = IORESOURCE_IRQ,
479 },
480 {
481 .start = IRQ_SPORT0_ERROR,
482 .end = IRQ_SPORT0_ERROR,
483 .flags = IORESOURCE_IRQ,
484 },
485 };
486
487 static unsigned short bfin_sport0_peripherals[] = {
488 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
489 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
490 };
491
492 static struct platform_device bfin_sport0_uart_device = {
493 .name = "bfin-sport-uart",
494 .id = 0,
495 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
496 .resource = bfin_sport0_uart_resources,
497 .dev = {
498 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
499 },
500 };
501 #endif
502 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
503 static struct resource bfin_sport1_uart_resources[] = {
504 {
505 .start = SPORT1_TCR1,
506 .end = SPORT1_MRCS3+4,
507 .flags = IORESOURCE_MEM,
508 },
509 {
510 .start = IRQ_SPORT1_RX,
511 .end = IRQ_SPORT1_RX+1,
512 .flags = IORESOURCE_IRQ,
513 },
514 {
515 .start = IRQ_SPORT1_ERROR,
516 .end = IRQ_SPORT1_ERROR,
517 .flags = IORESOURCE_IRQ,
518 },
519 };
520
521 static unsigned short bfin_sport1_peripherals[] = {
522 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
523 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
524 };
525
526 static struct platform_device bfin_sport1_uart_device = {
527 .name = "bfin-sport-uart",
528 .id = 1,
529 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
530 .resource = bfin_sport1_uart_resources,
531 .dev = {
532 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
533 },
534 };
535 #endif
536 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
537 static struct resource bfin_sport2_uart_resources[] = {
538 {
539 .start = SPORT2_TCR1,
540 .end = SPORT2_MRCS3+4,
541 .flags = IORESOURCE_MEM,
542 },
543 {
544 .start = IRQ_SPORT2_RX,
545 .end = IRQ_SPORT2_RX+1,
546 .flags = IORESOURCE_IRQ,
547 },
548 {
549 .start = IRQ_SPORT2_ERROR,
550 .end = IRQ_SPORT2_ERROR,
551 .flags = IORESOURCE_IRQ,
552 },
553 };
554
555 static unsigned short bfin_sport2_peripherals[] = {
556 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
557 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
558 };
559
560 static struct platform_device bfin_sport2_uart_device = {
561 .name = "bfin-sport-uart",
562 .id = 2,
563 .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
564 .resource = bfin_sport2_uart_resources,
565 .dev = {
566 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
567 },
568 };
569 #endif
570 #endif
571
572 #if IS_ENABLED(CONFIG_CAN_BFIN)
573
574 static unsigned short bfin_can0_peripherals[] = {
575 P_CAN0_RX, P_CAN0_TX, 0
576 };
577
578 static struct resource bfin_can0_resources[] = {
579 {
580 .start = 0xFFC00A00,
581 .end = 0xFFC00FFF,
582 .flags = IORESOURCE_MEM,
583 },
584 {
585 .start = IRQ_CAN0_RX,
586 .end = IRQ_CAN0_RX,
587 .flags = IORESOURCE_IRQ,
588 },
589 {
590 .start = IRQ_CAN0_TX,
591 .end = IRQ_CAN0_TX,
592 .flags = IORESOURCE_IRQ,
593 },
594 {
595 .start = IRQ_CAN0_STAT,
596 .end = IRQ_CAN0_STAT,
597 .flags = IORESOURCE_IRQ,
598 },
599 };
600
601 static struct platform_device bfin_can0_device = {
602 .name = "bfin_can",
603 .id = 0,
604 .num_resources = ARRAY_SIZE(bfin_can0_resources),
605 .resource = bfin_can0_resources,
606 .dev = {
607 .platform_data = &bfin_can0_peripherals, /* Passed to driver */
608 },
609 };
610
611 #endif
612
613 #if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
614 static struct mtd_partition partition_info[] = {
615 {
616 .name = "bootloader(nand)",
617 .offset = 0,
618 .size = 0x80000,
619 }, {
620 .name = "linux kernel(nand)",
621 .offset = MTDPART_OFS_APPEND,
622 .size = 4 * 1024 * 1024,
623 },
624 {
625 .name = "file system(nand)",
626 .offset = MTDPART_OFS_APPEND,
627 .size = MTDPART_SIZ_FULL,
628 },
629 };
630
631 static struct bf5xx_nand_platform bfin_nand_platform = {
632 .data_width = NFC_NWIDTH_8,
633 .partitions = partition_info,
634 .nr_partitions = ARRAY_SIZE(partition_info),
635 .rd_dly = 3,
636 .wr_dly = 3,
637 };
638
639 static struct resource bfin_nand_resources[] = {
640 {
641 .start = 0xFFC03B00,
642 .end = 0xFFC03B4F,
643 .flags = IORESOURCE_MEM,
644 },
645 {
646 .start = CH_NFC,
647 .end = CH_NFC,
648 .flags = IORESOURCE_IRQ,
649 },
650 };
651
652 static struct platform_device bfin_nand_device = {
653 .name = "bfin-nand",
654 .id = 0,
655 .num_resources = ARRAY_SIZE(bfin_nand_resources),
656 .resource = bfin_nand_resources,
657 .dev = {
658 .platform_data = &bfin_nand_platform,
659 },
660 };
661 #endif
662
663 #if IS_ENABLED(CONFIG_SDH_BFIN)
664
665 static struct bfin_sd_host bfin_sdh_data = {
666 .dma_chan = CH_RSI,
667 .irq_int0 = IRQ_RSI_INT0,
668 .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
669 };
670
671 static struct platform_device bfin_sdh_device = {
672 .name = "bfin-sdh",
673 .id = 0,
674 .dev = {
675 .platform_data = &bfin_sdh_data,
676 },
677 };
678 #endif
679
680 #if IS_ENABLED(CONFIG_MTD_PHYSMAP)
681 static struct mtd_partition ezkit_partitions[] = {
682 {
683 .name = "bootloader(nor)",
684 .size = 0x80000,
685 .offset = 0,
686 }, {
687 .name = "linux kernel(nor)",
688 .size = 0x400000,
689 .offset = MTDPART_OFS_APPEND,
690 }, {
691 .name = "file system(nor)",
692 .size = 0x1000000 - 0x80000 - 0x400000,
693 .offset = MTDPART_OFS_APPEND,
694 },
695 };
696
697 int bf609_nor_flash_init(struct platform_device *pdev)
698 {
699 #define CONFIG_SMC_GCTL_VAL 0x00000010
700
701 if (!devm_pinctrl_get_select_default(&pdev->dev))
702 return -EBUSY;
703 bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
704 bfin_write32(SMC_B0CTL, 0x01002011);
705 bfin_write32(SMC_B0TIM, 0x08170977);
706 bfin_write32(SMC_B0ETIM, 0x00092231);
707 return 0;
708 }
709
710 void bf609_nor_flash_exit(struct platform_device *pdev)
711 {
712 devm_pinctrl_put(pdev->dev.pins->p);
713 bfin_write32(SMC_GCTL, 0);
714 }
715
716 static struct physmap_flash_data ezkit_flash_data = {
717 .width = 2,
718 .parts = ezkit_partitions,
719 .init = bf609_nor_flash_init,
720 .exit = bf609_nor_flash_exit,
721 .nr_parts = ARRAY_SIZE(ezkit_partitions),
722 #ifdef CONFIG_ROMKERNEL
723 .probe_type = "map_rom",
724 #endif
725 };
726
727 static struct resource ezkit_flash_resource = {
728 .start = 0xb0000000,
729 .end = 0xb0ffffff,
730 .flags = IORESOURCE_MEM,
731 };
732
733 static struct platform_device ezkit_flash_device = {
734 .name = "physmap-flash",
735 .id = 0,
736 .dev = {
737 .platform_data = &ezkit_flash_data,
738 },
739 .num_resources = 1,
740 .resource = &ezkit_flash_resource,
741 };
742 #endif
743
744 #if IS_ENABLED(CONFIG_MTD_M25P80)
745 /* SPI flash chip (w25q32) */
746 static struct mtd_partition bfin_spi_flash_partitions[] = {
747 {
748 .name = "bootloader(spi)",
749 .size = 0x00080000,
750 .offset = 0,
751 .mask_flags = MTD_CAP_ROM
752 }, {
753 .name = "linux kernel(spi)",
754 .size = 0x00180000,
755 .offset = MTDPART_OFS_APPEND,
756 }, {
757 .name = "file system(spi)",
758 .size = MTDPART_SIZ_FULL,
759 .offset = MTDPART_OFS_APPEND,
760 }
761 };
762
763 static struct flash_platform_data bfin_spi_flash_data = {
764 .name = "m25p80",
765 .parts = bfin_spi_flash_partitions,
766 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
767 .type = "w25q32",
768 };
769
770 static struct adi_spi3_chip spi_flash_chip_info = {
771 .enable_dma = true, /* use dma transfer with this chip*/
772 };
773 #endif
774
775 #if IS_ENABLED(CONFIG_SPI_SPIDEV)
776 static struct adi_spi3_chip spidev_chip_info = {
777 .enable_dma = true,
778 };
779 #endif
780
781 #if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
782 static struct platform_device bfin_i2s_pcm = {
783 .name = "bfin-i2s-pcm-audio",
784 .id = -1,
785 };
786 #endif
787
788 #if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
789 #include <asm/bfin_sport3.h>
790 static struct resource bfin_snd_resources[] = {
791 {
792 .start = SPORT0_CTL_A,
793 .end = SPORT0_CTL_A,
794 .flags = IORESOURCE_MEM,
795 },
796 {
797 .start = SPORT0_CTL_B,
798 .end = SPORT0_CTL_B,
799 .flags = IORESOURCE_MEM,
800 },
801 {
802 .start = CH_SPORT0_TX,
803 .end = CH_SPORT0_TX,
804 .flags = IORESOURCE_DMA,
805 },
806 {
807 .start = CH_SPORT0_RX,
808 .end = CH_SPORT0_RX,
809 .flags = IORESOURCE_DMA,
810 },
811 {
812 .start = IRQ_SPORT0_TX_STAT,
813 .end = IRQ_SPORT0_TX_STAT,
814 .flags = IORESOURCE_IRQ,
815 },
816 {
817 .start = IRQ_SPORT0_RX_STAT,
818 .end = IRQ_SPORT0_RX_STAT,
819 .flags = IORESOURCE_IRQ,
820 },
821 };
822
823 static const unsigned short bfin_snd_pin[] = {
824 P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
825 P_SPORT0_BFS, P_SPORT0_BD0, 0,
826 };
827
828 static struct bfin_snd_platform_data bfin_snd_data = {
829 .pin_req = bfin_snd_pin,
830 };
831
832 static struct platform_device bfin_i2s = {
833 .name = "bfin-i2s",
834 .num_resources = ARRAY_SIZE(bfin_snd_resources),
835 .resource = bfin_snd_resources,
836 .dev = {
837 .platform_data = &bfin_snd_data,
838 },
839 };
840 #endif
841
842 #if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
843 static const char * const ad1836_link[] = {
844 "bfin-i2s.0",
845 "spi0.76",
846 };
847 static struct platform_device bfin_ad1836_machine = {
848 .name = "bfin-snd-ad1836",
849 .id = -1,
850 .dev = {
851 .platform_data = (void *)ad1836_link,
852 },
853 };
854 #endif
855
856 #if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
857 static struct platform_device adau1761_device = {
858 .name = "bfin-eval-adau1x61",
859 };
860 #endif
861
862 #if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
863 #include <sound/adau17x1.h>
864 static struct adau1761_platform_data adau1761_info = {
865 .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
866 .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
867 };
868 #endif
869
870 #if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
871 #include <linux/videodev2.h>
872 #include <media/blackfin/bfin_capture.h>
873 #include <media/blackfin/ppi.h>
874
875 static const unsigned short ppi_req[] = {
876 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
877 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
878 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
879 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
880 #if !IS_ENABLED(CONFIG_VIDEO_VS6624)
881 P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
882 P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
883 #endif
884 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
885 0,
886 };
887
888 static const struct ppi_info ppi_info = {
889 .type = PPI_TYPE_EPPI3,
890 .dma_ch = CH_EPPI0_CH0,
891 .irq_err = IRQ_EPPI0_STAT,
892 .base = (void __iomem *)EPPI0_STAT,
893 .pin_req = ppi_req,
894 };
895
896 #if IS_ENABLED(CONFIG_VIDEO_VS6624)
897 static struct v4l2_input vs6624_inputs[] = {
898 {
899 .index = 0,
900 .name = "Camera",
901 .type = V4L2_INPUT_TYPE_CAMERA,
902 .std = V4L2_STD_UNKNOWN,
903 },
904 };
905
906 static struct bcap_route vs6624_routes[] = {
907 {
908 .input = 0,
909 .output = 0,
910 },
911 };
912
913 static const unsigned vs6624_ce_pin = GPIO_PE4;
914
915 static struct bfin_capture_config bfin_capture_data = {
916 .card_name = "BF609",
917 .inputs = vs6624_inputs,
918 .num_inputs = ARRAY_SIZE(vs6624_inputs),
919 .routes = vs6624_routes,
920 .i2c_adapter_id = 0,
921 .board_info = {
922 .type = "vs6624",
923 .addr = 0x10,
924 .platform_data = (void *)&vs6624_ce_pin,
925 },
926 .ppi_info = &ppi_info,
927 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
928 | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
929 .blank_pixels = 4,
930 };
931 #endif
932
933 #if IS_ENABLED(CONFIG_VIDEO_ADV7842)
934 #include <media/adv7842.h>
935
936 static struct v4l2_input adv7842_inputs[] = {
937 {
938 .index = 0,
939 .name = "Composite",
940 .type = V4L2_INPUT_TYPE_CAMERA,
941 .std = V4L2_STD_ALL,
942 .capabilities = V4L2_IN_CAP_STD,
943 },
944 {
945 .index = 1,
946 .name = "S-Video",
947 .type = V4L2_INPUT_TYPE_CAMERA,
948 .std = V4L2_STD_ALL,
949 .capabilities = V4L2_IN_CAP_STD,
950 },
951 {
952 .index = 2,
953 .name = "Component",
954 .type = V4L2_INPUT_TYPE_CAMERA,
955 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
956 },
957 {
958 .index = 3,
959 .name = "VGA",
960 .type = V4L2_INPUT_TYPE_CAMERA,
961 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
962 },
963 {
964 .index = 4,
965 .name = "HDMI",
966 .type = V4L2_INPUT_TYPE_CAMERA,
967 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
968 },
969 };
970
971 static struct bcap_route adv7842_routes[] = {
972 {
973 .input = 3,
974 .output = 0,
975 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
976 | EPPI_CTL_ACTIVE656),
977 },
978 {
979 .input = 4,
980 .output = 0,
981 },
982 {
983 .input = 2,
984 .output = 0,
985 },
986 {
987 .input = 1,
988 .output = 0,
989 },
990 {
991 .input = 0,
992 .output = 1,
993 .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
994 | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
995 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
996 },
997 };
998
999 static struct adv7842_output_format adv7842_opf[] = {
1000 {
1001 .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
1002 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
1003 .op_656_range = 1,
1004 .blank_data = 1,
1005 .insert_av_codes = 1,
1006 },
1007 {
1008 .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
1009 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
1010 .op_656_range = 1,
1011 .blank_data = 1,
1012 },
1013 };
1014
1015 static struct adv7842_platform_data adv7842_data = {
1016 .opf = adv7842_opf,
1017 .num_opf = ARRAY_SIZE(adv7842_opf),
1018 .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
1019 .prim_mode = ADV7842_PRIM_MODE_SDP,
1020 .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
1021 .hdmi_free_run_enable = 1,
1022 .sdp_free_run_auto = 1,
1023 .llc_dll_phase = 0x10,
1024 .i2c_sdp_io = 0x40,
1025 .i2c_sdp = 0x41,
1026 .i2c_cp = 0x42,
1027 .i2c_vdp = 0x43,
1028 .i2c_afe = 0x44,
1029 .i2c_hdmi = 0x45,
1030 .i2c_repeater = 0x46,
1031 .i2c_edid = 0x47,
1032 .i2c_infoframe = 0x48,
1033 .i2c_cec = 0x49,
1034 .i2c_avlink = 0x4a,
1035 .i2c_ex = 0x26,
1036 };
1037
1038 static struct bfin_capture_config bfin_capture_data = {
1039 .card_name = "BF609",
1040 .inputs = adv7842_inputs,
1041 .num_inputs = ARRAY_SIZE(adv7842_inputs),
1042 .routes = adv7842_routes,
1043 .i2c_adapter_id = 0,
1044 .board_info = {
1045 .type = "adv7842",
1046 .addr = 0x20,
1047 .platform_data = (void *)&adv7842_data,
1048 },
1049 .ppi_info = &ppi_info,
1050 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
1051 | EPPI_CTL_ACTIVE656),
1052 };
1053 #endif
1054
1055 static struct platform_device bfin_capture_device = {
1056 .name = "bfin_capture",
1057 .dev = {
1058 .platform_data = &bfin_capture_data,
1059 },
1060 };
1061 #endif
1062
1063 #if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
1064 #include <linux/videodev2.h>
1065 #include <media/blackfin/bfin_display.h>
1066 #include <media/blackfin/ppi.h>
1067
1068 static const unsigned short ppi_req_disp[] = {
1069 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
1070 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
1071 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
1072 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
1073 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
1074 0,
1075 };
1076
1077 static const struct ppi_info ppi_info = {
1078 .type = PPI_TYPE_EPPI3,
1079 .dma_ch = CH_EPPI0_CH0,
1080 .irq_err = IRQ_EPPI0_STAT,
1081 .base = (void __iomem *)EPPI0_STAT,
1082 .pin_req = ppi_req_disp,
1083 };
1084
1085 #if IS_ENABLED(CONFIG_VIDEO_ADV7511)
1086 #include <media/adv7511.h>
1087
1088 static struct v4l2_output adv7511_outputs[] = {
1089 {
1090 .index = 0,
1091 .name = "HDMI",
1092 .type = V4L2_INPUT_TYPE_CAMERA,
1093 .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
1094 },
1095 };
1096
1097 static struct disp_route adv7511_routes[] = {
1098 {
1099 .output = 0,
1100 },
1101 };
1102
1103 static struct adv7511_platform_data adv7511_data = {
1104 .edid_addr = 0x7e,
1105 .i2c_ex = 0x25,
1106 };
1107
1108 static struct bfin_display_config bfin_display_data = {
1109 .card_name = "BF609",
1110 .outputs = adv7511_outputs,
1111 .num_outputs = ARRAY_SIZE(adv7511_outputs),
1112 .routes = adv7511_routes,
1113 .i2c_adapter_id = 0,
1114 .board_info = {
1115 .type = "adv7511",
1116 .addr = 0x39,
1117 .platform_data = (void *)&adv7511_data,
1118 },
1119 .ppi_info = &ppi_info,
1120 .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
1121 | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
1122 | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
1123 | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1124 };
1125 #endif
1126
1127 #if IS_ENABLED(CONFIG_VIDEO_ADV7343)
1128 #include <media/adv7343.h>
1129
1130 static struct v4l2_output adv7343_outputs[] = {
1131 {
1132 .index = 0,
1133 .name = "Composite",
1134 .type = V4L2_OUTPUT_TYPE_ANALOG,
1135 .std = V4L2_STD_ALL,
1136 .capabilities = V4L2_OUT_CAP_STD,
1137 },
1138 {
1139 .index = 1,
1140 .name = "S-Video",
1141 .type = V4L2_OUTPUT_TYPE_ANALOG,
1142 .std = V4L2_STD_ALL,
1143 .capabilities = V4L2_OUT_CAP_STD,
1144 },
1145 {
1146 .index = 2,
1147 .name = "Component",
1148 .type = V4L2_OUTPUT_TYPE_ANALOG,
1149 .std = V4L2_STD_ALL,
1150 .capabilities = V4L2_OUT_CAP_STD,
1151 },
1152
1153 };
1154
1155 static struct disp_route adv7343_routes[] = {
1156 {
1157 .output = ADV7343_COMPOSITE_ID,
1158 },
1159 {
1160 .output = ADV7343_SVIDEO_ID,
1161 },
1162 {
1163 .output = ADV7343_COMPONENT_ID,
1164 },
1165 };
1166
1167 static struct adv7343_platform_data adv7343_data = {
1168 .mode_config = {
1169 .sleep_mode = false,
1170 .pll_control = false,
1171 .dac_1 = true,
1172 .dac_2 = true,
1173 .dac_3 = true,
1174 .dac_4 = true,
1175 .dac_5 = true,
1176 .dac_6 = true,
1177 },
1178 .sd_config = {
1179 .sd_dac_out1 = false,
1180 .sd_dac_out2 = false,
1181 },
1182 };
1183
1184 static struct bfin_display_config bfin_display_data = {
1185 .card_name = "BF609",
1186 .outputs = adv7343_outputs,
1187 .num_outputs = ARRAY_SIZE(adv7343_outputs),
1188 .routes = adv7343_routes,
1189 .i2c_adapter_id = 0,
1190 .board_info = {
1191 .type = "adv7343",
1192 .addr = 0x2b,
1193 .platform_data = (void *)&adv7343_data,
1194 },
1195 .ppi_info = &ppi_info_disp,
1196 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO
1197 | EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2
1198 | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1199 };
1200 #endif
1201
1202 static struct platform_device bfin_display_device = {
1203 .name = "bfin_display",
1204 .dev = {
1205 .platform_data = &bfin_display_data,
1206 },
1207 };
1208 #endif
1209
1210 #if defined(CONFIG_BFIN_CRC)
1211 #define BFIN_CRC_NAME "bfin-crc"
1212
1213 static struct resource bfin_crc0_resources[] = {
1214 {
1215 .start = REG_CRC0_CTL,
1216 .end = REG_CRC0_REVID+4,
1217 .flags = IORESOURCE_MEM,
1218 },
1219 {
1220 .start = IRQ_CRC0_DCNTEXP,
1221 .end = IRQ_CRC0_DCNTEXP,
1222 .flags = IORESOURCE_IRQ,
1223 },
1224 {
1225 .start = CH_MEM_STREAM0_SRC_CRC0,
1226 .end = CH_MEM_STREAM0_SRC_CRC0,
1227 .flags = IORESOURCE_DMA,
1228 },
1229 {
1230 .start = CH_MEM_STREAM0_DEST_CRC0,
1231 .end = CH_MEM_STREAM0_DEST_CRC0,
1232 .flags = IORESOURCE_DMA,
1233 },
1234 };
1235
1236 static struct platform_device bfin_crc0_device = {
1237 .name = BFIN_CRC_NAME,
1238 .id = 0,
1239 .num_resources = ARRAY_SIZE(bfin_crc0_resources),
1240 .resource = bfin_crc0_resources,
1241 };
1242
1243 static struct resource bfin_crc1_resources[] = {
1244 {
1245 .start = REG_CRC1_CTL,
1246 .end = REG_CRC1_REVID+4,
1247 .flags = IORESOURCE_MEM,
1248 },
1249 {
1250 .start = IRQ_CRC1_DCNTEXP,
1251 .end = IRQ_CRC1_DCNTEXP,
1252 .flags = IORESOURCE_IRQ,
1253 },
1254 {
1255 .start = CH_MEM_STREAM1_SRC_CRC1,
1256 .end = CH_MEM_STREAM1_SRC_CRC1,
1257 .flags = IORESOURCE_DMA,
1258 },
1259 {
1260 .start = CH_MEM_STREAM1_DEST_CRC1,
1261 .end = CH_MEM_STREAM1_DEST_CRC1,
1262 .flags = IORESOURCE_DMA,
1263 },
1264 };
1265
1266 static struct platform_device bfin_crc1_device = {
1267 .name = BFIN_CRC_NAME,
1268 .id = 1,
1269 .num_resources = ARRAY_SIZE(bfin_crc1_resources),
1270 .resource = bfin_crc1_resources,
1271 };
1272 #endif
1273
1274 #if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
1275 #define BFIN_CRYPTO_CRC_NAME "bfin-hmac-crc"
1276 #define BFIN_CRYPTO_CRC_POLY_DATA 0x5c5c5c5c
1277
1278 static struct resource bfin_crypto_crc_resources[] = {
1279 {
1280 .start = REG_CRC0_CTL,
1281 .end = REG_CRC0_REVID+4,
1282 .flags = IORESOURCE_MEM,
1283 },
1284 {
1285 .start = IRQ_CRC0_DCNTEXP,
1286 .end = IRQ_CRC0_DCNTEXP,
1287 .flags = IORESOURCE_IRQ,
1288 },
1289 {
1290 .start = CH_MEM_STREAM0_SRC_CRC0,
1291 .end = CH_MEM_STREAM0_SRC_CRC0,
1292 .flags = IORESOURCE_DMA,
1293 },
1294 };
1295
1296 static struct platform_device bfin_crypto_crc_device = {
1297 .name = BFIN_CRYPTO_CRC_NAME,
1298 .id = 0,
1299 .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
1300 .resource = bfin_crypto_crc_resources,
1301 .dev = {
1302 .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
1303 },
1304 };
1305 #endif
1306
1307 #if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
1308 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1309 .model = 7877,
1310 .vref_delay_usecs = 50, /* internal, no capacitor */
1311 .x_plate_ohms = 419,
1312 .y_plate_ohms = 486,
1313 .pressure_max = 1000,
1314 .pressure_min = 0,
1315 .stopacq_polarity = 1,
1316 .first_conversion_delay = 3,
1317 .acquisition_time = 1,
1318 .averaging = 1,
1319 .pen_down_acc_interval = 1,
1320 };
1321 #endif
1322
1323 #ifdef CONFIG_PINCTRL_ADI2
1324
1325 # define ADI_PINT_DEVNAME "adi-gpio-pint"
1326 # define ADI_GPIO_DEVNAME "adi-gpio"
1327 # define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
1328
1329 static struct platform_device bfin_pinctrl_device = {
1330 .name = ADI_PINCTRL_DEVNAME,
1331 .id = 0,
1332 };
1333
1334 static struct resource bfin_pint0_resources[] = {
1335 {
1336 .start = PINT0_MASK_SET,
1337 .end = PINT0_LATCH + 3,
1338 .flags = IORESOURCE_MEM,
1339 },
1340 {
1341 .start = IRQ_PINT0,
1342 .end = IRQ_PINT0,
1343 .flags = IORESOURCE_IRQ,
1344 },
1345 };
1346
1347 static struct platform_device bfin_pint0_device = {
1348 .name = ADI_PINT_DEVNAME,
1349 .id = 0,
1350 .num_resources = ARRAY_SIZE(bfin_pint0_resources),
1351 .resource = bfin_pint0_resources,
1352 };
1353
1354 static struct resource bfin_pint1_resources[] = {
1355 {
1356 .start = PINT1_MASK_SET,
1357 .end = PINT1_LATCH + 3,
1358 .flags = IORESOURCE_MEM,
1359 },
1360 {
1361 .start = IRQ_PINT1,
1362 .end = IRQ_PINT1,
1363 .flags = IORESOURCE_IRQ,
1364 },
1365 };
1366
1367 static struct platform_device bfin_pint1_device = {
1368 .name = ADI_PINT_DEVNAME,
1369 .id = 1,
1370 .num_resources = ARRAY_SIZE(bfin_pint1_resources),
1371 .resource = bfin_pint1_resources,
1372 };
1373
1374 static struct resource bfin_pint2_resources[] = {
1375 {
1376 .start = PINT2_MASK_SET,
1377 .end = PINT2_LATCH + 3,
1378 .flags = IORESOURCE_MEM,
1379 },
1380 {
1381 .start = IRQ_PINT2,
1382 .end = IRQ_PINT2,
1383 .flags = IORESOURCE_IRQ,
1384 },
1385 };
1386
1387 static struct platform_device bfin_pint2_device = {
1388 .name = ADI_PINT_DEVNAME,
1389 .id = 2,
1390 .num_resources = ARRAY_SIZE(bfin_pint2_resources),
1391 .resource = bfin_pint2_resources,
1392 };
1393
1394 static struct resource bfin_pint3_resources[] = {
1395 {
1396 .start = PINT3_MASK_SET,
1397 .end = PINT3_LATCH + 3,
1398 .flags = IORESOURCE_MEM,
1399 },
1400 {
1401 .start = IRQ_PINT3,
1402 .end = IRQ_PINT3,
1403 .flags = IORESOURCE_IRQ,
1404 },
1405 };
1406
1407 static struct platform_device bfin_pint3_device = {
1408 .name = ADI_PINT_DEVNAME,
1409 .id = 3,
1410 .num_resources = ARRAY_SIZE(bfin_pint3_resources),
1411 .resource = bfin_pint3_resources,
1412 };
1413
1414 static struct resource bfin_pint4_resources[] = {
1415 {
1416 .start = PINT4_MASK_SET,
1417 .end = PINT4_LATCH + 3,
1418 .flags = IORESOURCE_MEM,
1419 },
1420 {
1421 .start = IRQ_PINT4,
1422 .end = IRQ_PINT4,
1423 .flags = IORESOURCE_IRQ,
1424 },
1425 };
1426
1427 static struct platform_device bfin_pint4_device = {
1428 .name = ADI_PINT_DEVNAME,
1429 .id = 4,
1430 .num_resources = ARRAY_SIZE(bfin_pint4_resources),
1431 .resource = bfin_pint4_resources,
1432 };
1433
1434 static struct resource bfin_pint5_resources[] = {
1435 {
1436 .start = PINT5_MASK_SET,
1437 .end = PINT5_LATCH + 3,
1438 .flags = IORESOURCE_MEM,
1439 },
1440 {
1441 .start = IRQ_PINT5,
1442 .end = IRQ_PINT5,
1443 .flags = IORESOURCE_IRQ,
1444 },
1445 };
1446
1447 static struct platform_device bfin_pint5_device = {
1448 .name = ADI_PINT_DEVNAME,
1449 .id = 5,
1450 .num_resources = ARRAY_SIZE(bfin_pint5_resources),
1451 .resource = bfin_pint5_resources,
1452 };
1453
1454 static struct resource bfin_gpa_resources[] = {
1455 {
1456 .start = PORTA_FER,
1457 .end = PORTA_MUX + 3,
1458 .flags = IORESOURCE_MEM,
1459 },
1460 { /* optional */
1461 .start = IRQ_PA0,
1462 .end = IRQ_PA0,
1463 .flags = IORESOURCE_IRQ,
1464 },
1465 };
1466
1467 static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
1468 .port_pin_base = GPIO_PA0,
1469 .port_width = GPIO_BANKSIZE,
1470 .pint_id = 0, /* PINT0 */
1471 .pint_assign = true, /* PINT upper 16 bit */
1472 .pint_map = 0, /* mapping mask in PINT */
1473 };
1474
1475 static struct platform_device bfin_gpa_device = {
1476 .name = ADI_GPIO_DEVNAME,
1477 .id = 0,
1478 .num_resources = ARRAY_SIZE(bfin_gpa_resources),
1479 .resource = bfin_gpa_resources,
1480 .dev = {
1481 .platform_data = &bfin_gpa_pdata, /* Passed to driver */
1482 },
1483 };
1484
1485 static struct resource bfin_gpb_resources[] = {
1486 {
1487 .start = PORTB_FER,
1488 .end = PORTB_MUX + 3,
1489 .flags = IORESOURCE_MEM,
1490 },
1491 {
1492 .start = IRQ_PB0,
1493 .end = IRQ_PB0,
1494 .flags = IORESOURCE_IRQ,
1495 },
1496 };
1497
1498 static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
1499 .port_pin_base = GPIO_PB0,
1500 .port_width = GPIO_BANKSIZE,
1501 .pint_id = 0,
1502 .pint_assign = false,
1503 .pint_map = 1,
1504 };
1505
1506 static struct platform_device bfin_gpb_device = {
1507 .name = ADI_GPIO_DEVNAME,
1508 .id = 1,
1509 .num_resources = ARRAY_SIZE(bfin_gpb_resources),
1510 .resource = bfin_gpb_resources,
1511 .dev = {
1512 .platform_data = &bfin_gpb_pdata, /* Passed to driver */
1513 },
1514 };
1515
1516 static struct resource bfin_gpc_resources[] = {
1517 {
1518 .start = PORTC_FER,
1519 .end = PORTC_MUX + 3,
1520 .flags = IORESOURCE_MEM,
1521 },
1522 {
1523 .start = IRQ_PC0,
1524 .end = IRQ_PC0,
1525 .flags = IORESOURCE_IRQ,
1526 },
1527 };
1528
1529 static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
1530 .port_pin_base = GPIO_PC0,
1531 .port_width = GPIO_BANKSIZE,
1532 .pint_id = 1,
1533 .pint_assign = false,
1534 .pint_map = 1,
1535 };
1536
1537 static struct platform_device bfin_gpc_device = {
1538 .name = ADI_GPIO_DEVNAME,
1539 .id = 2,
1540 .num_resources = ARRAY_SIZE(bfin_gpc_resources),
1541 .resource = bfin_gpc_resources,
1542 .dev = {
1543 .platform_data = &bfin_gpc_pdata, /* Passed to driver */
1544 },
1545 };
1546
1547 static struct resource bfin_gpd_resources[] = {
1548 {
1549 .start = PORTD_FER,
1550 .end = PORTD_MUX + 3,
1551 .flags = IORESOURCE_MEM,
1552 },
1553 {
1554 .start = IRQ_PD0,
1555 .end = IRQ_PD0,
1556 .flags = IORESOURCE_IRQ,
1557 },
1558 };
1559
1560 static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
1561 .port_pin_base = GPIO_PD0,
1562 .port_width = GPIO_BANKSIZE,
1563 .pint_id = 2,
1564 .pint_assign = false,
1565 .pint_map = 1,
1566 };
1567
1568 static struct platform_device bfin_gpd_device = {
1569 .name = ADI_GPIO_DEVNAME,
1570 .id = 3,
1571 .num_resources = ARRAY_SIZE(bfin_gpd_resources),
1572 .resource = bfin_gpd_resources,
1573 .dev = {
1574 .platform_data = &bfin_gpd_pdata, /* Passed to driver */
1575 },
1576 };
1577
1578 static struct resource bfin_gpe_resources[] = {
1579 {
1580 .start = PORTE_FER,
1581 .end = PORTE_MUX + 3,
1582 .flags = IORESOURCE_MEM,
1583 },
1584 {
1585 .start = IRQ_PE0,
1586 .end = IRQ_PE0,
1587 .flags = IORESOURCE_IRQ,
1588 },
1589 };
1590
1591 static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
1592 .port_pin_base = GPIO_PE0,
1593 .port_width = GPIO_BANKSIZE,
1594 .pint_id = 3,
1595 .pint_assign = false,
1596 .pint_map = 1,
1597 };
1598
1599 static struct platform_device bfin_gpe_device = {
1600 .name = ADI_GPIO_DEVNAME,
1601 .id = 4,
1602 .num_resources = ARRAY_SIZE(bfin_gpe_resources),
1603 .resource = bfin_gpe_resources,
1604 .dev = {
1605 .platform_data = &bfin_gpe_pdata, /* Passed to driver */
1606 },
1607 };
1608
1609 static struct resource bfin_gpf_resources[] = {
1610 {
1611 .start = PORTF_FER,
1612 .end = PORTF_MUX + 3,
1613 .flags = IORESOURCE_MEM,
1614 },
1615 {
1616 .start = IRQ_PF0,
1617 .end = IRQ_PF0,
1618 .flags = IORESOURCE_IRQ,
1619 },
1620 };
1621
1622 static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
1623 .port_pin_base = GPIO_PF0,
1624 .port_width = GPIO_BANKSIZE,
1625 .pint_id = 4,
1626 .pint_assign = false,
1627 .pint_map = 1,
1628 };
1629
1630 static struct platform_device bfin_gpf_device = {
1631 .name = ADI_GPIO_DEVNAME,
1632 .id = 5,
1633 .num_resources = ARRAY_SIZE(bfin_gpf_resources),
1634 .resource = bfin_gpf_resources,
1635 .dev = {
1636 .platform_data = &bfin_gpf_pdata, /* Passed to driver */
1637 },
1638 };
1639
1640 static struct resource bfin_gpg_resources[] = {
1641 {
1642 .start = PORTG_FER,
1643 .end = PORTG_MUX + 3,
1644 .flags = IORESOURCE_MEM,
1645 },
1646 {
1647 .start = IRQ_PG0,
1648 .end = IRQ_PG0,
1649 .flags = IORESOURCE_IRQ,
1650 },
1651 };
1652
1653 static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
1654 .port_pin_base = GPIO_PG0,
1655 .port_width = GPIO_BANKSIZE,
1656 .pint_id = 5,
1657 .pint_assign = false,
1658 .pint_map = 1,
1659 };
1660
1661 static struct platform_device bfin_gpg_device = {
1662 .name = ADI_GPIO_DEVNAME,
1663 .id = 6,
1664 .num_resources = ARRAY_SIZE(bfin_gpg_resources),
1665 .resource = bfin_gpg_resources,
1666 .dev = {
1667 .platform_data = &bfin_gpg_pdata, /* Passed to driver */
1668 },
1669 };
1670
1671 #endif
1672
1673 #if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
1674 #include <linux/input.h>
1675 #include <linux/gpio_keys.h>
1676
1677 static struct gpio_keys_button bfin_gpio_keys_table[] = {
1678 {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
1679 {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
1680 };
1681
1682 static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1683 .buttons = bfin_gpio_keys_table,
1684 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
1685 };
1686
1687 static struct platform_device bfin_device_gpiokeys = {
1688 .name = "gpio-keys",
1689 .dev = {
1690 .platform_data = &bfin_gpio_keys_data,
1691 },
1692 };
1693 #endif
1694
1695 static struct spi_board_info bfin_spi_board_info[] __initdata = {
1696 #if IS_ENABLED(CONFIG_MTD_M25P80)
1697 {
1698 /* the modalias must be the same as spi device driver name */
1699 .modalias = "m25p80", /* Name of spi_driver for this device */
1700 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
1701 .bus_num = 0, /* Framework bus number */
1702 .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
1703 .platform_data = &bfin_spi_flash_data,
1704 .controller_data = &spi_flash_chip_info,
1705 .mode = SPI_MODE_3,
1706 },
1707 #endif
1708 #if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
1709 {
1710 .modalias = "ad7877",
1711 .platform_data = &bfin_ad7877_ts_info,
1712 .irq = IRQ_PD9,
1713 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
1714 .bus_num = 0,
1715 .chip_select = MAX_CTRL_CS + GPIO_PC15, /* SPI_SSEL4 */
1716 },
1717 #endif
1718 #if IS_ENABLED(CONFIG_SPI_SPIDEV)
1719 {
1720 .modalias = "spidev",
1721 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1722 .bus_num = 0,
1723 .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
1724 .controller_data = &spidev_chip_info,
1725 },
1726 #endif
1727 #if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
1728 {
1729 .modalias = "adxl34x",
1730 .platform_data = &adxl34x_info,
1731 .irq = IRQ_PC5,
1732 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1733 .bus_num = 1,
1734 .chip_select = 2,
1735 .mode = SPI_MODE_3,
1736 },
1737 #endif
1738 };
1739 #if IS_ENABLED(CONFIG_SPI_ADI_V3)
1740 /* SPI (0) */
1741 static struct resource bfin_spi0_resource[] = {
1742 {
1743 .start = SPI0_REGBASE,
1744 .end = SPI0_REGBASE + 0xFF,
1745 .flags = IORESOURCE_MEM,
1746 },
1747 {
1748 .start = CH_SPI0_TX,
1749 .end = CH_SPI0_TX,
1750 .flags = IORESOURCE_DMA,
1751 },
1752 {
1753 .start = CH_SPI0_RX,
1754 .end = CH_SPI0_RX,
1755 .flags = IORESOURCE_DMA,
1756 },
1757 };
1758
1759 /* SPI (1) */
1760 static struct resource bfin_spi1_resource[] = {
1761 {
1762 .start = SPI1_REGBASE,
1763 .end = SPI1_REGBASE + 0xFF,
1764 .flags = IORESOURCE_MEM,
1765 },
1766 {
1767 .start = CH_SPI1_TX,
1768 .end = CH_SPI1_TX,
1769 .flags = IORESOURCE_DMA,
1770 },
1771 {
1772 .start = CH_SPI1_RX,
1773 .end = CH_SPI1_RX,
1774 .flags = IORESOURCE_DMA,
1775 },
1776
1777 };
1778
1779 /* SPI controller data */
1780 static struct adi_spi3_master bf60x_spi_master_info0 = {
1781 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1782 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1783 };
1784
1785 static struct platform_device bf60x_spi_master0 = {
1786 .name = "adi-spi3",
1787 .id = 0, /* Bus number */
1788 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1789 .resource = bfin_spi0_resource,
1790 .dev = {
1791 .platform_data = &bf60x_spi_master_info0, /* Passed to driver */
1792 },
1793 };
1794
1795 static struct adi_spi3_master bf60x_spi_master_info1 = {
1796 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1797 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1798 };
1799
1800 static struct platform_device bf60x_spi_master1 = {
1801 .name = "adi-spi3",
1802 .id = 1, /* Bus number */
1803 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
1804 .resource = bfin_spi1_resource,
1805 .dev = {
1806 .platform_data = &bf60x_spi_master_info1, /* Passed to driver */
1807 },
1808 };
1809 #endif /* spi master and devices */
1810
1811 #if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
1812 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
1813
1814 static struct resource bfin_twi0_resource[] = {
1815 [0] = {
1816 .start = TWI0_CLKDIV,
1817 .end = TWI0_CLKDIV + 0xFF,
1818 .flags = IORESOURCE_MEM,
1819 },
1820 [1] = {
1821 .start = IRQ_TWI0,
1822 .end = IRQ_TWI0,
1823 .flags = IORESOURCE_IRQ,
1824 },
1825 };
1826
1827 static struct platform_device i2c_bfin_twi0_device = {
1828 .name = "i2c-bfin-twi",
1829 .id = 0,
1830 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1831 .resource = bfin_twi0_resource,
1832 .dev = {
1833 .platform_data = &bfin_twi0_pins,
1834 },
1835 };
1836
1837 static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
1838
1839 static struct resource bfin_twi1_resource[] = {
1840 [0] = {
1841 .start = TWI1_CLKDIV,
1842 .end = TWI1_CLKDIV + 0xFF,
1843 .flags = IORESOURCE_MEM,
1844 },
1845 [1] = {
1846 .start = IRQ_TWI1,
1847 .end = IRQ_TWI1,
1848 .flags = IORESOURCE_IRQ,
1849 },
1850 };
1851
1852 static struct platform_device i2c_bfin_twi1_device = {
1853 .name = "i2c-bfin-twi",
1854 .id = 1,
1855 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1856 .resource = bfin_twi1_resource,
1857 .dev = {
1858 .platform_data = &bfin_twi1_pins,
1859 },
1860 };
1861 #endif
1862
1863 static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
1864 #if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
1865 {
1866 I2C_BOARD_INFO("adxl34x", 0x53),
1867 .irq = IRQ_PC5,
1868 .platform_data = (void *)&adxl34x_info,
1869 },
1870 #endif
1871 #if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
1872 {
1873 I2C_BOARD_INFO("adau1761", 0x38),
1874 .platform_data = (void *)&adau1761_info
1875 },
1876 #endif
1877 #if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
1878 {
1879 I2C_BOARD_INFO("ssm2602", 0x1b),
1880 },
1881 #endif
1882 };
1883
1884 static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
1885 };
1886
1887 static const unsigned int cclk_vlev_datasheet[] =
1888 {
1889 /*
1890 * Internal VLEV BF54XSBBC1533
1891 ****temporarily using these values until data sheet is updated
1892 */
1893 VRPAIR(VLEV_085, 150000000),
1894 VRPAIR(VLEV_090, 250000000),
1895 VRPAIR(VLEV_110, 276000000),
1896 VRPAIR(VLEV_115, 301000000),
1897 VRPAIR(VLEV_120, 525000000),
1898 VRPAIR(VLEV_125, 550000000),
1899 VRPAIR(VLEV_130, 600000000),
1900 };
1901
1902 static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1903 .tuple_tab = cclk_vlev_datasheet,
1904 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1905 .vr_settling_time = 25 /* us */,
1906 };
1907
1908 static struct platform_device bfin_dpmc = {
1909 .name = "bfin dpmc",
1910 .dev = {
1911 .platform_data = &bfin_dmpc_vreg_data,
1912 },
1913 };
1914
1915 static struct platform_device *ezkit_devices[] __initdata = {
1916
1917 &bfin_dpmc,
1918 #if defined(CONFIG_PINCTRL_ADI2)
1919 &bfin_pinctrl_device,
1920 &bfin_pint0_device,
1921 &bfin_pint1_device,
1922 &bfin_pint2_device,
1923 &bfin_pint3_device,
1924 &bfin_pint4_device,
1925 &bfin_pint5_device,
1926 &bfin_gpa_device,
1927 &bfin_gpb_device,
1928 &bfin_gpc_device,
1929 &bfin_gpd_device,
1930 &bfin_gpe_device,
1931 &bfin_gpf_device,
1932 &bfin_gpg_device,
1933 #endif
1934
1935 #if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
1936 &rtc_device,
1937 #endif
1938
1939 #if IS_ENABLED(CONFIG_SERIAL_BFIN)
1940 #ifdef CONFIG_SERIAL_BFIN_UART0
1941 &bfin_uart0_device,
1942 #endif
1943 #ifdef CONFIG_SERIAL_BFIN_UART1
1944 &bfin_uart1_device,
1945 #endif
1946 #endif
1947
1948 #if IS_ENABLED(CONFIG_BFIN_SIR)
1949 #ifdef CONFIG_BFIN_SIR0
1950 &bfin_sir0_device,
1951 #endif
1952 #ifdef CONFIG_BFIN_SIR1
1953 &bfin_sir1_device,
1954 #endif
1955 #endif
1956
1957 #if IS_ENABLED(CONFIG_STMMAC_ETH)
1958 &bfin_eth_device,
1959 #endif
1960
1961 #if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
1962 &musb_device,
1963 #endif
1964
1965 #if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
1966 &bfin_isp1760_device,
1967 #endif
1968
1969 #if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
1970 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1971 &bfin_sport0_uart_device,
1972 #endif
1973 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1974 &bfin_sport1_uart_device,
1975 #endif
1976 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1977 &bfin_sport2_uart_device,
1978 #endif
1979 #endif
1980
1981 #if IS_ENABLED(CONFIG_CAN_BFIN)
1982 &bfin_can0_device,
1983 #endif
1984
1985 #if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
1986 &bfin_nand_device,
1987 #endif
1988
1989 #if IS_ENABLED(CONFIG_SDH_BFIN)
1990 &bfin_sdh_device,
1991 #endif
1992
1993 #if IS_ENABLED(CONFIG_SPI_ADI_V3)
1994 &bf60x_spi_master0,
1995 &bf60x_spi_master1,
1996 #endif
1997
1998 #if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
1999 &bfin_rotary_device,
2000 #endif
2001
2002 #if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
2003 &i2c_bfin_twi0_device,
2004 #if !defined(CONFIG_BF542)
2005 &i2c_bfin_twi1_device,
2006 #endif
2007 #endif
2008
2009 #if defined(CONFIG_BFIN_CRC)
2010 &bfin_crc0_device,
2011 &bfin_crc1_device,
2012 #endif
2013 #if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
2014 &bfin_crypto_crc_device,
2015 #endif
2016
2017 #if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
2018 &bfin_device_gpiokeys,
2019 #endif
2020
2021 #if IS_ENABLED(CONFIG_MTD_PHYSMAP)
2022 &ezkit_flash_device,
2023 #endif
2024 #if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
2025 &bfin_i2s_pcm,
2026 #endif
2027 #if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
2028 &bfin_i2s,
2029 #endif
2030 #if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
2031 &bfin_ad1836_machine,
2032 #endif
2033 #if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
2034 &adau1761_device,
2035 #endif
2036 #if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
2037 &bfin_capture_device,
2038 #endif
2039 #if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
2040 &bfin_display_device,
2041 #endif
2042
2043 };
2044
2045 /* Pin control settings */
2046 static struct pinctrl_map __initdata bfin_pinmux_map[] = {
2047 /* per-device maps */
2048 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
2049 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
2050 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
2051 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
2052 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
2053 PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"),
2054 PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.0", "pinctrl-adi2.0", NULL, "spi0"),
2055 PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.1", "pinctrl-adi2.0", NULL, "spi1"),
2056 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
2057 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
2058 PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
2059 PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
2060 PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0", "pinctrl-adi2.0", NULL, "smc0"),
2061 PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.2", "pinctrl-adi2.0", NULL, "ppi2_16b"),
2062 PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
2063 #if IS_ENABLED(CONFIG_VIDEO_MT9M114)
2064 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_8b"),
2065 #elif IS_ENABLED(CONFIG_VIDEO_VS6624)
2066 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
2067 #else
2068 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_24b"),
2069 #endif
2070 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
2071 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
2072 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
2073 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
2074 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
2075 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
2076 };
2077
2078 static int __init ezkit_init(void)
2079 {
2080 printk(KERN_INFO "%s(): registering device resources\n", __func__);
2081
2082 /* Initialize pinmuxing */
2083 pinctrl_register_mappings(bfin_pinmux_map,
2084 ARRAY_SIZE(bfin_pinmux_map));
2085
2086 i2c_register_board_info(0, bfin_i2c_board_info0,
2087 ARRAY_SIZE(bfin_i2c_board_info0));
2088 i2c_register_board_info(1, bfin_i2c_board_info1,
2089 ARRAY_SIZE(bfin_i2c_board_info1));
2090
2091 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
2092
2093 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
2094
2095 return 0;
2096 }
2097
2098 arch_initcall(ezkit_init);
2099
2100 static struct platform_device *ezkit_early_devices[] __initdata = {
2101 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
2102 #ifdef CONFIG_SERIAL_BFIN_UART0
2103 &bfin_uart0_device,
2104 #endif
2105 #ifdef CONFIG_SERIAL_BFIN_UART1
2106 &bfin_uart1_device,
2107 #endif
2108 #endif
2109 };
2110
2111 void __init native_machine_early_platform_add_devices(void)
2112 {
2113 printk(KERN_INFO "register early platform devices\n");
2114 early_platform_add_devices(ezkit_early_devices,
2115 ARRAY_SIZE(ezkit_early_devices));
2116 }
Linux with added FPC-III support