3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 * Derived from arch/i386/kernel/pci-pc.c
6 * (c) 1999--2000 Martin Mares <mj@suse.cz>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public Licence
10 * as published by the Free Software Foundation; either version
11 * 2 of the Licence, or (at your option) any later version.
13 #include <linux/types.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
18 #include <linux/ioport.h>
19 #include <linux/delay.h>
20 #include <linux/irq.h>
23 #include "pci-asb2305.h"
25 unsigned int pci_probe
= 1;
27 struct pci_ops
*pci_root_ops
;
30 * The accessible PCI window does not cover the entire CPU address space, but
31 * there are devices we want to access outside of that window, so we need to
32 * insert specific PCI bus resources instead of using the platform-level bus
33 * resources directly for the PCI root bus.
35 * These are configured and inserted by pcibios_init().
37 static struct resource pci_ioport_resource
= {
41 .flags
= IORESOURCE_IO
,
44 static struct resource pci_iomem_resource
= {
48 .flags
= IORESOURCE_MEM
,
52 * Functions for accessing PCI configuration space
55 #define CONFIG_CMD(bus, devfn, where) \
56 (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
58 #define MEM_PAGING_REG (*(volatile __u32 *) 0xBFFFFFF4)
59 #define CONFIG_ADDRESS (*(volatile __u32 *) 0xBFFFFFF8)
60 #define CONFIG_DATAL(X) (*(volatile __u32 *) 0xBFFFFFFC)
61 #define CONFIG_DATAW(X) (*(volatile __u16 *) (0xBFFFFFFC + ((X) & 2)))
62 #define CONFIG_DATAB(X) (*(volatile __u8 *) (0xBFFFFFFC + ((X) & 3)))
64 #define BRIDGEREGB(X) (*(volatile __u8 *) (0xBE040000 + (X)))
65 #define BRIDGEREGW(X) (*(volatile __u16 *) (0xBE040000 + (X)))
66 #define BRIDGEREGL(X) (*(volatile __u32 *) (0xBE040000 + (X)))
68 static inline int __query(const struct pci_bus
*bus
, unsigned int devfn
)
71 return bus
->number
== 0 && (devfn
== PCI_DEVFN(0, 0));
72 return bus
->number
== 1;
73 return bus
->number
== 0 &&
74 (devfn
== PCI_DEVFN(2, 0) || devfn
== PCI_DEVFN(3, 0));
82 static int pci_ampci_read_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
83 int where
, u32
*_value
)
87 if (bus
->number
== 0 && devfn
== PCI_DEVFN(0, 0)) {
88 value
= BRIDGEREGB(where
);
89 __pcbdebug("=> %02hx", &BRIDGEREGL(where
), value
);
91 CONFIG_ADDRESS
= CONFIG_CMD(bus
, devfn
, where
);
92 rawval
= CONFIG_ADDRESS
;
93 value
= CONFIG_DATAB(where
);
94 if (__query(bus
, devfn
))
95 __pcidebug("=> %02hx", bus
, devfn
, where
, value
);
99 return PCIBIOS_SUCCESSFUL
;
102 static int pci_ampci_read_config_word(struct pci_bus
*bus
, unsigned int devfn
,
103 int where
, u32
*_value
)
107 if (bus
->number
== 0 && devfn
== PCI_DEVFN(0, 0)) {
108 value
= BRIDGEREGW(where
);
109 __pcbdebug("=> %04hx", &BRIDGEREGL(where
), value
);
111 CONFIG_ADDRESS
= CONFIG_CMD(bus
, devfn
, where
);
112 rawval
= CONFIG_ADDRESS
;
113 value
= CONFIG_DATAW(where
);
114 if (__query(bus
, devfn
))
115 __pcidebug("=> %04hx", bus
, devfn
, where
, value
);
119 return PCIBIOS_SUCCESSFUL
;
122 static int pci_ampci_read_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
123 int where
, u32
*_value
)
127 if (bus
->number
== 0 && devfn
== PCI_DEVFN(0, 0)) {
128 value
= BRIDGEREGL(where
);
129 __pcbdebug("=> %08x", &BRIDGEREGL(where
), value
);
131 CONFIG_ADDRESS
= CONFIG_CMD(bus
, devfn
, where
);
132 rawval
= CONFIG_ADDRESS
;
133 value
= CONFIG_DATAL(where
);
134 if (__query(bus
, devfn
))
135 __pcidebug("=> %08x", bus
, devfn
, where
, value
);
139 return PCIBIOS_SUCCESSFUL
;
142 static int pci_ampci_write_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
147 if (bus
->number
== 0 && devfn
== PCI_DEVFN(0, 0)) {
148 __pcbdebug("<= %02x", &BRIDGEREGB(where
), value
);
149 BRIDGEREGB(where
) = value
;
151 if (bus
->number
== 0 &&
152 (devfn
== PCI_DEVFN(2, 0) || devfn
== PCI_DEVFN(3, 0))
154 __pcidebug("<= %02x", bus
, devfn
, where
, value
);
155 CONFIG_ADDRESS
= CONFIG_CMD(bus
, devfn
, where
);
156 rawval
= CONFIG_ADDRESS
;
157 CONFIG_DATAB(where
) = value
;
159 return PCIBIOS_SUCCESSFUL
;
162 static int pci_ampci_write_config_word(struct pci_bus
*bus
, unsigned int devfn
,
163 int where
, u16 value
)
167 if (bus
->number
== 0 && devfn
== PCI_DEVFN(0, 0)) {
168 __pcbdebug("<= %04hx", &BRIDGEREGW(where
), value
);
169 BRIDGEREGW(where
) = value
;
171 if (__query(bus
, devfn
))
172 __pcidebug("<= %04hx", bus
, devfn
, where
, value
);
173 CONFIG_ADDRESS
= CONFIG_CMD(bus
, devfn
, where
);
174 rawval
= CONFIG_ADDRESS
;
175 CONFIG_DATAW(where
) = value
;
177 return PCIBIOS_SUCCESSFUL
;
180 static int pci_ampci_write_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
181 int where
, u32 value
)
185 if (bus
->number
== 0 && devfn
== PCI_DEVFN(0, 0)) {
186 __pcbdebug("<= %08x", &BRIDGEREGL(where
), value
);
187 BRIDGEREGL(where
) = value
;
189 if (__query(bus
, devfn
))
190 __pcidebug("<= %08x", bus
, devfn
, where
, value
);
191 CONFIG_ADDRESS
= CONFIG_CMD(bus
, devfn
, where
);
192 rawval
= CONFIG_ADDRESS
;
193 CONFIG_DATAL(where
) = value
;
195 return PCIBIOS_SUCCESSFUL
;
198 static int pci_ampci_read_config(struct pci_bus
*bus
, unsigned int devfn
,
199 int where
, int size
, u32
*val
)
203 return pci_ampci_read_config_byte(bus
, devfn
, where
, val
);
205 return pci_ampci_read_config_word(bus
, devfn
, where
, val
);
207 return pci_ampci_read_config_dword(bus
, devfn
, where
, val
);
214 static int pci_ampci_write_config(struct pci_bus
*bus
, unsigned int devfn
,
215 int where
, int size
, u32 val
)
219 return pci_ampci_write_config_byte(bus
, devfn
, where
, val
);
221 return pci_ampci_write_config_word(bus
, devfn
, where
, val
);
223 return pci_ampci_write_config_dword(bus
, devfn
, where
, val
);
230 static struct pci_ops pci_direct_ampci
= {
231 pci_ampci_read_config
,
232 pci_ampci_write_config
,
236 * Before we decide to use direct hardware access mechanisms, we try to do some
237 * trivial checks to ensure it at least _seems_ to be working -- we just test
238 * whether bus 00 contains a host bridge (this is similar to checking
239 * techniques used in XFree86, but ours should be more reliable since we
240 * attempt to make use of direct access hints provided by the PCI BIOS).
242 * This should be close to trivial, but it isn't, because there are buggy
243 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
245 static int __init
pci_sanity_check(struct pci_ops
*o
)
247 struct pci_bus bus
; /* Fake bus and device */
252 if ((!o
->read(&bus
, 0, PCI_CLASS_DEVICE
, 2, &x
) &&
253 (x
== PCI_CLASS_BRIDGE_HOST
|| x
== PCI_CLASS_DISPLAY_VGA
)) ||
254 (!o
->read(&bus
, 0, PCI_VENDOR_ID
, 2, &x
) &&
255 (x
== PCI_VENDOR_ID_INTEL
|| x
== PCI_VENDOR_ID_COMPAQ
)))
258 printk(KERN_ERR
"PCI: Sanity check failed\n");
262 static int __init
pci_check_direct(void)
266 local_irq_save(flags
);
269 * Check if access works.
271 if (pci_sanity_check(&pci_direct_ampci
)) {
272 local_irq_restore(flags
);
273 printk(KERN_INFO
"PCI: Using configuration ampci\n");
274 request_mem_region(0xBE040000, 256, "AMPCI bridge");
275 request_mem_region(0xBFFFFFF4, 12, "PCI ampci");
276 request_mem_region(0xBC000000, 32 * 1024 * 1024, "PCI SRAM");
280 local_irq_restore(flags
);
284 static int is_valid_resource(struct pci_dev
*dev
, int idx
)
286 unsigned int i
, type_mask
= IORESOURCE_IO
| IORESOURCE_MEM
;
287 struct resource
*devr
= &dev
->resource
[idx
], *busr
;
290 pci_bus_for_each_resource(dev
->bus
, busr
, i
) {
291 if (!busr
|| (busr
->flags
^ devr
->flags
) & type_mask
)
295 devr
->start
>= busr
->start
&&
296 devr
->end
<= busr
->end
)
304 static void pcibios_fixup_device_resources(struct pci_dev
*dev
)
308 if (dev
->bus
->number
!= 0)
311 limit
= (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) ?
312 PCI_BRIDGE_RESOURCES
: PCI_NUM_RESOURCES
;
314 for (i
= 0; i
< limit
; i
++) {
315 if (!dev
->resource
[i
].flags
)
318 if (is_valid_resource(dev
, i
))
319 pci_claim_resource(dev
, i
);
324 * Called after each bus is probed, but before its children
327 void pcibios_fixup_bus(struct pci_bus
*bus
)
332 pci_read_bridge_bases(bus
);
333 pcibios_fixup_device_resources(bus
->self
);
336 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
337 pcibios_fixup_device_resources(dev
);
341 * Initialization. Try all known PCI access methods. Note that we support
342 * using both PCI BIOS and direct access: in such cases, we use I/O ports
343 * to access config space, but we still keep BIOS order of cards to be
344 * compatible with 2.0.X. This should go away some day.
346 static int __init
pcibios_init(void)
348 resource_size_t io_offset
, mem_offset
;
349 LIST_HEAD(resources
);
351 ioport_resource
.start
= 0xA0000000;
352 ioport_resource
.end
= 0xDFFFFFFF;
353 iomem_resource
.start
= 0xA0000000;
354 iomem_resource
.end
= 0xDFFFFFFF;
356 if (insert_resource(&iomem_resource
, &pci_iomem_resource
) < 0)
357 panic("Unable to insert PCI IOMEM resource\n");
358 if (insert_resource(&ioport_resource
, &pci_ioport_resource
) < 0)
359 panic("Unable to insert PCI IOPORT resource\n");
364 if (pci_check_direct() < 0) {
365 printk(KERN_WARNING
"PCI: No PCI bus detected\n");
369 printk(KERN_INFO
"PCI: Probing PCI hardware [mempage %08x]\n",
372 io_offset
= pci_ioport_resource
.start
-
373 (pci_ioport_resource
.start
& 0x00ffffff);
374 mem_offset
= pci_iomem_resource
.start
-
375 ((pci_iomem_resource
.start
& 0x03ffffff) | MEM_PAGING_REG
);
377 pci_add_resource_offset(&resources
, &pci_ioport_resource
, io_offset
);
378 pci_add_resource_offset(&resources
, &pci_iomem_resource
, mem_offset
);
379 pci_scan_root_bus(NULL
, 0, &pci_direct_ampci
, NULL
, &resources
);
382 pcibios_fixup_irqs();
383 pcibios_resource_survey();
387 arch_initcall(pcibios_init
);
389 char *__init
pcibios_setup(char *str
)
391 if (!strcmp(str
, "off")) {
399 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
403 err
= pci_enable_resources(dev
, mask
);
405 pcibios_enable_irq(dev
);
410 * disable the ethernet chipset
412 static void __init
unit_disable_pcnet(struct pci_bus
*bus
, struct pci_ops
*o
)
418 o
->read (bus
, PCI_DEVFN(2, 0), PCI_VENDOR_ID
, 4, &x
);
419 o
->read (bus
, PCI_DEVFN(2, 0), PCI_COMMAND
, 2, &x
);
420 x
|= PCI_COMMAND_MASTER
|
421 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
|
422 PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
423 o
->write(bus
, PCI_DEVFN(2, 0), PCI_COMMAND
, 2, x
);
424 o
->read (bus
, PCI_DEVFN(2, 0), PCI_COMMAND
, 2, &x
);
425 o
->write(bus
, PCI_DEVFN(2, 0), PCI_BASE_ADDRESS_0
, 4, 0x00030001);
426 o
->read (bus
, PCI_DEVFN(2, 0), PCI_BASE_ADDRESS_0
, 4, &x
);
428 #define RDP (*(volatile u32 *) 0xBE030010)
429 #define RAP (*(volatile u32 *) 0xBE030014)
430 #define __set_RAP(X) do { RAP = (X); x = RAP; } while (0)
431 #define __set_RDP(X) do { RDP = (X); x = RDP; } while (0)
432 #define __get_RDP() ({ RDP & 0xffff; })
435 __set_RDP(0x0004); /* CSR0 = STOP */
437 __set_RAP(88); /* check CSR88 indicates an Am79C973 */
438 BUG_ON(__get_RDP() != 0x5003);
440 for (x
= 0; x
< 100; x
++)
443 __set_RDP(0x0004); /* CSR0 = STOP */
447 * initialise the unit hardware
449 asmlinkage
void __init
unit_pci_init(void)
451 struct pci_bus bus
; /* Fake bus and device */
452 struct pci_ops
*o
= &pci_direct_ampci
;
455 set_intr_level(XIRQ1
, NUM2GxICR_LEVEL(CONFIG_PCI_IRQ_LEVEL
));
457 memset(&bus
, 0, sizeof(bus
));
459 MEM_PAGING_REG
= 0xE8000000;
461 /* we need to set up the bridge _now_ or we won't be able to access the
462 * PCI config registers
464 BRIDGEREGW(PCI_COMMAND
) |=
465 PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
|
466 PCI_COMMAND_MEMORY
| PCI_COMMAND_IO
| PCI_COMMAND_MASTER
;
467 BRIDGEREGW(PCI_STATUS
) = 0xF800;
468 BRIDGEREGB(PCI_LATENCY_TIMER
) = 0x10;
469 BRIDGEREGL(PCI_BASE_ADDRESS_0
) = 0x80000000;
470 BRIDGEREGB(PCI_INTERRUPT_LINE
) = 1;
471 BRIDGEREGL(0x48) = 0x98000000; /* AMPCI base addr */
472 BRIDGEREGB(0x41) = 0x00; /* secondary bus
474 BRIDGEREGB(0x42) = 0x01; /* subordinate bus
476 BRIDGEREGB(0x44) = 0x01;
477 BRIDGEREGL(0x50) = 0x00000001;
478 BRIDGEREGL(0x58) = 0x00001002;
479 BRIDGEREGL(0x5C) = 0x00000011;
481 /* we also need to set up the PCI-PCI bridge */
484 /* IO: 0x00000000-0x00020000 */
485 o
->read (&bus
, PCI_DEVFN(3, 0), PCI_COMMAND
, 2, &x
);
486 x
|= PCI_COMMAND_MASTER
|
487 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
|
488 PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
489 o
->write(&bus
, PCI_DEVFN(3, 0), PCI_COMMAND
, 2, x
);
491 o
->read (&bus
, PCI_DEVFN(3, 0), PCI_IO_BASE
, 1, &x
);
492 o
->read (&bus
, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16
, 4, &x
);
493 o
->read (&bus
, PCI_DEVFN(3, 0), PCI_MEMORY_BASE
, 4, &x
);
494 o
->read (&bus
, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE
, 4, &x
);
496 o
->write(&bus
, PCI_DEVFN(3, 0), PCI_IO_BASE
, 1, 0x01);
497 o
->read (&bus
, PCI_DEVFN(3, 0), PCI_IO_BASE
, 1, &x
);
498 o
->write(&bus
, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16
, 4, 0x00020000);
499 o
->read (&bus
, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16
, 4, &x
);
500 o
->write(&bus
, PCI_DEVFN(3, 0), PCI_MEMORY_BASE
, 4, 0xEBB0EA00);
501 o
->read (&bus
, PCI_DEVFN(3, 0), PCI_MEMORY_BASE
, 4, &x
);
502 o
->write(&bus
, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE
, 4, 0xE9F0E800);
503 o
->read (&bus
, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE
, 4, &x
);
505 unit_disable_pcnet(&bus
, o
);