| blob | 3132bb9365f33788771c610aea90e25384f736d0 |
1 /*
2 * Copyright 2009 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * provides masks and opcode images for use by code generation, emulation
10 * and for instructions that older assemblers might not know about
11 */
12 #ifndef _ASM_POWERPC_PPC_OPCODE_H
13 #define _ASM_POWERPC_PPC_OPCODE_H
15 #include <linux/stringify.h>
16 #include <asm/asm-compat.h>
18 #define __REG_R0 0
19 #define __REG_R1 1
20 #define __REG_R2 2
21 #define __REG_R3 3
22 #define __REG_R4 4
23 #define __REG_R5 5
24 #define __REG_R6 6
25 #define __REG_R7 7
26 #define __REG_R8 8
27 #define __REG_R9 9
28 #define __REG_R10 10
29 #define __REG_R11 11
30 #define __REG_R12 12
31 #define __REG_R13 13
32 #define __REG_R14 14
33 #define __REG_R15 15
34 #define __REG_R16 16
35 #define __REG_R17 17
36 #define __REG_R18 18
37 #define __REG_R19 19
38 #define __REG_R20 20
39 #define __REG_R21 21
40 #define __REG_R22 22
41 #define __REG_R23 23
42 #define __REG_R24 24
43 #define __REG_R25 25
44 #define __REG_R26 26
45 #define __REG_R27 27
46 #define __REG_R28 28
47 #define __REG_R29 29
48 #define __REG_R30 30
49 #define __REG_R31 31
51 #define __REGA0_0 0
52 #define __REGA0_R1 1
53 #define __REGA0_R2 2
54 #define __REGA0_R3 3
55 #define __REGA0_R4 4
56 #define __REGA0_R5 5
57 #define __REGA0_R6 6
58 #define __REGA0_R7 7
59 #define __REGA0_R8 8
60 #define __REGA0_R9 9
61 #define __REGA0_R10 10
62 #define __REGA0_R11 11
63 #define __REGA0_R12 12
64 #define __REGA0_R13 13
65 #define __REGA0_R14 14
66 #define __REGA0_R15 15
67 #define __REGA0_R16 16
68 #define __REGA0_R17 17
69 #define __REGA0_R18 18
70 #define __REGA0_R19 19
71 #define __REGA0_R20 20
72 #define __REGA0_R21 21
73 #define __REGA0_R22 22
74 #define __REGA0_R23 23
75 #define __REGA0_R24 24
76 #define __REGA0_R25 25
77 #define __REGA0_R26 26
78 #define __REGA0_R27 27
79 #define __REGA0_R28 28
80 #define __REGA0_R29 29
81 #define __REGA0_R30 30
82 #define __REGA0_R31 31
84 /* opcode and xopcode for instructions */
85 #define OP_TRAP 3
86 #define OP_TRAP_64 2
88 #define OP_31_XOP_TRAP 4
89 #define OP_31_XOP_LWZX 23
90 #define OP_31_XOP_DCBST 54
91 #define OP_31_XOP_LWZUX 55
92 #define OP_31_XOP_TRAP_64 68
93 #define OP_31_XOP_DCBF 86
94 #define OP_31_XOP_LBZX 87
95 #define OP_31_XOP_STWX 151
96 #define OP_31_XOP_STBX 215
97 #define OP_31_XOP_LBZUX 119
98 #define OP_31_XOP_STBUX 247
99 #define OP_31_XOP_LHZX 279
100 #define OP_31_XOP_LHZUX 311
101 #define OP_31_XOP_MFSPR 339
102 #define OP_31_XOP_LHAX 343
103 #define OP_31_XOP_LHAUX 375
104 #define OP_31_XOP_STHX 407
105 #define OP_31_XOP_STHUX 439
106 #define OP_31_XOP_MTSPR 467
107 #define OP_31_XOP_DCBI 470
108 #define OP_31_XOP_LWBRX 534
109 #define OP_31_XOP_TLBSYNC 566
110 #define OP_31_XOP_STWBRX 662
111 #define OP_31_XOP_LHBRX 790
112 #define OP_31_XOP_STHBRX 918
114 #define OP_LWZ 32
115 #define OP_LD 58
116 #define OP_LWZU 33
117 #define OP_LBZ 34
118 #define OP_LBZU 35
119 #define OP_STW 36
120 #define OP_STWU 37
121 #define OP_STD 62
122 #define OP_STB 38
123 #define OP_STBU 39
124 #define OP_LHZ 40
125 #define OP_LHZU 41
126 #define OP_LHA 42
127 #define OP_LHAU 43
128 #define OP_STH 44
129 #define OP_STHU 45
131 /* sorted alphabetically */
132 #define PPC_INST_BHRBE 0x7c00025c
133 #define PPC_INST_CLRBHRB 0x7c00035c
134 #define PPC_INST_DCBA 0x7c0005ec
135 #define PPC_INST_DCBA_MASK 0xfc0007fe
136 #define PPC_INST_DCBAL 0x7c2005ec
137 #define PPC_INST_DCBZL 0x7c2007ec
138 #define PPC_INST_ICBT 0x7c00002c
139 #define PPC_INST_ISEL 0x7c00001e
140 #define PPC_INST_ISEL_MASK 0xfc00003e
141 #define PPC_INST_LDARX 0x7c0000a8
142 #define PPC_INST_LSWI 0x7c0004aa
143 #define PPC_INST_LSWX 0x7c00042a
144 #define PPC_INST_LWARX 0x7c000028
145 #define PPC_INST_LWSYNC 0x7c2004ac
146 #define PPC_INST_SYNC 0x7c0004ac
147 #define PPC_INST_SYNC_MASK 0xfc0007fe
148 #define PPC_INST_LXVD2X 0x7c000698
149 #define PPC_INST_MCRXR 0x7c000400
150 #define PPC_INST_MCRXR_MASK 0xfc0007fe
151 #define PPC_INST_MFSPR_PVR 0x7c1f42a6
152 #define PPC_INST_MFSPR_PVR_MASK 0xfc1fffff
153 #define PPC_INST_MSGSND 0x7c00019c
154 #define PPC_INST_MSGSNDP 0x7c00011c
155 #define PPC_INST_NOP 0x60000000
156 #define PPC_INST_POPCNTB 0x7c0000f4
157 #define PPC_INST_POPCNTB_MASK 0xfc0007fe
158 #define PPC_INST_POPCNTD 0x7c0003f4
159 #define PPC_INST_POPCNTW 0x7c0002f4
160 #define PPC_INST_RFCI 0x4c000066
161 #define PPC_INST_RFDI 0x4c00004e
162 #define PPC_INST_RFMCI 0x4c00004c
163 #define PPC_INST_MFSPR_DSCR 0x7c1102a6
164 #define PPC_INST_MFSPR_DSCR_MASK 0xfc1fffff
165 #define PPC_INST_MTSPR_DSCR 0x7c1103a6
166 #define PPC_INST_MTSPR_DSCR_MASK 0xfc1fffff
167 #define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6
168 #define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1fffff
169 #define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6
170 #define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1fffff
171 #define PPC_INST_SLBFEE 0x7c0007a7
173 #define PPC_INST_STRING 0x7c00042a
174 #define PPC_INST_STRING_MASK 0xfc0007fe
175 #define PPC_INST_STRING_GEN_MASK 0xfc00067e
177 #define PPC_INST_STSWI 0x7c0005aa
178 #define PPC_INST_STSWX 0x7c00052a
179 #define PPC_INST_STXVD2X 0x7c000798
180 #define PPC_INST_TLBIE 0x7c000264
181 #define PPC_INST_TLBILX 0x7c000024
182 #define PPC_INST_WAIT 0x7c00007c
183 #define PPC_INST_TLBIVAX 0x7c000624
184 #define PPC_INST_TLBSRX_DOT 0x7c0006a5
185 #define PPC_INST_XXLOR 0xf0000510
186 #define PPC_INST_XXSWAPD 0xf0000250
187 #define PPC_INST_XVCPSGNDP 0xf0000780
188 #define PPC_INST_TRECHKPT 0x7c0007dd
189 #define PPC_INST_TRECLAIM 0x7c00075d
190 #define PPC_INST_TABORT 0x7c00071d
192 #define PPC_INST_NAP 0x4c000364
193 #define PPC_INST_SLEEP 0x4c0003a4
195 /* A2 specific instructions */
196 #define PPC_INST_ERATWE 0x7c0001a6
197 #define PPC_INST_ERATRE 0x7c000166
198 #define PPC_INST_ERATILX 0x7c000066
199 #define PPC_INST_ERATIVAX 0x7c000666
200 #define PPC_INST_ERATSX 0x7c000126
201 #define PPC_INST_ERATSX_DOT 0x7c000127
203 /* Misc instructions for BPF compiler */
204 #define PPC_INST_LD 0xe8000000
205 #define PPC_INST_LHZ 0xa0000000
206 #define PPC_INST_LHBRX 0x7c00062c
207 #define PPC_INST_LWZ 0x80000000
208 #define PPC_INST_STD 0xf8000000
209 #define PPC_INST_STDU 0xf8000001
210 #define PPC_INST_MFLR 0x7c0802a6
211 #define PPC_INST_MTLR 0x7c0803a6
212 #define PPC_INST_CMPWI 0x2c000000
213 #define PPC_INST_CMPDI 0x2c200000
214 #define PPC_INST_CMPLW 0x7c000040
215 #define PPC_INST_CMPLWI 0x28000000
216 #define PPC_INST_ADDI 0x38000000
217 #define PPC_INST_ADDIS 0x3c000000
218 #define PPC_INST_ADD 0x7c000214
219 #define PPC_INST_SUB 0x7c000050
220 #define PPC_INST_BLR 0x4e800020
221 #define PPC_INST_BLRL 0x4e800021
222 #define PPC_INST_MULLW 0x7c0001d6
223 #define PPC_INST_MULHWU 0x7c000016
224 #define PPC_INST_MULLI 0x1c000000
225 #define PPC_INST_DIVWU 0x7c000396
226 #define PPC_INST_RLWINM 0x54000000
227 #define PPC_INST_RLDICR 0x78000004
228 #define PPC_INST_SLW 0x7c000030
229 #define PPC_INST_SRW 0x7c000430
230 #define PPC_INST_AND 0x7c000038
231 #define PPC_INST_ANDDOT 0x7c000039
232 #define PPC_INST_OR 0x7c000378
233 #define PPC_INST_XOR 0x7c000278
234 #define PPC_INST_ANDI 0x70000000
235 #define PPC_INST_ORI 0x60000000
236 #define PPC_INST_ORIS 0x64000000
237 #define PPC_INST_XORI 0x68000000
238 #define PPC_INST_XORIS 0x6c000000
239 #define PPC_INST_NEG 0x7c0000d0
240 #define PPC_INST_BRANCH 0x48000000
241 #define PPC_INST_BRANCH_COND 0x40800000
242 #define PPC_INST_LBZCIX 0x7c0006aa
243 #define PPC_INST_STBCIX 0x7c0007aa
245 /* macros to insert fields into opcodes */
246 #define ___PPC_RA(a) (((a) & 0x1f) << 16)
247 #define ___PPC_RB(b) (((b) & 0x1f) << 11)
248 #define ___PPC_RS(s) (((s) & 0x1f) << 21)
249 #define ___PPC_RT(t) ___PPC_RS(t)
250 #define __PPC_RA(a) ___PPC_RA(__REG_##a)
251 #define __PPC_RA0(a) ___PPC_RA(__REGA0_##a)
252 #define __PPC_RB(b) ___PPC_RB(__REG_##b)
253 #define __PPC_RS(s) ___PPC_RS(__REG_##s)
254 #define __PPC_RT(t) ___PPC_RT(__REG_##t)
255 #define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
256 #define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
257 #define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
258 #define __PPC_XT(s) __PPC_XS(s)
259 #define __PPC_T_TLB(t) (((t) & 0x3) << 21)
260 #define __PPC_WC(w) (((w) & 0x3) << 21)
261 #define __PPC_WS(w) (((w) & 0x1f) << 11)
262 #define __PPC_SH(s) __PPC_WS(s)
263 #define __PPC_MB(s) (((s) & 0x1f) << 6)
264 #define __PPC_ME(s) (((s) & 0x1f) << 1)
265 #define __PPC_BI(s) (((s) & 0x1f) << 16)
266 #define __PPC_CT(t) (((t) & 0x0f) << 21)
268 /*
269 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
270 * larx with EH set as an illegal instruction.
271 */
272 #ifdef CONFIG_PPC64
273 #define __PPC_EH(eh) (((eh) & 0x1) << 0)
274 #else
275 #define __PPC_EH(eh) 0
276 #endif
278 /* Deal with instructions that older assemblers aren't aware of */
279 #define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \
280 __PPC_RA(a) | __PPC_RB(b))
281 #define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \
282 __PPC_RA(a) | __PPC_RB(b))
283 #define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \
284 ___PPC_RT(t) | ___PPC_RA(a) | \
285 ___PPC_RB(b) | __PPC_EH(eh))
286 #define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \
287 ___PPC_RT(t) | ___PPC_RA(a) | \
288 ___PPC_RB(b) | __PPC_EH(eh))
289 #define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \
290 ___PPC_RB(b))
291 #define PPC_MSGSNDP(b) stringify_in_c(.long PPC_INST_MSGSNDP | \
292 ___PPC_RB(b))
293 #define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \
294 __PPC_RA(a) | __PPC_RS(s))
295 #define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \
296 __PPC_RA(a) | __PPC_RS(s))
297 #define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \
298 __PPC_RA(a) | __PPC_RS(s))
299 #define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI)
300 #define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
301 #define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
302 #define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \
303 __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
304 #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
305 #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
306 #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
307 #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
308 __PPC_WC(w))
309 #define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \
310 ___PPC_RB(a) | ___PPC_RS(lp))
311 #define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
312 __PPC_RA0(a) | __PPC_RB(b))
313 #define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \
314 __PPC_RA0(a) | __PPC_RB(b))
316 #define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \
317 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
318 #define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \
319 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
320 #define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \
321 __PPC_T_TLB(t) | __PPC_RA0(a) | \
322 __PPC_RB(b))
323 #define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \
324 __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
325 #define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \
326 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
327 #define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
328 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
329 #define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \
330 __PPC_RT(t) | __PPC_RB(b))
331 #define PPC_ICBT(c,a,b) stringify_in_c(.long PPC_INST_ICBT | \
332 __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
333 /* PASemi instructions */
334 #define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \
335 __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
336 #define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \
337 __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
339 /*
340 * Define what the VSX XX1 form instructions will look like, then add
341 * the 128 bit load store instructions based on that.
342 */
343 #define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
344 #define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
345 #define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \
346 VSX_XX1((s), a, b))
347 #define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \
348 VSX_XX1((s), a, b))
349 #define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \
350 VSX_XX3((t), a, b))
351 #define XXSWAPD(t, a) stringify_in_c(.long PPC_INST_XXSWAPD | \
352 VSX_XX3((t), a, a))
353 #define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_INST_XVCPSGNDP | \
354 VSX_XX3((t), (a), (b))))
356 #define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
357 #define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
359 /* BHRB instructions */
360 #define PPC_CLRBHRB stringify_in_c(.long PPC_INST_CLRBHRB)
361 #define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_INST_BHRBE | \
362 __PPC_RT(r) | \
363 (((n) & 0x3ff) << 11))
365 /* Transactional memory instructions */
366 #define TRECHKPT stringify_in_c(.long PPC_INST_TRECHKPT)
367 #define TRECLAIM(r) stringify_in_c(.long PPC_INST_TRECLAIM \
368 | __PPC_RA(r))
369 #define TABORT(r) stringify_in_c(.long PPC_INST_TABORT \
370 | __PPC_RA(r))