arch/powerpc/perf/power8-pmu.c

   1 /*
   2  * Performance counter support for POWER8 processors.
   3  *
   4  * Copyright 2009 Paul Mackerras, IBM Corporation.
   5  * Copyright 2013 Michael Ellerman, IBM Corporation.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version
  10  * 2 of the License, or (at your option) any later version.
  11  */
  12
  13 #define pr_fmt(fmt)     "power8-pmu: " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/perf_event.h>
  17 #include <asm/firmware.h>
  18
  19
  20 /*
  21  * Some power8 event codes.
  22  */
  23 #define PM_CYC                          0x0001e
  24 #define PM_GCT_NOSLOT_CYC               0x100f8
  25 #define PM_CMPLU_STALL                  0x4000a
  26 #define PM_INST_CMPL                    0x00002
  27 #define PM_BRU_FIN                      0x10068
  28 #define PM_BR_MPRED_CMPL                0x400f6
  29
  30 /* All L1 D cache load references counted at finish, gated by reject */
  31 #define PM_LD_REF_L1                    0x100ee
  32 /* Load Missed L1 */
  33 #define PM_LD_MISS_L1                   0x3e054
  34 /* Store Missed L1 */
  35 #define PM_ST_MISS_L1                   0x300f0
  36 /* L1 cache data prefetches */
  37 #define PM_L1_PREF                      0x0d8b8
  38 /* Instruction fetches from L1 */
  39 #define PM_INST_FROM_L1                 0x04080
  40 /* Demand iCache Miss */
  41 #define PM_L1_ICACHE_MISS               0x200fd
  42 /* Instruction Demand sectors wriittent into IL1 */
  43 #define PM_L1_DEMAND_WRITE              0x0408c
  44 /* Instruction prefetch written into IL1 */
  45 #define PM_IC_PREF_WRITE                0x0408e
  46 /* The data cache was reloaded from local core's L3 due to a demand load */
  47 #define PM_DATA_FROM_L3                 0x4c042
  48 /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
  49 #define PM_DATA_FROM_L3MISS             0x300fe
  50 /* All successful D-side store dispatches for this thread */
  51 #define PM_L2_ST                        0x17080
  52 /* All successful D-side store dispatches for this thread that were L2 Miss */
  53 #define PM_L2_ST_MISS                   0x17082
  54 /* Total HW L3 prefetches(Load+store) */
  55 #define PM_L3_PREF_ALL                  0x4e052
  56 /* Data PTEG reload */
  57 #define PM_DTLB_MISS                    0x300fc
  58 /* ITLB Reloaded */
  59 #define PM_ITLB_MISS                    0x400fc
  60
  61
  62 /*
  63  * Raw event encoding for POWER8:
  64  *
  65  *        60        56        52        48        44        40        36        32
  66  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
  67  *   | | [ ]                           [      thresh_cmp     ]   [  thresh_ctl   ]
  68  *   | |  |                                                              |
  69  *   | |  *- IFM (Linux)                 thresh start/stop OR FAB match -*
  70  *   | *- BHRB (Linux)
  71  *   *- EBB (Linux)
  72  *
  73  *        28        24        20        16        12         8         4         0
  74  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
  75  *   [   ] [  sample ]   [cache]   [ pmc ]   [unit ]   c     m   [    pmcxsel    ]
  76  *     |        |           |                          |     |
  77  *     |        |           |                          |     *- mark
  78  *     |        |           *- L1/L2/L3 cache_sel      |
  79  *     |        |                                      |
  80  *     |        *- sampling mode for marked events     *- combine
  81  *     |
  82  *     *- thresh_sel
  83  *
  84  * Below uses IBM bit numbering.
  85  *
  86  * MMCR1[x:y] = unit    (PMCxUNIT)
  87  * MMCR1[x]   = combine (PMCxCOMB)
  88  *
  89  * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
  90  *      # PM_MRK_FAB_RSP_MATCH
  91  *      MMCR1[20:27] = thresh_ctl   (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
  92  * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
  93  *      # PM_MRK_FAB_RSP_MATCH_CYC
  94  *      MMCR1[20:27] = thresh_ctl   (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
  95  * else
  96  *      MMCRA[48:55] = thresh_ctl   (THRESH START/END)
  97  *
  98  * if thresh_sel:
  99  *      MMCRA[45:47] = thresh_sel
 100  *
 101  * if thresh_cmp:
 102  *      MMCRA[22:24] = thresh_cmp[0:2]
 103  *      MMCRA[25:31] = thresh_cmp[3:9]
 104  *
 105  * if unit == 6 or unit == 7
 106  *      MMCRC[53:55] = cache_sel[1:3]      (L2EVENT_SEL)
 107  * else if unit == 8 or unit == 9:
 108  *      if cache_sel[0] == 0: # L3 bank
 109  *              MMCRC[47:49] = cache_sel[1:3]  (L3EVENT_SEL0)
 110  *      else if cache_sel[0] == 1:
 111  *              MMCRC[50:51] = cache_sel[2:3]  (L3EVENT_SEL1)
 112  * else if cache_sel[1]: # L1 event
 113  *      MMCR1[16] = cache_sel[2]
 114  *     MMCR1[17] = cache_sel[3]
 115  *
 116  * if mark:
 117  *      MMCRA[63]    = 1                (SAMPLE_ENABLE)
 118  *      MMCRA[57:59] = sample[0:2]      (RAND_SAMP_ELIG)
 119  *     MMCRA[61:62] = sample[3:4]      (RAND_SAMP_MODE)
 120  *
 121  * if EBB and BHRB:
 122  *      MMCRA[32:33] = IFM
 123  *
 124  */
 125
 126 #define EVENT_EBB_MASK          1ull
 127 #define EVENT_EBB_SHIFT         PERF_EVENT_CONFIG_EBB_SHIFT
 128 #define EVENT_BHRB_MASK         1ull
 129 #define EVENT_BHRB_SHIFT        62
 130 #define EVENT_WANTS_BHRB        (EVENT_BHRB_MASK << EVENT_BHRB_SHIFT)
 131 #define EVENT_IFM_MASK          3ull
 132 #define EVENT_IFM_SHIFT         60
 133 #define EVENT_THR_CMP_SHIFT     40      /* Threshold CMP value */
 134 #define EVENT_THR_CMP_MASK      0x3ff
 135 #define EVENT_THR_CTL_SHIFT     32      /* Threshold control value (start/stop) */
 136 #define EVENT_THR_CTL_MASK      0xffull
 137 #define EVENT_THR_SEL_SHIFT     29      /* Threshold select value */
 138 #define EVENT_THR_SEL_MASK      0x7
 139 #define EVENT_THRESH_SHIFT      29      /* All threshold bits */
 140 #define EVENT_THRESH_MASK       0x1fffffull
 141 #define EVENT_SAMPLE_SHIFT      24      /* Sampling mode & eligibility */
 142 #define EVENT_SAMPLE_MASK       0x1f
 143 #define EVENT_CACHE_SEL_SHIFT   20      /* L2/L3 cache select */
 144 #define EVENT_CACHE_SEL_MASK    0xf
 145 #define EVENT_IS_L1             (4 << EVENT_CACHE_SEL_SHIFT)
 146 #define EVENT_PMC_SHIFT         16      /* PMC number (1-based) */
 147 #define EVENT_PMC_MASK          0xf
 148 #define EVENT_UNIT_SHIFT        12      /* Unit */
 149 #define EVENT_UNIT_MASK         0xf
 150 #define EVENT_COMBINE_SHIFT     11      /* Combine bit */
 151 #define EVENT_COMBINE_MASK      0x1
 152 #define EVENT_MARKED_SHIFT      8       /* Marked bit */
 153 #define EVENT_MARKED_MASK       0x1
 154 #define EVENT_IS_MARKED         (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT)
 155 #define EVENT_PSEL_MASK         0xff    /* PMCxSEL value */
 156
 157 /* Bits defined by Linux */
 158 #define EVENT_LINUX_MASK        \
 159         ((EVENT_EBB_MASK  << EVENT_EBB_SHIFT)                   |       \
 160          (EVENT_BHRB_MASK << EVENT_BHRB_SHIFT)                  |       \
 161          (EVENT_IFM_MASK  << EVENT_IFM_SHIFT))
 162
 163 #define EVENT_VALID_MASK        \
 164         ((EVENT_THRESH_MASK    << EVENT_THRESH_SHIFT)           |       \
 165          (EVENT_SAMPLE_MASK    << EVENT_SAMPLE_SHIFT)           |       \
 166          (EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT)        |       \
 167          (EVENT_PMC_MASK       << EVENT_PMC_SHIFT)              |       \
 168          (EVENT_UNIT_MASK      << EVENT_UNIT_SHIFT)             |       \
 169          (EVENT_COMBINE_MASK   << EVENT_COMBINE_SHIFT)          |       \
 170          (EVENT_MARKED_MASK    << EVENT_MARKED_SHIFT)           |       \
 171           EVENT_LINUX_MASK                                      |       \
 172           EVENT_PSEL_MASK)
 173
 174 /* MMCRA IFM bits - POWER8 */
 175 #define POWER8_MMCRA_IFM1               0x0000000040000000UL
 176 #define POWER8_MMCRA_IFM2               0x0000000080000000UL
 177 #define POWER8_MMCRA_IFM3               0x00000000C0000000UL
 178
 179 #define ONLY_PLM \
 180         (PERF_SAMPLE_BRANCH_USER        |\
 181          PERF_SAMPLE_BRANCH_KERNEL      |\
 182          PERF_SAMPLE_BRANCH_HV)
 183
 184 /*
 185  * Layout of constraint bits:
 186  *
 187  *        60        56        52        48        44        40        36        32
 188  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
 189  *   [   fab_match   ]         [       thresh_cmp      ] [   thresh_ctl    ] [   ]
 190  *                                                                             |
 191  *                                                                 thresh_sel -*
 192  *
 193  *        28        24        20        16        12         8         4         0
 194  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
 195  *               [ ] |   [ ]   [  sample ]   [     ]   [6] [5]   [4] [3]   [2] [1]
 196  *                |  |    |                     |
 197  *      BHRB IFM -*  |    |                     |      Count of events for each PMC.
 198  *              EBB -*    |                     |        p1, p2, p3, p4, p5, p6.
 199  *      L1 I/D qualifier -*                     |
 200  *                     nc - number of counters -*
 201  *
 202  * The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
 203  * we want the low bit of each field to be added to any existing value.
 204  *
 205  * Everything else is a value field.
 206  */
 207
 208 #define CNST_FAB_MATCH_VAL(v)   (((v) & EVENT_THR_CTL_MASK) << 56)
 209 #define CNST_FAB_MATCH_MASK     CNST_FAB_MATCH_VAL(EVENT_THR_CTL_MASK)
 210
 211 /* We just throw all the threshold bits into the constraint */
 212 #define CNST_THRESH_VAL(v)      (((v) & EVENT_THRESH_MASK) << 32)
 213 #define CNST_THRESH_MASK        CNST_THRESH_VAL(EVENT_THRESH_MASK)
 214
 215 #define CNST_EBB_VAL(v)         (((v) & EVENT_EBB_MASK) << 24)
 216 #define CNST_EBB_MASK           CNST_EBB_VAL(EVENT_EBB_MASK)
 217
 218 #define CNST_IFM_VAL(v)         (((v) & EVENT_IFM_MASK) << 25)
 219 #define CNST_IFM_MASK           CNST_IFM_VAL(EVENT_IFM_MASK)
 220
 221 #define CNST_L1_QUAL_VAL(v)     (((v) & 3) << 22)
 222 #define CNST_L1_QUAL_MASK       CNST_L1_QUAL_VAL(3)
 223
 224 #define CNST_SAMPLE_VAL(v)      (((v) & EVENT_SAMPLE_MASK) << 16)
 225 #define CNST_SAMPLE_MASK        CNST_SAMPLE_VAL(EVENT_SAMPLE_MASK)
 226
 227 /*
 228  * For NC we are counting up to 4 events. This requires three bits, and we need
 229  * the fifth event to overflow and set the 4th bit. To achieve that we bias the
 230  * fields by 3 in test_adder.
 231  */
 232 #define CNST_NC_SHIFT           12
 233 #define CNST_NC_VAL             (1 << CNST_NC_SHIFT)
 234 #define CNST_NC_MASK            (8 << CNST_NC_SHIFT)
 235 #define POWER8_TEST_ADDER       (3 << CNST_NC_SHIFT)
 236
 237 /*
 238  * For the per-PMC fields we have two bits. The low bit is added, so if two
 239  * events ask for the same PMC the sum will overflow, setting the high bit,
 240  * indicating an error. So our mask sets the high bit.
 241  */
 242 #define CNST_PMC_SHIFT(pmc)     ((pmc - 1) * 2)
 243 #define CNST_PMC_VAL(pmc)       (1 << CNST_PMC_SHIFT(pmc))
 244 #define CNST_PMC_MASK(pmc)      (2 << CNST_PMC_SHIFT(pmc))
 245
 246 /* Our add_fields is defined as: */
 247 #define POWER8_ADD_FIELDS       \
 248         CNST_PMC_VAL(1) | CNST_PMC_VAL(2) | CNST_PMC_VAL(3) | \
 249         CNST_PMC_VAL(4) | CNST_PMC_VAL(5) | CNST_PMC_VAL(6) | CNST_NC_VAL
 250
 251
 252 /* Bits in MMCR1 for POWER8 */
 253 #define MMCR1_UNIT_SHIFT(pmc)           (60 - (4 * ((pmc) - 1)))
 254 #define MMCR1_COMBINE_SHIFT(pmc)        (35 - ((pmc) - 1))
 255 #define MMCR1_PMCSEL_SHIFT(pmc)         (24 - (((pmc) - 1)) * 8)
 256 #define MMCR1_FAB_SHIFT                 36
 257 #define MMCR1_DC_QUAL_SHIFT             47
 258 #define MMCR1_IC_QUAL_SHIFT             46
 259
 260 /* Bits in MMCRA for POWER8 */
 261 #define MMCRA_SAMP_MODE_SHIFT           1
 262 #define MMCRA_SAMP_ELIG_SHIFT           4
 263 #define MMCRA_THR_CTL_SHIFT             8
 264 #define MMCRA_THR_SEL_SHIFT             16
 265 #define MMCRA_THR_CMP_SHIFT             32
 266 #define MMCRA_SDAR_MODE_TLB             (1ull << 42)
 267 #define MMCRA_IFM_SHIFT                 30
 268
 269
 270 static inline bool event_is_fab_match(u64 event)
 271 {
 272         /* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */
 273         event &= 0xff0fe;
 274
 275         /* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */
 276         return (event == 0x30056 || event == 0x4f052);
 277 }
 278
 279 static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
 280 {
 281         unsigned int unit, pmc, cache, ebb;
 282         unsigned long mask, value;
 283
 284         mask = value = 0;
 285
 286         if (event & ~EVENT_VALID_MASK)
 287                 return -1;
 288
 289         pmc   = (event >> EVENT_PMC_SHIFT)        & EVENT_PMC_MASK;
 290         unit  = (event >> EVENT_UNIT_SHIFT)       & EVENT_UNIT_MASK;
 291         cache = (event >> EVENT_CACHE_SEL_SHIFT)  & EVENT_CACHE_SEL_MASK;
 292         ebb   = (event >> EVENT_EBB_SHIFT)        & EVENT_EBB_MASK;
 293
 294         if (pmc) {
 295                 u64 base_event;
 296
 297                 if (pmc > 6)
 298                         return -1;
 299
 300                 /* Ignore Linux defined bits when checking event below */
 301                 base_event = event & ~EVENT_LINUX_MASK;
 302
 303                 if (pmc >= 5 && base_event != 0x500fa && base_event != 0x600f4)
 304                         return -1;
 305
 306                 mask  |= CNST_PMC_MASK(pmc);
 307                 value |= CNST_PMC_VAL(pmc);
 308         }
 309
 310         if (pmc <= 4) {
 311                 /*
 312                  * Add to number of counters in use. Note this includes events with
 313                  * a PMC of 0 - they still need a PMC, it's just assigned later.
 314                  * Don't count events on PMC 5 & 6, there is only one valid event
 315                  * on each of those counters, and they are handled above.
 316                  */
 317                 mask  |= CNST_NC_MASK;
 318                 value |= CNST_NC_VAL;
 319         }
 320
 321         if (unit >= 6 && unit <= 9) {
 322                 /*
 323                  * L2/L3 events contain a cache selector field, which is
 324                  * supposed to be programmed into MMCRC. However MMCRC is only
 325                  * HV writable, and there is no API for guest kernels to modify
 326                  * it. The solution is for the hypervisor to initialise the
 327                  * field to zeroes, and for us to only ever allow events that
 328                  * have a cache selector of zero. The bank selector (bit 3) is
 329                  * irrelevant, as long as the rest of the value is 0.
 330                  */
 331                 if (cache & 0x7)
 332                         return -1;
 333
 334         } else if (event & EVENT_IS_L1) {
 335                 mask  |= CNST_L1_QUAL_MASK;
 336                 value |= CNST_L1_QUAL_VAL(cache);
 337         }
 338
 339         if (event & EVENT_IS_MARKED) {
 340                 mask  |= CNST_SAMPLE_MASK;
 341                 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
 342         }
 343
 344         /*
 345          * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
 346          * the threshold control bits are used for the match value.
 347          */
 348         if (event_is_fab_match(event)) {
 349                 mask  |= CNST_FAB_MATCH_MASK;
 350                 value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
 351         } else {
 352                 /*
 353                  * Check the mantissa upper two bits are not zero, unless the
 354                  * exponent is also zero. See the THRESH_CMP_MANTISSA doc.
 355                  */
 356                 unsigned int cmp, exp;
 357
 358                 cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
 359                 exp = cmp >> 7;
 360
 361                 if (exp && (cmp & 0x60) == 0)
 362                         return -1;
 363
 364                 mask  |= CNST_THRESH_MASK;
 365                 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
 366         }
 367
 368         if (!pmc && ebb)
 369                 /* EBB events must specify the PMC */
 370                 return -1;
 371
 372         if (event & EVENT_WANTS_BHRB) {
 373                 if (!ebb)
 374                         /* Only EBB events can request BHRB */
 375                         return -1;
 376
 377                 mask  |= CNST_IFM_MASK;
 378                 value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT);
 379         }
 380
 381         /*
 382          * All events must agree on EBB, either all request it or none.
 383          * EBB events are pinned & exclusive, so this should never actually
 384          * hit, but we leave it as a fallback in case.
 385          */
 386         mask  |= CNST_EBB_VAL(ebb);
 387         value |= CNST_EBB_MASK;
 388
 389         *maskp = mask;
 390         *valp = value;
 391
 392         return 0;
 393 }
 394
 395 static int power8_compute_mmcr(u64 event[], int n_ev,
 396                                unsigned int hwc[], unsigned long mmcr[])
 397 {
 398         unsigned long mmcra, mmcr1, unit, combine, psel, cache, val;
 399         unsigned int pmc, pmc_inuse;
 400         int i;
 401
 402         pmc_inuse = 0;
 403
 404         /* First pass to count resource use */
 405         for (i = 0; i < n_ev; ++i) {
 406                 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
 407                 if (pmc)
 408                         pmc_inuse |= 1 << pmc;
 409         }
 410
 411         /* In continous sampling mode, update SDAR on TLB miss */
 412         mmcra = MMCRA_SDAR_MODE_TLB;
 413         mmcr1 = 0;
 414
 415         /* Second pass: assign PMCs, set all MMCR1 fields */
 416         for (i = 0; i < n_ev; ++i) {
 417                 pmc     = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
 418                 unit    = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
 419                 combine = (event[i] >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK;
 420                 psel    =  event[i] & EVENT_PSEL_MASK;
 421
 422                 if (!pmc) {
 423                         for (pmc = 1; pmc <= 4; ++pmc) {
 424                                 if (!(pmc_inuse & (1 << pmc)))
 425                                         break;
 426                         }
 427
 428                         pmc_inuse |= 1 << pmc;
 429                 }
 430
 431                 if (pmc <= 4) {
 432                         mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc);
 433                         mmcr1 |= combine << MMCR1_COMBINE_SHIFT(pmc);
 434                         mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc);
 435                 }
 436
 437                 if (event[i] & EVENT_IS_L1) {
 438                         cache = event[i] >> EVENT_CACHE_SEL_SHIFT;
 439                         mmcr1 |= (cache & 1) << MMCR1_IC_QUAL_SHIFT;
 440                         cache >>= 1;
 441                         mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT;
 442                 }
 443
 444                 if (event[i] & EVENT_IS_MARKED) {
 445                         mmcra |= MMCRA_SAMPLE_ENABLE;
 446
 447                         val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
 448                         if (val) {
 449                                 mmcra |= (val &  3) << MMCRA_SAMP_MODE_SHIFT;
 450                                 mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT;
 451                         }
 452                 }
 453
 454                 /*
 455                  * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
 456                  * the threshold bits are used for the match value.
 457                  */
 458                 if (event_is_fab_match(event[i])) {
 459                         mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) &
 460                                   EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT;
 461                 } else {
 462                         val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
 463                         mmcra |= val << MMCRA_THR_CTL_SHIFT;
 464                         val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
 465                         mmcra |= val << MMCRA_THR_SEL_SHIFT;
 466                         val = (event[i] >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
 467                         mmcra |= val << MMCRA_THR_CMP_SHIFT;
 468                 }
 469
 470                 if (event[i] & EVENT_WANTS_BHRB) {
 471                         val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK;
 472                         mmcra |= val << MMCRA_IFM_SHIFT;
 473                 }
 474
 475                 hwc[i] = pmc - 1;
 476         }
 477
 478         /* Return MMCRx values */
 479         mmcr[0] = 0;
 480
 481         /* pmc_inuse is 1-based */
 482         if (pmc_inuse & 2)
 483                 mmcr[0] = MMCR0_PMC1CE;
 484
 485         if (pmc_inuse & 0x7c)
 486                 mmcr[0] |= MMCR0_PMCjCE;
 487
 488         /* If we're not using PMC 5 or 6, freeze them */
 489         if (!(pmc_inuse & 0x60))
 490                 mmcr[0] |= MMCR0_FC56;
 491
 492         mmcr[1] = mmcr1;
 493         mmcr[2] = mmcra;
 494
 495         return 0;
 496 }
 497
 498 #define MAX_ALT 2
 499
 500 /* Table of alternatives, sorted by column 0 */
 501 static const unsigned int event_alternatives[][MAX_ALT] = {
 502         { 0x10134, 0x301e2 },           /* PM_MRK_ST_CMPL */
 503         { 0x10138, 0x40138 },           /* PM_BR_MRK_2PATH */
 504         { 0x18082, 0x3e05e },           /* PM_L3_CO_MEPF */
 505         { 0x1d14e, 0x401e8 },           /* PM_MRK_DATA_FROM_L2MISS */
 506         { 0x1e054, 0x4000a },           /* PM_CMPLU_STALL */
 507         { 0x20036, 0x40036 },           /* PM_BR_2PATH */
 508         { 0x200f2, 0x300f2 },           /* PM_INST_DISP */
 509         { 0x200f4, 0x600f4 },           /* PM_RUN_CYC */
 510         { 0x2013c, 0x3012e },           /* PM_MRK_FILT_MATCH */
 511         { 0x3e054, 0x400f0 },           /* PM_LD_MISS_L1 */
 512         { 0x400fa, 0x500fa },           /* PM_RUN_INST_CMPL */
 513 };
 514
 515 /*
 516  * Scan the alternatives table for a match and return the
 517  * index into the alternatives table if found, else -1.
 518  */
 519 static int find_alternative(u64 event)
 520 {
 521         int i, j;
 522
 523         for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
 524                 if (event < event_alternatives[i][0])
 525                         break;
 526
 527                 for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
 528                         if (event == event_alternatives[i][j])
 529                                 return i;
 530         }
 531
 532         return -1;
 533 }
 534
 535 static int power8_get_alternatives(u64 event, unsigned int flags, u64 alt[])
 536 {
 537         int i, j, num_alt = 0;
 538         u64 alt_event;
 539
 540         alt[num_alt++] = event;
 541
 542         i = find_alternative(event);
 543         if (i >= 0) {
 544                 /* Filter out the original event, it's already in alt[0] */
 545                 for (j = 0; j < MAX_ALT; ++j) {
 546                         alt_event = event_alternatives[i][j];
 547                         if (alt_event && alt_event != event)
 548                                 alt[num_alt++] = alt_event;
 549                 }
 550         }
 551
 552         if (flags & PPMU_ONLY_COUNT_RUN) {
 553                 /*
 554                  * We're only counting in RUN state, so PM_CYC is equivalent to
 555                  * PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL.
 556                  */
 557                 j = num_alt;
 558                 for (i = 0; i < num_alt; ++i) {
 559                         switch (alt[i]) {
 560                         case 0x1e:      /* PM_CYC */
 561                                 alt[j++] = 0x600f4;     /* PM_RUN_CYC */
 562                                 break;
 563                         case 0x600f4:   /* PM_RUN_CYC */
 564                                 alt[j++] = 0x1e;
 565                                 break;
 566                         case 0x2:       /* PM_PPC_CMPL */
 567                                 alt[j++] = 0x500fa;     /* PM_RUN_INST_CMPL */
 568                                 break;
 569                         case 0x500fa:   /* PM_RUN_INST_CMPL */
 570                                 alt[j++] = 0x2; /* PM_PPC_CMPL */
 571                                 break;
 572                         }
 573                 }
 574                 num_alt = j;
 575         }
 576
 577         return num_alt;
 578 }
 579
 580 static void power8_disable_pmc(unsigned int pmc, unsigned long mmcr[])
 581 {
 582         if (pmc <= 3)
 583                 mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
 584 }
 585
 586 PMU_FORMAT_ATTR(event,          "config:0-49");
 587 PMU_FORMAT_ATTR(pmcxsel,        "config:0-7");
 588 PMU_FORMAT_ATTR(mark,           "config:8");
 589 PMU_FORMAT_ATTR(combine,        "config:11");
 590 PMU_FORMAT_ATTR(unit,           "config:12-15");
 591 PMU_FORMAT_ATTR(pmc,            "config:16-19");
 592 PMU_FORMAT_ATTR(cache_sel,      "config:20-23");
 593 PMU_FORMAT_ATTR(sample_mode,    "config:24-28");
 594 PMU_FORMAT_ATTR(thresh_sel,     "config:29-31");
 595 PMU_FORMAT_ATTR(thresh_stop,    "config:32-35");
 596 PMU_FORMAT_ATTR(thresh_start,   "config:36-39");
 597 PMU_FORMAT_ATTR(thresh_cmp,     "config:40-49");
 598
 599 static struct attribute *power8_pmu_format_attr[] = {
 600         &format_attr_event.attr,
 601         &format_attr_pmcxsel.attr,
 602         &format_attr_mark.attr,
 603         &format_attr_combine.attr,
 604         &format_attr_unit.attr,
 605         &format_attr_pmc.attr,
 606         &format_attr_cache_sel.attr,
 607         &format_attr_sample_mode.attr,
 608         &format_attr_thresh_sel.attr,
 609         &format_attr_thresh_stop.attr,
 610         &format_attr_thresh_start.attr,
 611         &format_attr_thresh_cmp.attr,
 612         NULL,
 613 };
 614
 615 struct attribute_group power8_pmu_format_group = {
 616         .name = "format",
 617         .attrs = power8_pmu_format_attr,
 618 };
 619
 620 static const struct attribute_group *power8_pmu_attr_groups[] = {
 621         &power8_pmu_format_group,
 622         NULL,
 623 };
 624
 625 static int power8_generic_events[] = {
 626         [PERF_COUNT_HW_CPU_CYCLES] =                    PM_CYC,
 627         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =       PM_GCT_NOSLOT_CYC,
 628         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =        PM_CMPLU_STALL,
 629         [PERF_COUNT_HW_INSTRUCTIONS] =                  PM_INST_CMPL,
 630         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =           PM_BRU_FIN,
 631         [PERF_COUNT_HW_BRANCH_MISSES] =                 PM_BR_MPRED_CMPL,
 632         [PERF_COUNT_HW_CACHE_REFERENCES] =              PM_LD_REF_L1,
 633         [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1,
 634 };
 635
 636 static u64 power8_bhrb_filter_map(u64 branch_sample_type)
 637 {
 638         u64 pmu_bhrb_filter = 0;
 639
 640         /* BHRB and regular PMU events share the same privilege state
 641          * filter configuration. BHRB is always recorded along with a
 642          * regular PMU event. As the privilege state filter is handled
 643          * in the basic PMC configuration of the accompanying regular
 644          * PMU event, we ignore any separate BHRB specific request.
 645          */
 646
 647         /* No branch filter requested */
 648         if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
 649                 return pmu_bhrb_filter;
 650
 651         /* Invalid branch filter options - HW does not support */
 652         if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
 653                 return -1;
 654
 655         if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
 656                 return -1;
 657
 658         if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
 659                 pmu_bhrb_filter |= POWER8_MMCRA_IFM1;
 660                 return pmu_bhrb_filter;
 661         }
 662
 663         /* Every thing else is unsupported */
 664         return -1;
 665 }
 666
 667 static void power8_config_bhrb(u64 pmu_bhrb_filter)
 668 {
 669         /* Enable BHRB filter in PMU */
 670         mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
 671 }
 672
 673 #define C(x)    PERF_COUNT_HW_CACHE_##x
 674
 675 /*
 676  * Table of generalized cache-related events.
 677  * 0 means not supported, -1 means nonsensical, other values
 678  * are event codes.
 679  */
 680 static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 681         [ C(L1D) ] = {
 682                 [ C(OP_READ) ] = {
 683                         [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
 684                         [ C(RESULT_MISS)   ] = PM_LD_MISS_L1,
 685                 },
 686                 [ C(OP_WRITE) ] = {
 687                         [ C(RESULT_ACCESS) ] = 0,
 688                         [ C(RESULT_MISS)   ] = PM_ST_MISS_L1,
 689                 },
 690                 [ C(OP_PREFETCH) ] = {
 691                         [ C(RESULT_ACCESS) ] = PM_L1_PREF,
 692                         [ C(RESULT_MISS)   ] = 0,
 693                 },
 694         },
 695         [ C(L1I) ] = {
 696                 [ C(OP_READ) ] = {
 697                         [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
 698                         [ C(RESULT_MISS)   ] = PM_L1_ICACHE_MISS,
 699                 },
 700                 [ C(OP_WRITE) ] = {
 701                         [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
 702                         [ C(RESULT_MISS)   ] = -1,
 703                 },
 704                 [ C(OP_PREFETCH) ] = {
 705                         [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
 706                         [ C(RESULT_MISS)   ] = 0,
 707                 },
 708         },
 709         [ C(LL) ] = {
 710                 [ C(OP_READ) ] = {
 711                         [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
 712                         [ C(RESULT_MISS)   ] = PM_DATA_FROM_L3MISS,
 713                 },
 714                 [ C(OP_WRITE) ] = {
 715                         [ C(RESULT_ACCESS) ] = PM_L2_ST,
 716                         [ C(RESULT_MISS)   ] = PM_L2_ST_MISS,
 717                 },
 718                 [ C(OP_PREFETCH) ] = {
 719                         [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
 720                         [ C(RESULT_MISS)   ] = 0,
 721                 },
 722         },
 723         [ C(DTLB) ] = {
 724                 [ C(OP_READ) ] = {
 725                         [ C(RESULT_ACCESS) ] = 0,
 726                         [ C(RESULT_MISS)   ] = PM_DTLB_MISS,
 727                 },
 728                 [ C(OP_WRITE) ] = {
 729                         [ C(RESULT_ACCESS) ] = -1,
 730                         [ C(RESULT_MISS)   ] = -1,
 731                 },
 732                 [ C(OP_PREFETCH) ] = {
 733                         [ C(RESULT_ACCESS) ] = -1,
 734                         [ C(RESULT_MISS)   ] = -1,
 735                 },
 736         },
 737         [ C(ITLB) ] = {
 738                 [ C(OP_READ) ] = {
 739                         [ C(RESULT_ACCESS) ] = 0,
 740                         [ C(RESULT_MISS)   ] = PM_ITLB_MISS,
 741                 },
 742                 [ C(OP_WRITE) ] = {
 743                         [ C(RESULT_ACCESS) ] = -1,
 744                         [ C(RESULT_MISS)   ] = -1,
 745                 },
 746                 [ C(OP_PREFETCH) ] = {
 747                         [ C(RESULT_ACCESS) ] = -1,
 748                         [ C(RESULT_MISS)   ] = -1,
 749                 },
 750         },
 751         [ C(BPU) ] = {
 752                 [ C(OP_READ) ] = {
 753                         [ C(RESULT_ACCESS) ] = PM_BRU_FIN,
 754                         [ C(RESULT_MISS)   ] = PM_BR_MPRED_CMPL,
 755                 },
 756                 [ C(OP_WRITE) ] = {
 757                         [ C(RESULT_ACCESS) ] = -1,
 758                         [ C(RESULT_MISS)   ] = -1,
 759                 },
 760                 [ C(OP_PREFETCH) ] = {
 761                         [ C(RESULT_ACCESS) ] = -1,
 762                         [ C(RESULT_MISS)   ] = -1,
 763                 },
 764         },
 765         [ C(NODE) ] = {
 766                 [ C(OP_READ) ] = {
 767                         [ C(RESULT_ACCESS) ] = -1,
 768                         [ C(RESULT_MISS)   ] = -1,
 769                 },
 770                 [ C(OP_WRITE) ] = {
 771                         [ C(RESULT_ACCESS) ] = -1,
 772                         [ C(RESULT_MISS)   ] = -1,
 773                 },
 774                 [ C(OP_PREFETCH) ] = {
 775                         [ C(RESULT_ACCESS) ] = -1,
 776                         [ C(RESULT_MISS)   ] = -1,
 777                 },
 778         },
 779 };
 780
 781 #undef C
 782
 783 static struct power_pmu power8_pmu = {
 784         .name                   = "POWER8",
 785         .n_counter              = 6,
 786         .max_alternatives       = MAX_ALT + 1,
 787         .add_fields             = POWER8_ADD_FIELDS,
 788         .test_adder             = POWER8_TEST_ADDER,
 789         .compute_mmcr           = power8_compute_mmcr,
 790         .config_bhrb            = power8_config_bhrb,
 791         .bhrb_filter_map        = power8_bhrb_filter_map,
 792         .get_constraint         = power8_get_constraint,
 793         .get_alternatives       = power8_get_alternatives,
 794         .disable_pmc            = power8_disable_pmc,
 795         .flags                  = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_BHRB | PPMU_EBB,
 796         .n_generic              = ARRAY_SIZE(power8_generic_events),
 797         .generic_events         = power8_generic_events,
 798         .cache_events           = &power8_cache_events,
 799         .attr_groups            = power8_pmu_attr_groups,
 800         .bhrb_nr                = 32,
 801 };
 802
 803 static int __init init_power8_pmu(void)
 804 {
 805         int rc;
 806
 807         if (!cur_cpu_spec->oprofile_cpu_type ||
 808             strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power8"))
 809                 return -ENODEV;
 810
 811         rc = register_power_pmu(&power8_pmu);
 812         if (rc)
 813                 return rc;
 814
 815         /* Tell userspace that EBB is supported */
 816         cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
 817
 818         if (cpu_has_feature(CPU_FTR_PMAO_BUG))
 819                 pr_info("PMAO restore workaround active.\n");
 820
 821         return 0;
 822 }
 823 early_initcall(init_power8_pmu);