sound/soc/samsung/ac97.c

   1 /* sound/soc/samsung/ac97.c
   2  *
   3  * ALSA SoC Audio Layer - S3C AC97 Controller driver
   4  *      Evolved from s3c2443-ac97.c
   5  *
   6  * Copyright (c) 2010 Samsung Electronics Co. Ltd
   7  *      Author: Jaswinder Singh <jassisinghbrar@gmail.com>
   8  *      Credits: Graeme Gregory, Sean Choi
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/io.h>
  16 #include <linux/delay.h>
  17 #include <linux/clk.h>
  18 #include <linux/module.h>
  19
  20 #include <sound/soc.h>
  21
  22 #include <mach/dma.h>
  23 #include "regs-ac97.h"
  24 #include <linux/platform_data/asoc-s3c.h>
  25
  26 #include "dma.h"
  27
  28 #define AC_CMD_ADDR(x) (x << 16)
  29 #define AC_CMD_DATA(x) (x & 0xffff)
  30
  31 #define S3C_AC97_DAI_PCM 0
  32 #define S3C_AC97_DAI_MIC 1
  33
  34 struct s3c_ac97_info {
  35         struct clk         *ac97_clk;
  36         void __iomem       *regs;
  37         struct mutex       lock;
  38         struct completion  done;
  39 };
  40 static struct s3c_ac97_info s3c_ac97;
  41
  42 static struct s3c_dma_client s3c_dma_client_out = {
  43         .name = "AC97 PCMOut"
  44 };
  45
  46 static struct s3c_dma_client s3c_dma_client_in = {
  47         .name = "AC97 PCMIn"
  48 };
  49
  50 static struct s3c_dma_client s3c_dma_client_micin = {
  51         .name = "AC97 MicIn"
  52 };
  53
  54 static struct s3c_dma_params s3c_ac97_pcm_out = {
  55         .client         = &s3c_dma_client_out,
  56         .dma_size       = 4,
  57 };
  58
  59 static struct s3c_dma_params s3c_ac97_pcm_in = {
  60         .client         = &s3c_dma_client_in,
  61         .dma_size       = 4,
  62 };
  63
  64 static struct s3c_dma_params s3c_ac97_mic_in = {
  65         .client         = &s3c_dma_client_micin,
  66         .dma_size       = 4,
  67 };
  68
  69 static void s3c_ac97_activate(struct snd_ac97 *ac97)
  70 {
  71         u32 ac_glbctrl, stat;
  72
  73         stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
  74         if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
  75                 return; /* Return if already active */
  76
  77         reinit_completion(&s3c_ac97.done);
  78
  79         ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
  80         ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
  81         writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  82         msleep(1);
  83
  84         ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
  85         writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  86         msleep(1);
  87
  88         ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
  89         ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
  90         writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  91
  92         if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
  93                 pr_err("AC97: Unable to activate!");
  94 }
  95
  96 static unsigned short s3c_ac97_read(struct snd_ac97 *ac97,
  97         unsigned short reg)
  98 {
  99         u32 ac_glbctrl, ac_codec_cmd;
 100         u32 stat, addr, data;
 101
 102         mutex_lock(&s3c_ac97.lock);
 103
 104         s3c_ac97_activate(ac97);
 105
 106         reinit_completion(&s3c_ac97.done);
 107
 108         ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
 109         ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
 110         writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
 111
 112         udelay(50);
 113
 114         ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
 115         ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
 116         writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
 117
 118         if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
 119                 pr_err("AC97: Unable to read!");
 120
 121         stat = readl(s3c_ac97.regs + S3C_AC97_STAT);
 122         addr = (stat >> 16) & 0x7f;
 123         data = (stat & 0xffff);
 124
 125         if (addr != reg)
 126                 pr_err("ac97: req addr = %02x, rep addr = %02x\n",
 127                         reg, addr);
 128
 129         mutex_unlock(&s3c_ac97.lock);
 130
 131         return (unsigned short)data;
 132 }
 133
 134 static void s3c_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
 135         unsigned short val)
 136 {
 137         u32 ac_glbctrl, ac_codec_cmd;
 138
 139         mutex_lock(&s3c_ac97.lock);
 140
 141         s3c_ac97_activate(ac97);
 142
 143         reinit_completion(&s3c_ac97.done);
 144
 145         ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
 146         ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
 147         writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
 148
 149         udelay(50);
 150
 151         ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
 152         ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
 153         writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
 154
 155         if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
 156                 pr_err("AC97: Unable to write!");
 157
 158         ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
 159         ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
 160         writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
 161
 162         mutex_unlock(&s3c_ac97.lock);
 163 }
 164
 165 static void s3c_ac97_cold_reset(struct snd_ac97 *ac97)
 166 {
 167         pr_debug("AC97: Cold reset\n");
 168         writel(S3C_AC97_GLBCTRL_COLDRESET,
 169                         s3c_ac97.regs + S3C_AC97_GLBCTRL);
 170         msleep(1);
 171
 172         writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
 173         msleep(1);
 174 }
 175
 176 static void s3c_ac97_warm_reset(struct snd_ac97 *ac97)
 177 {
 178         u32 stat;
 179
 180         stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
 181         if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
 182                 return; /* Return if already active */
 183
 184         pr_debug("AC97: Warm reset\n");
 185
 186         writel(S3C_AC97_GLBCTRL_WARMRESET, s3c_ac97.regs + S3C_AC97_GLBCTRL);
 187         msleep(1);
 188
 189         writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
 190         msleep(1);
 191
 192         s3c_ac97_activate(ac97);
 193 }
 194
 195 static irqreturn_t s3c_ac97_irq(int irq, void *dev_id)
 196 {
 197         u32 ac_glbctrl, ac_glbstat;
 198
 199         ac_glbstat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT);
 200
 201         if (ac_glbstat & S3C_AC97_GLBSTAT_CODECREADY) {
 202
 203                 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
 204                 ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
 205                 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
 206
 207                 complete(&s3c_ac97.done);
 208         }
 209
 210         ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
 211         ac_glbctrl |= (1<<30); /* Clear interrupt */
 212         writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
 213
 214         return IRQ_HANDLED;
 215 }
 216
 217 static struct snd_ac97_bus_ops s3c_ac97_ops = {
 218         .read       = s3c_ac97_read,
 219         .write      = s3c_ac97_write,
 220         .warm_reset = s3c_ac97_warm_reset,
 221         .reset      = s3c_ac97_cold_reset,
 222 };
 223
 224 static int s3c_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
 225                                 struct snd_soc_dai *dai)
 226 {
 227         u32 ac_glbctrl;
 228         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 229         struct s3c_dma_params *dma_data =
 230                 snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
 231
 232         ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
 233         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 234                 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
 235         else
 236                 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
 237
 238         switch (cmd) {
 239         case SNDRV_PCM_TRIGGER_START:
 240         case SNDRV_PCM_TRIGGER_RESUME:
 241         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 242                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 243                         ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
 244                 else
 245                         ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
 246                 break;
 247
 248         case SNDRV_PCM_TRIGGER_STOP:
 249         case SNDRV_PCM_TRIGGER_SUSPEND:
 250         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 251                 break;
 252         }
 253
 254         writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
 255
 256         if (!dma_data->ops)
 257                 dma_data->ops = samsung_dma_get_ops();
 258
 259         dma_data->ops->started(dma_data->channel);
 260
 261         return 0;
 262 }
 263
 264 static int s3c_ac97_mic_trigger(struct snd_pcm_substream *substream,
 265                                     int cmd, struct snd_soc_dai *dai)
 266 {
 267         u32 ac_glbctrl;
 268         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 269         struct s3c_dma_params *dma_data =
 270                 snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
 271
 272         ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
 273         ac_glbctrl &= ~S3C_AC97_GLBCTRL_MICINTM_MASK;
 274
 275         switch (cmd) {
 276         case SNDRV_PCM_TRIGGER_START:
 277         case SNDRV_PCM_TRIGGER_RESUME:
 278         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 279                 ac_glbctrl |= S3C_AC97_GLBCTRL_MICINTM_DMA;
 280                 break;
 281
 282         case SNDRV_PCM_TRIGGER_STOP:
 283         case SNDRV_PCM_TRIGGER_SUSPEND:
 284         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 285                 break;
 286         }
 287
 288         writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
 289
 290         if (!dma_data->ops)
 291                 dma_data->ops = samsung_dma_get_ops();
 292
 293         dma_data->ops->started(dma_data->channel);
 294
 295         return 0;
 296 }
 297
 298 static const struct snd_soc_dai_ops s3c_ac97_dai_ops = {
 299         .trigger        = s3c_ac97_trigger,
 300 };
 301
 302 static const struct snd_soc_dai_ops s3c_ac97_mic_dai_ops = {
 303         .trigger        = s3c_ac97_mic_trigger,
 304 };
 305
 306 static int s3c_ac97_dai_probe(struct snd_soc_dai *dai)
 307 {
 308         samsung_asoc_init_dma_data(dai, &s3c_ac97_pcm_out, &s3c_ac97_pcm_in);
 309
 310         return 0;
 311 }
 312
 313 static int s3c_ac97_mic_dai_probe(struct snd_soc_dai *dai)
 314 {
 315         samsung_asoc_init_dma_data(dai, NULL, &s3c_ac97_mic_in);
 316
 317         return 0;
 318 }
 319
 320 static struct snd_soc_dai_driver s3c_ac97_dai[] = {
 321         [S3C_AC97_DAI_PCM] = {
 322                 .name = "samsung-ac97",
 323                 .ac97_control = 1,
 324                 .playback = {
 325                         .stream_name = "AC97 Playback",
 326                         .channels_min = 2,
 327                         .channels_max = 2,
 328                         .rates = SNDRV_PCM_RATE_8000_48000,
 329                         .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 330                 .capture = {
 331                         .stream_name = "AC97 Capture",
 332                         .channels_min = 2,
 333                         .channels_max = 2,
 334                         .rates = SNDRV_PCM_RATE_8000_48000,
 335                         .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 336                 .probe = s3c_ac97_dai_probe,
 337                 .ops = &s3c_ac97_dai_ops,
 338         },
 339         [S3C_AC97_DAI_MIC] = {
 340                 .name = "samsung-ac97-mic",
 341                 .ac97_control = 1,
 342                 .capture = {
 343                         .stream_name = "AC97 Mic Capture",
 344                         .channels_min = 1,
 345                         .channels_max = 1,
 346                         .rates = SNDRV_PCM_RATE_8000_48000,
 347                         .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 348                 .probe = s3c_ac97_mic_dai_probe,
 349                 .ops = &s3c_ac97_mic_dai_ops,
 350         },
 351 };
 352
 353 static const struct snd_soc_component_driver s3c_ac97_component = {
 354         .name           = "s3c-ac97",
 355 };
 356
 357 static int s3c_ac97_probe(struct platform_device *pdev)
 358 {
 359         struct resource *mem_res, *dmatx_res, *dmarx_res, *dmamic_res, *irq_res;
 360         struct s3c_audio_pdata *ac97_pdata;
 361         int ret;
 362
 363         ac97_pdata = pdev->dev.platform_data;
 364         if (!ac97_pdata || !ac97_pdata->cfg_gpio) {
 365                 dev_err(&pdev->dev, "cfg_gpio callback not provided!\n");
 366                 return -EINVAL;
 367         }
 368
 369         /* Check for availability of necessary resource */
 370         dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 371         if (!dmatx_res) {
 372                 dev_err(&pdev->dev, "Unable to get AC97-TX dma resource\n");
 373                 return -ENXIO;
 374         }
 375
 376         dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
 377         if (!dmarx_res) {
 378                 dev_err(&pdev->dev, "Unable to get AC97-RX dma resource\n");
 379                 return -ENXIO;
 380         }
 381
 382         dmamic_res = platform_get_resource(pdev, IORESOURCE_DMA, 2);
 383         if (!dmamic_res) {
 384                 dev_err(&pdev->dev, "Unable to get AC97-MIC dma resource\n");
 385                 return -ENXIO;
 386         }
 387
 388         irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 389         if (!irq_res) {
 390                 dev_err(&pdev->dev, "AC97 IRQ not provided!\n");
 391                 return -ENXIO;
 392         }
 393
 394         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 395         s3c_ac97.regs = devm_ioremap_resource(&pdev->dev, mem_res);
 396         if (IS_ERR(s3c_ac97.regs))
 397                 return PTR_ERR(s3c_ac97.regs);
 398
 399         s3c_ac97_pcm_out.channel = dmatx_res->start;
 400         s3c_ac97_pcm_out.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
 401         s3c_ac97_pcm_in.channel = dmarx_res->start;
 402         s3c_ac97_pcm_in.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
 403         s3c_ac97_mic_in.channel = dmamic_res->start;
 404         s3c_ac97_mic_in.dma_addr = mem_res->start + S3C_AC97_MIC_DATA;
 405
 406         init_completion(&s3c_ac97.done);
 407         mutex_init(&s3c_ac97.lock);
 408
 409         s3c_ac97.ac97_clk = devm_clk_get(&pdev->dev, "ac97");
 410         if (IS_ERR(s3c_ac97.ac97_clk)) {
 411                 dev_err(&pdev->dev, "ac97 failed to get ac97_clock\n");
 412                 ret = -ENODEV;
 413                 goto err2;
 414         }
 415         clk_prepare_enable(s3c_ac97.ac97_clk);
 416
 417         if (ac97_pdata->cfg_gpio(pdev)) {
 418                 dev_err(&pdev->dev, "Unable to configure gpio\n");
 419                 ret = -EINVAL;
 420                 goto err3;
 421         }
 422
 423         ret = request_irq(irq_res->start, s3c_ac97_irq,
 424                                         0, "AC97", NULL);
 425         if (ret < 0) {
 426                 dev_err(&pdev->dev, "ac97: interrupt request failed.\n");
 427                 goto err4;
 428         }
 429
 430         ret = snd_soc_set_ac97_ops(&s3c_ac97_ops);
 431         if (ret != 0) {
 432                 dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
 433                 goto err4;
 434         }
 435
 436         ret = devm_snd_soc_register_component(&pdev->dev, &s3c_ac97_component,
 437                                          s3c_ac97_dai, ARRAY_SIZE(s3c_ac97_dai));
 438         if (ret)
 439                 goto err5;
 440
 441         ret = samsung_asoc_dma_platform_register(&pdev->dev);
 442         if (ret) {
 443                 dev_err(&pdev->dev, "failed to get register DMA: %d\n", ret);
 444                 goto err5;
 445         }
 446
 447         return 0;
 448 err5:
 449         free_irq(irq_res->start, NULL);
 450 err4:
 451 err3:
 452         clk_disable_unprepare(s3c_ac97.ac97_clk);
 453 err2:
 454         snd_soc_set_ac97_ops(NULL);
 455         return ret;
 456 }
 457
 458 static int s3c_ac97_remove(struct platform_device *pdev)
 459 {
 460         struct resource *irq_res;
 461
 462         irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 463         if (irq_res)
 464                 free_irq(irq_res->start, NULL);
 465
 466         clk_disable_unprepare(s3c_ac97.ac97_clk);
 467         snd_soc_set_ac97_ops(NULL);
 468
 469         return 0;
 470 }
 471
 472 static struct platform_driver s3c_ac97_driver = {
 473         .probe  = s3c_ac97_probe,
 474         .remove = s3c_ac97_remove,
 475         .driver = {
 476                 .name = "samsung-ac97",
 477                 .owner = THIS_MODULE,
 478         },
 479 };
 480
 481 module_platform_driver(s3c_ac97_driver);
 482
 483 MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
 484 MODULE_DESCRIPTION("AC97 driver for the Samsung SoC");
 485 MODULE_LICENSE("GPL");
 486 MODULE_ALIAS("platform:samsung-ac97");