arch/mips/kernel/irq-gic.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
   7  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
   8  */
   9 #include <linux/bitmap.h>
  10 #include <linux/init.h>
  11 #include <linux/smp.h>
  12 #include <linux/irq.h>
  13
  14 #include <asm/io.h>
  15 #include <asm/gic.h>
  16 #include <asm/setup.h>
  17 #include <asm/traps.h>
  18 #include <asm/gcmpregs.h>
  19 #include <linux/hardirq.h>
  20 #include <asm-generic/bitops/find.h>
  21
  22 unsigned long _gic_base;
  23 unsigned int gic_irq_base;
  24 unsigned int gic_irq_flags[GIC_NUM_INTRS];
  25
  26 /* The index into this array is the vector # of the interrupt. */
  27 struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS];
  28
  29 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
  30 static struct gic_pending_regs pending_regs[NR_CPUS];
  31 static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
  32
  33 unsigned int gic_get_timer_pending(void)
  34 {
  35         unsigned int vpe_pending;
  36
  37         GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0);
  38         GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_PEND), vpe_pending);
  39         return (vpe_pending & GIC_VPE_PEND_TIMER_MSK);
  40 }
  41
  42 void gic_bind_eic_interrupt(int irq, int set)
  43 {
  44         /* Convert irq vector # to hw int # */
  45         irq -= GIC_PIN_TO_VEC_OFFSET;
  46
  47         /* Set irq to use shadow set */
  48         GICWRITE(GIC_REG_ADDR(VPE_LOCAL, GIC_VPE_EIC_SS(irq)), set);
  49 }
  50
  51 void gic_send_ipi(unsigned int intr)
  52 {
  53         GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
  54 }
  55
  56 static void gic_eic_irq_dispatch(void)
  57 {
  58         unsigned int cause = read_c0_cause();
  59         int irq;
  60
  61         irq = (cause & ST0_IM) >> STATUSB_IP2;
  62         if (irq == 0)
  63                 irq = -1;
  64
  65         if (irq >= 0)
  66                 do_IRQ(gic_irq_base + irq);
  67         else
  68                 spurious_interrupt();
  69 }
  70
  71 static void __init vpe_local_setup(unsigned int numvpes)
  72 {
  73         unsigned long timer_intr = GIC_INT_TMR;
  74         unsigned long perf_intr = GIC_INT_PERFCTR;
  75         unsigned int vpe_ctl;
  76         int i;
  77
  78         if (cpu_has_veic) {
  79                 /*
  80                  * GIC timer interrupt -> CPU HW Int X (vector X+2) ->
  81                  * map to pin X+2-1 (since GIC adds 1)
  82                  */
  83                 timer_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
  84                 /*
  85                  * GIC perfcnt interrupt -> CPU HW Int X (vector X+2) ->
  86                  * map to pin X+2-1 (since GIC adds 1)
  87                  */
  88                 perf_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
  89         }
  90
  91         /*
  92          * Setup the default performance counter timer interrupts
  93          * for all VPEs
  94          */
  95         for (i = 0; i < numvpes; i++) {
  96                 GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
  97
  98                 /* Are Interrupts locally routable? */
  99                 GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
 100                 if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
 101                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
 102                                  GIC_MAP_TO_PIN_MSK | timer_intr);
 103                 if (cpu_has_veic) {
 104                         set_vi_handler(timer_intr + GIC_PIN_TO_VEC_OFFSET,
 105                                 gic_eic_irq_dispatch);
 106                         gic_shared_intr_map[timer_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_TIMER_MSK;
 107                 }
 108
 109                 if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
 110                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
 111                                  GIC_MAP_TO_PIN_MSK | perf_intr);
 112                 if (cpu_has_veic) {
 113                         set_vi_handler(perf_intr + GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch);
 114                         gic_shared_intr_map[perf_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_PERFCNT_MSK;
 115                 }
 116         }
 117 }
 118
 119 unsigned int gic_get_int(void)
 120 {
 121         unsigned int i;
 122         unsigned long *pending, *intrmask, *pcpu_mask;
 123         unsigned long *pending_abs, *intrmask_abs;
 124
 125         /* Get per-cpu bitmaps */
 126         pending = pending_regs[smp_processor_id()].pending;
 127         intrmask = intrmask_regs[smp_processor_id()].intrmask;
 128         pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
 129
 130         pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
 131                                                          GIC_SH_PEND_31_0_OFS);
 132         intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
 133                                                           GIC_SH_MASK_31_0_OFS);
 134
 135         for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
 136                 GICREAD(*pending_abs, pending[i]);
 137                 GICREAD(*intrmask_abs, intrmask[i]);
 138                 pending_abs++;
 139                 intrmask_abs++;
 140         }
 141
 142         bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
 143         bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
 144
 145         return find_first_bit(pending, GIC_NUM_INTRS);
 146 }
 147
 148 static void gic_mask_irq(struct irq_data *d)
 149 {
 150         GIC_CLR_INTR_MASK(d->irq - gic_irq_base);
 151 }
 152
 153 static void gic_unmask_irq(struct irq_data *d)
 154 {
 155         GIC_SET_INTR_MASK(d->irq - gic_irq_base);
 156 }
 157
 158 #ifdef CONFIG_SMP
 159 static DEFINE_SPINLOCK(gic_lock);
 160
 161 static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
 162                             bool force)
 163 {
 164         unsigned int irq = (d->irq - gic_irq_base);
 165         cpumask_t       tmp = CPU_MASK_NONE;
 166         unsigned long   flags;
 167         int             i;
 168
 169         cpumask_and(&tmp, cpumask, cpu_online_mask);
 170         if (cpus_empty(tmp))
 171                 return -1;
 172
 173         /* Assumption : cpumask refers to a single CPU */
 174         spin_lock_irqsave(&gic_lock, flags);
 175         for (;;) {
 176                 /* Re-route this IRQ */
 177                 GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
 178
 179                 /* Update the pcpu_masks */
 180                 for (i = 0; i < NR_CPUS; i++)
 181                         clear_bit(irq, pcpu_masks[i].pcpu_mask);
 182                 set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
 183
 184         }
 185         cpumask_copy(d->affinity, cpumask);
 186         spin_unlock_irqrestore(&gic_lock, flags);
 187
 188         return IRQ_SET_MASK_OK_NOCOPY;
 189 }
 190 #endif
 191
 192 static struct irq_chip gic_irq_controller = {
 193         .name                   =       "MIPS GIC",
 194         .irq_ack                =       gic_irq_ack,
 195         .irq_mask               =       gic_mask_irq,
 196         .irq_mask_ack           =       gic_mask_irq,
 197         .irq_unmask             =       gic_unmask_irq,
 198         .irq_eoi                =       gic_finish_irq,
 199 #ifdef CONFIG_SMP
 200         .irq_set_affinity       =       gic_set_affinity,
 201 #endif
 202 };
 203
 204 static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
 205         unsigned int pin, unsigned int polarity, unsigned int trigtype,
 206         unsigned int flags)
 207 {
 208         struct gic_shared_intr_map *map_ptr;
 209
 210         /* Setup Intr to Pin mapping */
 211         if (pin & GIC_MAP_TO_NMI_MSK) {
 212                 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
 213                 /* FIXME: hack to route NMI to all cpu's */
 214                 for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
 215                         GICWRITE(GIC_REG_ADDR(SHARED,
 216                                           GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
 217                                  0xffffffff);
 218                 }
 219         } else {
 220                 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
 221                          GIC_MAP_TO_PIN_MSK | pin);
 222                 /* Setup Intr to CPU mapping */
 223                 GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
 224                 if (cpu_has_veic) {
 225                         set_vi_handler(pin + GIC_PIN_TO_VEC_OFFSET,
 226                                 gic_eic_irq_dispatch);
 227                         map_ptr = &gic_shared_intr_map[pin + GIC_PIN_TO_VEC_OFFSET];
 228                         if (map_ptr->num_shared_intr >= GIC_MAX_SHARED_INTR)
 229                                 BUG();
 230                         map_ptr->intr_list[map_ptr->num_shared_intr++] = intr;
 231                 }
 232         }
 233
 234         /* Setup Intr Polarity */
 235         GIC_SET_POLARITY(intr, polarity);
 236
 237         /* Setup Intr Trigger Type */
 238         GIC_SET_TRIGGER(intr, trigtype);
 239
 240         /* Init Intr Masks */
 241         GIC_CLR_INTR_MASK(intr);
 242         /* Initialise per-cpu Interrupt software masks */
 243         if (flags & GIC_FLAG_IPI)
 244                 set_bit(intr, pcpu_masks[cpu].pcpu_mask);
 245         if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0))
 246                 GIC_SET_INTR_MASK(intr);
 247         if (trigtype == GIC_TRIG_EDGE)
 248                 gic_irq_flags[intr] |= GIC_TRIG_EDGE;
 249 }
 250
 251 static void __init gic_basic_init(int numintrs, int numvpes,
 252                         struct gic_intr_map *intrmap, int mapsize)
 253 {
 254         unsigned int i, cpu;
 255         unsigned int pin_offset = 0;
 256
 257         board_bind_eic_interrupt = &gic_bind_eic_interrupt;
 258
 259         /* Setup defaults */
 260         for (i = 0; i < numintrs; i++) {
 261                 GIC_SET_POLARITY(i, GIC_POL_POS);
 262                 GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
 263                 GIC_CLR_INTR_MASK(i);
 264                 if (i < GIC_NUM_INTRS) {
 265                         gic_irq_flags[i] = 0;
 266                         gic_shared_intr_map[i].num_shared_intr = 0;
 267                         gic_shared_intr_map[i].local_intr_mask = 0;
 268                 }
 269         }
 270
 271         /*
 272          * In EIC mode, the HW_INT# is offset by (2-1). Need to subtract
 273          * one because the GIC will add one (since 0=no intr).
 274          */
 275         if (cpu_has_veic)
 276                 pin_offset = (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
 277
 278         /* Setup specifics */
 279         for (i = 0; i < mapsize; i++) {
 280                 cpu = intrmap[i].cpunum;
 281                 if (cpu == GIC_UNUSED)
 282                         continue;
 283                 if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
 284                         continue;
 285                 gic_setup_intr(i,
 286                         intrmap[i].cpunum,
 287                         intrmap[i].pin + pin_offset,
 288                         intrmap[i].polarity,
 289                         intrmap[i].trigtype,
 290                         intrmap[i].flags);
 291         }
 292
 293         vpe_local_setup(numvpes);
 294 }
 295
 296 void __init gic_init(unsigned long gic_base_addr,
 297                      unsigned long gic_addrspace_size,
 298                      struct gic_intr_map *intr_map, unsigned int intr_map_size,
 299                      unsigned int irqbase)
 300 {
 301         unsigned int gicconfig;
 302         int numvpes, numintrs;
 303
 304         _gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
 305                                                     gic_addrspace_size);
 306         gic_irq_base = irqbase;
 307
 308         GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
 309         numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
 310                    GIC_SH_CONFIG_NUMINTRS_SHF;
 311         numintrs = ((numintrs + 1) * 8);
 312
 313         numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
 314                   GIC_SH_CONFIG_NUMVPES_SHF;
 315         numvpes = numvpes + 1;
 316
 317         gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
 318
 319         gic_platform_init(numintrs, &gic_irq_controller);
 320 }