1 /*******************************************************************************
4 Copyright(c) 2012 EZchip Technologies.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 The full GNU General Public License is included in this distribution in
16 the file called "COPYING".
18 *******************************************************************************/
19 #include <linux/linkage.h>
20 #include <asm/entry.h>
21 #include <asm/cache.h>
22 #include <plat/ctop.h>
26 .section .init.text, "ax",@progbits
27 .align 1024 ; HW requierment for restart first PC
30 #ifdef CONFIG_EZNPS_MTM_EXT
31 ; There is no work for HW thread id != 0
32 lr r3, [CTOP_AUX_THREAD_ID]
37 #ifdef CONFIG_ARC_HAS_DCACHE
38 ; With no cache coherency mechanism D$ need to be used very carefully.
40 ; 0G-2G: We disable CONFIG_ARC_CACHE_PAGES.
41 ; 2G-3G: We disable D$ by setting this bit.
42 ; 3G-4G: D$ is disabled by architecture.
43 ; FMT are huge pages for user application reside at 0-2G.
44 ; Only FMT left as one who can use D$ where each such page got
45 ; disable/enable bit for cachability.
46 ; Programmer will use FMT pages for private data so cache coherency
47 ; would not be a problem.
48 ; First thing we invalidate D$
49 sr 1, [ARC_REG_DC_IVDC]
50 sr HW_COMPLY_KRN_NOT_D_CACHED, [CTOP_AUX_HW_COMPLY]
54 ; We set logical cpuid to be used by GET_CPUID
55 ; We do not use physical cpuid since we want ids to be continious when
56 ; it comes to cpus on the same quad cluster.
57 ; This is useful for applications that used shared resources of a quad
59 lr r3, [CTOP_AUX_CORE_ID]
60 sr r3, [CTOP_AUX_LOGIC_CORE_ID]
61 lr r3, [CTOP_AUX_CLUSTER_ID]
62 ; Set logical is acheived by swap of 2 middle bits of cluster id (4 bit)
63 ; r3 is used since we use short instruction and we need q-class reg
64 .short CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST
65 .word CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM
66 sr r3, [CTOP_AUX_LOGIC_CLUSTER_ID]