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blk-mq: always free hctx after request queue is freed
[linux/fpc-iii.git] / drivers / media / platform / pxa_camera.c
blob4fe228752a439e752eee498e4ca2e4ee49d511b2
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 * Copyright (C) 2016, Robert Jarzmik <robert.jarzmik@free.fr>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/err.h>
21 #include <linux/errno.h>
22 #include <linux/fs.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/moduleparam.h>
27 #include <linux/of.h>
28 #include <linux/of_graph.h>
29 #include <linux/time.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/sched.h>
33 #include <linux/slab.h>
34 #include <linux/dmaengine.h>
35 #include <linux/dma/pxa-dma.h>
36
37 #include <media/v4l2-async.h>
38 #include <media/v4l2-clk.h>
39 #include <media/v4l2-common.h>
40 #include <media/v4l2-ctrls.h>
41 #include <media/v4l2-device.h>
42 #include <media/v4l2-event.h>
43 #include <media/v4l2-ioctl.h>
44 #include <media/v4l2-fwnode.h>
45
46 #include <media/videobuf2-dma-sg.h>
47
48 #include <linux/videodev2.h>
49
50 #include <linux/platform_data/media/camera-pxa.h>
51
52 #define PXA_CAM_VERSION "0.0.6"
53 #define PXA_CAM_DRV_NAME "pxa27x-camera"
54
55 #define DEFAULT_WIDTH 640
56 #define DEFAULT_HEIGHT 480
57
58 /* Camera Interface */
59 #define CICR0 0x0000
60 #define CICR1 0x0004
61 #define CICR2 0x0008
62 #define CICR3 0x000C
63 #define CICR4 0x0010
64 #define CISR 0x0014
65 #define CIFR 0x0018
66 #define CITOR 0x001C
67 #define CIBR0 0x0028
68 #define CIBR1 0x0030
69 #define CIBR2 0x0038
70
71 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
72 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
73 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
74 #define CICR0_ENB (1 << 28) /* Camera interface enable */
75 #define CICR0_DIS (1 << 27) /* Camera interface disable */
76 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
77 #define CICR0_TOM (1 << 9) /* Time-out mask */
78 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
79 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
80 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
81 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
82 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
83 #define CICR0_CDM (1 << 3) /* Disable-done mask */
84 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
85 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
86 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
87
88 #define CICR1_TBIT (1 << 31) /* Transparency bit */
89 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
90 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
91 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
92 #define CICR1_RGB_F (1 << 11) /* RGB format */
93 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
94 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
95 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
96 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
97 #define CICR1_DW (0x7 << 0) /* Data width mask */
98
99 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
100 wait count mask */
101 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
102 wait count mask */
103 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
104 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
105 wait count mask */
106 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
107 wait count mask */
108
109 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
110 wait count mask */
111 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
112 wait count mask */
113 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
114 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
115 wait count mask */
116 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
117
118 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
119 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
120 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
121 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
122 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
123 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
124 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
125 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
126
127 #define CISR_FTO (1 << 15) /* FIFO time-out */
128 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
129 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
130 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
131 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
132 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
133 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
134 #define CISR_EOL (1 << 8) /* End of line */
135 #define CISR_PAR_ERR (1 << 7) /* Parity error */
136 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
137 #define CISR_CDD (1 << 5) /* Camera interface disable done */
138 #define CISR_SOF (1 << 4) /* Start of frame */
139 #define CISR_EOF (1 << 3) /* End of frame */
140 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
141 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
142 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
143
144 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
145 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
146 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
147 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
148 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
149 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
150 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
151 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
152
153 #define CICR0_SIM_MP (0 << 24)
154 #define CICR0_SIM_SP (1 << 24)
155 #define CICR0_SIM_MS (2 << 24)
156 #define CICR0_SIM_EP (3 << 24)
157 #define CICR0_SIM_ES (4 << 24)
158
159 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
160 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
161 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
162 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
163 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
164
165 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
166 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
167 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
168 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
169 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
170
171 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
172 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
173 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
174 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
175
176 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
177 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
178 CICR0_EOFM | CICR0_FOM)
179
180 #define sensor_call(cam, o, f, args...) \
181 v4l2_subdev_call(cam->sensor, o, f, ##args)
182
183 /*
184 * Format handling
185 */
186
187 /**
188 * enum pxa_mbus_packing - data packing types on the media-bus
189 * @PXA_MBUS_PACKING_NONE: no packing, bit-for-bit transfer to RAM, one
190 * sample represents one pixel
191 * @PXA_MBUS_PACKING_2X8_PADHI: 16 bits transferred in 2 8-bit samples, in the
192 * possibly incomplete byte high bits are padding
193 * @PXA_MBUS_PACKING_EXTEND16: sample width (e.g., 10 bits) has to be extended
194 * to 16 bits
195 */
196 enum pxa_mbus_packing {
197 PXA_MBUS_PACKING_NONE,
198 PXA_MBUS_PACKING_2X8_PADHI,
199 PXA_MBUS_PACKING_EXTEND16,
200 };
201
202 /**
203 * enum pxa_mbus_order - sample order on the media bus
204 * @PXA_MBUS_ORDER_LE: least significant sample first
205 * @PXA_MBUS_ORDER_BE: most significant sample first
206 */
207 enum pxa_mbus_order {
208 PXA_MBUS_ORDER_LE,
209 PXA_MBUS_ORDER_BE,
210 };
211
212 /**
213 * enum pxa_mbus_layout - planes layout in memory
214 * @PXA_MBUS_LAYOUT_PACKED: color components packed
215 * @PXA_MBUS_LAYOUT_PLANAR_2Y_U_V: YUV components stored in 3 planes (4:2:2)
216 * @PXA_MBUS_LAYOUT_PLANAR_2Y_C: YUV components stored in a luma and a
217 * chroma plane (C plane is half the size
218 * of Y plane)
219 * @PXA_MBUS_LAYOUT_PLANAR_Y_C: YUV components stored in a luma and a
220 * chroma plane (C plane is the same size
221 * as Y plane)
222 */
223 enum pxa_mbus_layout {
224 PXA_MBUS_LAYOUT_PACKED = 0,
225 PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
226 PXA_MBUS_LAYOUT_PLANAR_2Y_C,
227 PXA_MBUS_LAYOUT_PLANAR_Y_C,
228 };
229
230 /**
231 * struct pxa_mbus_pixelfmt - Data format on the media bus
232 * @name: Name of the format
233 * @fourcc: Fourcc code, that will be obtained if the data is
234 * stored in memory in the following way:
235 * @packing: Type of sample-packing, that has to be used
236 * @order: Sample order when storing in memory
237 * @layout: Planes layout in memory
238 * @bits_per_sample: How many bits the bridge has to sample
239 */
240 struct pxa_mbus_pixelfmt {
241 const char *name;
242 u32 fourcc;
243 enum pxa_mbus_packing packing;
244 enum pxa_mbus_order order;
245 enum pxa_mbus_layout layout;
246 u8 bits_per_sample;
247 };
248
249 /**
250 * struct pxa_mbus_lookup - Lookup FOURCC IDs by mediabus codes for pass-through
251 * @code: mediabus pixel-code
252 * @fmt: pixel format description
253 */
254 struct pxa_mbus_lookup {
255 u32 code;
256 struct pxa_mbus_pixelfmt fmt;
257 };
258
259 static const struct pxa_mbus_lookup mbus_fmt[] = {
260 {
261 .code = MEDIA_BUS_FMT_YUYV8_2X8,
262 .fmt = {
263 .fourcc = V4L2_PIX_FMT_YUYV,
264 .name = "YUYV",
265 .bits_per_sample = 8,
266 .packing = PXA_MBUS_PACKING_2X8_PADHI,
267 .order = PXA_MBUS_ORDER_LE,
268 .layout = PXA_MBUS_LAYOUT_PACKED,
269 },
270 }, {
271 .code = MEDIA_BUS_FMT_YVYU8_2X8,
272 .fmt = {
273 .fourcc = V4L2_PIX_FMT_YVYU,
274 .name = "YVYU",
275 .bits_per_sample = 8,
276 .packing = PXA_MBUS_PACKING_2X8_PADHI,
277 .order = PXA_MBUS_ORDER_LE,
278 .layout = PXA_MBUS_LAYOUT_PACKED,
279 },
280 }, {
281 .code = MEDIA_BUS_FMT_UYVY8_2X8,
282 .fmt = {
283 .fourcc = V4L2_PIX_FMT_UYVY,
284 .name = "UYVY",
285 .bits_per_sample = 8,
286 .packing = PXA_MBUS_PACKING_2X8_PADHI,
287 .order = PXA_MBUS_ORDER_LE,
288 .layout = PXA_MBUS_LAYOUT_PACKED,
289 },
290 }, {
291 .code = MEDIA_BUS_FMT_VYUY8_2X8,
292 .fmt = {
293 .fourcc = V4L2_PIX_FMT_VYUY,
294 .name = "VYUY",
295 .bits_per_sample = 8,
296 .packing = PXA_MBUS_PACKING_2X8_PADHI,
297 .order = PXA_MBUS_ORDER_LE,
298 .layout = PXA_MBUS_LAYOUT_PACKED,
299 },
300 }, {
301 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
302 .fmt = {
303 .fourcc = V4L2_PIX_FMT_RGB555,
304 .name = "RGB555",
305 .bits_per_sample = 8,
306 .packing = PXA_MBUS_PACKING_2X8_PADHI,
307 .order = PXA_MBUS_ORDER_LE,
308 .layout = PXA_MBUS_LAYOUT_PACKED,
309 },
310 }, {
311 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
312 .fmt = {
313 .fourcc = V4L2_PIX_FMT_RGB555X,
314 .name = "RGB555X",
315 .bits_per_sample = 8,
316 .packing = PXA_MBUS_PACKING_2X8_PADHI,
317 .order = PXA_MBUS_ORDER_BE,
318 .layout = PXA_MBUS_LAYOUT_PACKED,
319 },
320 }, {
321 .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
322 .fmt = {
323 .fourcc = V4L2_PIX_FMT_RGB565,
324 .name = "RGB565",
325 .bits_per_sample = 8,
326 .packing = PXA_MBUS_PACKING_2X8_PADHI,
327 .order = PXA_MBUS_ORDER_LE,
328 .layout = PXA_MBUS_LAYOUT_PACKED,
329 },
330 }, {
331 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
332 .fmt = {
333 .fourcc = V4L2_PIX_FMT_RGB565X,
334 .name = "RGB565X",
335 .bits_per_sample = 8,
336 .packing = PXA_MBUS_PACKING_2X8_PADHI,
337 .order = PXA_MBUS_ORDER_BE,
338 .layout = PXA_MBUS_LAYOUT_PACKED,
339 },
340 }, {
341 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
342 .fmt = {
343 .fourcc = V4L2_PIX_FMT_SBGGR8,
344 .name = "Bayer 8 BGGR",
345 .bits_per_sample = 8,
346 .packing = PXA_MBUS_PACKING_NONE,
347 .order = PXA_MBUS_ORDER_LE,
348 .layout = PXA_MBUS_LAYOUT_PACKED,
349 },
350 }, {
351 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
352 .fmt = {
353 .fourcc = V4L2_PIX_FMT_SGBRG8,
354 .name = "Bayer 8 GBRG",
355 .bits_per_sample = 8,
356 .packing = PXA_MBUS_PACKING_NONE,
357 .order = PXA_MBUS_ORDER_LE,
358 .layout = PXA_MBUS_LAYOUT_PACKED,
359 },
360 }, {
361 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
362 .fmt = {
363 .fourcc = V4L2_PIX_FMT_SGRBG8,
364 .name = "Bayer 8 GRBG",
365 .bits_per_sample = 8,
366 .packing = PXA_MBUS_PACKING_NONE,
367 .order = PXA_MBUS_ORDER_LE,
368 .layout = PXA_MBUS_LAYOUT_PACKED,
369 },
370 }, {
371 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
372 .fmt = {
373 .fourcc = V4L2_PIX_FMT_SRGGB8,
374 .name = "Bayer 8 RGGB",
375 .bits_per_sample = 8,
376 .packing = PXA_MBUS_PACKING_NONE,
377 .order = PXA_MBUS_ORDER_LE,
378 .layout = PXA_MBUS_LAYOUT_PACKED,
379 },
380 }, {
381 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
382 .fmt = {
383 .fourcc = V4L2_PIX_FMT_SBGGR10,
384 .name = "Bayer 10 BGGR",
385 .bits_per_sample = 10,
386 .packing = PXA_MBUS_PACKING_EXTEND16,
387 .order = PXA_MBUS_ORDER_LE,
388 .layout = PXA_MBUS_LAYOUT_PACKED,
389 },
390 }, {
391 .code = MEDIA_BUS_FMT_Y8_1X8,
392 .fmt = {
393 .fourcc = V4L2_PIX_FMT_GREY,
394 .name = "Grey",
395 .bits_per_sample = 8,
396 .packing = PXA_MBUS_PACKING_NONE,
397 .order = PXA_MBUS_ORDER_LE,
398 .layout = PXA_MBUS_LAYOUT_PACKED,
399 },
400 }, {
401 .code = MEDIA_BUS_FMT_Y10_1X10,
402 .fmt = {
403 .fourcc = V4L2_PIX_FMT_Y10,
404 .name = "Grey 10bit",
405 .bits_per_sample = 10,
406 .packing = PXA_MBUS_PACKING_EXTEND16,
407 .order = PXA_MBUS_ORDER_LE,
408 .layout = PXA_MBUS_LAYOUT_PACKED,
409 },
410 }, {
411 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
412 .fmt = {
413 .fourcc = V4L2_PIX_FMT_SBGGR10,
414 .name = "Bayer 10 BGGR",
415 .bits_per_sample = 8,
416 .packing = PXA_MBUS_PACKING_2X8_PADHI,
417 .order = PXA_MBUS_ORDER_LE,
418 .layout = PXA_MBUS_LAYOUT_PACKED,
419 },
420 }, {
421 .code = MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE,
422 .fmt = {
423 .fourcc = V4L2_PIX_FMT_SBGGR10,
424 .name = "Bayer 10 BGGR",
425 .bits_per_sample = 8,
426 .packing = PXA_MBUS_PACKING_2X8_PADHI,
427 .order = PXA_MBUS_ORDER_BE,
428 .layout = PXA_MBUS_LAYOUT_PACKED,
429 },
430 }, {
431 .code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE,
432 .fmt = {
433 .fourcc = V4L2_PIX_FMT_RGB444,
434 .name = "RGB444",
435 .bits_per_sample = 8,
436 .packing = PXA_MBUS_PACKING_2X8_PADHI,
437 .order = PXA_MBUS_ORDER_BE,
438 .layout = PXA_MBUS_LAYOUT_PACKED,
439 },
440 }, {
441 .code = MEDIA_BUS_FMT_UYVY8_1X16,
442 .fmt = {
443 .fourcc = V4L2_PIX_FMT_UYVY,
444 .name = "UYVY 16bit",
445 .bits_per_sample = 16,
446 .packing = PXA_MBUS_PACKING_EXTEND16,
447 .order = PXA_MBUS_ORDER_LE,
448 .layout = PXA_MBUS_LAYOUT_PACKED,
449 },
450 }, {
451 .code = MEDIA_BUS_FMT_VYUY8_1X16,
452 .fmt = {
453 .fourcc = V4L2_PIX_FMT_VYUY,
454 .name = "VYUY 16bit",
455 .bits_per_sample = 16,
456 .packing = PXA_MBUS_PACKING_EXTEND16,
457 .order = PXA_MBUS_ORDER_LE,
458 .layout = PXA_MBUS_LAYOUT_PACKED,
459 },
460 }, {
461 .code = MEDIA_BUS_FMT_YUYV8_1X16,
462 .fmt = {
463 .fourcc = V4L2_PIX_FMT_YUYV,
464 .name = "YUYV 16bit",
465 .bits_per_sample = 16,
466 .packing = PXA_MBUS_PACKING_EXTEND16,
467 .order = PXA_MBUS_ORDER_LE,
468 .layout = PXA_MBUS_LAYOUT_PACKED,
469 },
470 }, {
471 .code = MEDIA_BUS_FMT_YVYU8_1X16,
472 .fmt = {
473 .fourcc = V4L2_PIX_FMT_YVYU,
474 .name = "YVYU 16bit",
475 .bits_per_sample = 16,
476 .packing = PXA_MBUS_PACKING_EXTEND16,
477 .order = PXA_MBUS_ORDER_LE,
478 .layout = PXA_MBUS_LAYOUT_PACKED,
479 },
480 }, {
481 .code = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
482 .fmt = {
483 .fourcc = V4L2_PIX_FMT_SGRBG10DPCM8,
484 .name = "Bayer 10 BGGR DPCM 8",
485 .bits_per_sample = 8,
486 .packing = PXA_MBUS_PACKING_NONE,
487 .order = PXA_MBUS_ORDER_LE,
488 .layout = PXA_MBUS_LAYOUT_PACKED,
489 },
490 }, {
491 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
492 .fmt = {
493 .fourcc = V4L2_PIX_FMT_SGBRG10,
494 .name = "Bayer 10 GBRG",
495 .bits_per_sample = 10,
496 .packing = PXA_MBUS_PACKING_EXTEND16,
497 .order = PXA_MBUS_ORDER_LE,
498 .layout = PXA_MBUS_LAYOUT_PACKED,
499 },
500 }, {
501 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
502 .fmt = {
503 .fourcc = V4L2_PIX_FMT_SGRBG10,
504 .name = "Bayer 10 GRBG",
505 .bits_per_sample = 10,
506 .packing = PXA_MBUS_PACKING_EXTEND16,
507 .order = PXA_MBUS_ORDER_LE,
508 .layout = PXA_MBUS_LAYOUT_PACKED,
509 },
510 }, {
511 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
512 .fmt = {
513 .fourcc = V4L2_PIX_FMT_SRGGB10,
514 .name = "Bayer 10 RGGB",
515 .bits_per_sample = 10,
516 .packing = PXA_MBUS_PACKING_EXTEND16,
517 .order = PXA_MBUS_ORDER_LE,
518 .layout = PXA_MBUS_LAYOUT_PACKED,
519 },
520 }, {
521 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
522 .fmt = {
523 .fourcc = V4L2_PIX_FMT_SBGGR12,
524 .name = "Bayer 12 BGGR",
525 .bits_per_sample = 12,
526 .packing = PXA_MBUS_PACKING_EXTEND16,
527 .order = PXA_MBUS_ORDER_LE,
528 .layout = PXA_MBUS_LAYOUT_PACKED,
529 },
530 }, {
531 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
532 .fmt = {
533 .fourcc = V4L2_PIX_FMT_SGBRG12,
534 .name = "Bayer 12 GBRG",
535 .bits_per_sample = 12,
536 .packing = PXA_MBUS_PACKING_EXTEND16,
537 .order = PXA_MBUS_ORDER_LE,
538 .layout = PXA_MBUS_LAYOUT_PACKED,
539 },
540 }, {
541 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
542 .fmt = {
543 .fourcc = V4L2_PIX_FMT_SGRBG12,
544 .name = "Bayer 12 GRBG",
545 .bits_per_sample = 12,
546 .packing = PXA_MBUS_PACKING_EXTEND16,
547 .order = PXA_MBUS_ORDER_LE,
548 .layout = PXA_MBUS_LAYOUT_PACKED,
549 },
550 }, {
551 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
552 .fmt = {
553 .fourcc = V4L2_PIX_FMT_SRGGB12,
554 .name = "Bayer 12 RGGB",
555 .bits_per_sample = 12,
556 .packing = PXA_MBUS_PACKING_EXTEND16,
557 .order = PXA_MBUS_ORDER_LE,
558 .layout = PXA_MBUS_LAYOUT_PACKED,
559 },
560 },
561 };
562
563 static s32 pxa_mbus_bytes_per_line(u32 width, const struct pxa_mbus_pixelfmt *mf)
564 {
565 if (mf->layout != PXA_MBUS_LAYOUT_PACKED)
566 return width * mf->bits_per_sample / 8;
567
568 switch (mf->packing) {
569 case PXA_MBUS_PACKING_NONE:
570 return width * mf->bits_per_sample / 8;
571 case PXA_MBUS_PACKING_2X8_PADHI:
572 case PXA_MBUS_PACKING_EXTEND16:
573 return width * 2;
574 }
575 return -EINVAL;
576 }
577
578 static s32 pxa_mbus_image_size(const struct pxa_mbus_pixelfmt *mf,
579 u32 bytes_per_line, u32 height)
580 {
581 if (mf->layout == PXA_MBUS_LAYOUT_PACKED)
582 return bytes_per_line * height;
583
584 switch (mf->packing) {
585 case PXA_MBUS_PACKING_2X8_PADHI:
586 return bytes_per_line * height * 2;
587 default:
588 return -EINVAL;
589 }
590 }
591
592 static const struct pxa_mbus_pixelfmt *pxa_mbus_find_fmtdesc(
593 u32 code,
594 const struct pxa_mbus_lookup *lookup,
595 int n)
596 {
597 int i;
598
599 for (i = 0; i < n; i++)
600 if (lookup[i].code == code)
601 return &lookup[i].fmt;
602
603 return NULL;
604 }
605
606 static const struct pxa_mbus_pixelfmt *pxa_mbus_get_fmtdesc(
607 u32 code)
608 {
609 return pxa_mbus_find_fmtdesc(code, mbus_fmt, ARRAY_SIZE(mbus_fmt));
610 }
611
612 static unsigned int pxa_mbus_config_compatible(const struct v4l2_mbus_config *cfg,
613 unsigned int flags)
614 {
615 unsigned long common_flags;
616 bool hsync = true, vsync = true, pclk, data, mode;
617 bool mipi_lanes, mipi_clock;
618
619 common_flags = cfg->flags & flags;
620
621 switch (cfg->type) {
622 case V4L2_MBUS_PARALLEL:
623 hsync = common_flags & (V4L2_MBUS_HSYNC_ACTIVE_HIGH |
624 V4L2_MBUS_HSYNC_ACTIVE_LOW);
625 vsync = common_flags & (V4L2_MBUS_VSYNC_ACTIVE_HIGH |
626 V4L2_MBUS_VSYNC_ACTIVE_LOW);
627 /* fall through */
628 case V4L2_MBUS_BT656:
629 pclk = common_flags & (V4L2_MBUS_PCLK_SAMPLE_RISING |
630 V4L2_MBUS_PCLK_SAMPLE_FALLING);
631 data = common_flags & (V4L2_MBUS_DATA_ACTIVE_HIGH |
632 V4L2_MBUS_DATA_ACTIVE_LOW);
633 mode = common_flags & (V4L2_MBUS_MASTER | V4L2_MBUS_SLAVE);
634 return (!hsync || !vsync || !pclk || !data || !mode) ?
635 0 : common_flags;
636 case V4L2_MBUS_CSI2_DPHY:
637 mipi_lanes = common_flags & V4L2_MBUS_CSI2_LANES;
638 mipi_clock = common_flags & (V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK |
639 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK);
640 return (!mipi_lanes || !mipi_clock) ? 0 : common_flags;
641 default:
642 WARN_ON(1);
643 return -EINVAL;
644 }
645 return 0;
646 }
647
648 /**
649 * struct pxa_camera_format_xlate - match between host and sensor formats
650 * @code: code of a sensor provided format
651 * @host_fmt: host format after host translation from code
652 *
653 * Host and sensor translation structure. Used in table of host and sensor
654 * formats matchings in pxa_camera_device. A host can override the generic list
655 * generation by implementing get_formats(), and use it for format checks and
656 * format setup.
657 */
658 struct pxa_camera_format_xlate {
659 u32 code;
660 const struct pxa_mbus_pixelfmt *host_fmt;
661 };
662
663 /*
664 * Structures
665 */
666 enum pxa_camera_active_dma {
667 DMA_Y = 0x1,
668 DMA_U = 0x2,
669 DMA_V = 0x4,
670 };
671
672 /* buffer for one video frame */
673 struct pxa_buffer {
674 /* common v4l buffer stuff -- must be first */
675 struct vb2_v4l2_buffer vbuf;
676 struct list_head queue;
677 u32 code;
678 int nb_planes;
679 /* our descriptor lists for Y, U and V channels */
680 struct dma_async_tx_descriptor *descs[3];
681 dma_cookie_t cookie[3];
682 struct scatterlist *sg[3];
683 int sg_len[3];
684 size_t plane_sizes[3];
685 int inwork;
686 enum pxa_camera_active_dma active_dma;
687 };
688
689 struct pxa_camera_dev {
690 struct v4l2_device v4l2_dev;
691 struct video_device vdev;
692 struct v4l2_async_notifier notifier;
693 struct vb2_queue vb2_vq;
694 struct v4l2_subdev *sensor;
695 struct pxa_camera_format_xlate *user_formats;
696 const struct pxa_camera_format_xlate *current_fmt;
697 struct v4l2_pix_format current_pix;
698
699 struct v4l2_async_subdev asd;
700
701 /*
702 * PXA27x is only supposed to handle one camera on its Quick Capture
703 * interface. If anyone ever builds hardware to enable more than
704 * one camera, they will have to modify this driver too
705 */
706 struct clk *clk;
707
708 unsigned int irq;
709 void __iomem *base;
710
711 int channels;
712 struct dma_chan *dma_chans[3];
713
714 struct pxacamera_platform_data *pdata;
715 struct resource *res;
716 unsigned long platform_flags;
717 unsigned long ciclk;
718 unsigned long mclk;
719 u32 mclk_divisor;
720 struct v4l2_clk *mclk_clk;
721 u16 width_flags; /* max 10 bits */
722
723 struct list_head capture;
724
725 spinlock_t lock;
726 struct mutex mlock;
727 unsigned int buf_sequence;
728
729 struct pxa_buffer *active;
730 struct tasklet_struct task_eof;
731
732 u32 save_cicr[5];
733 };
734
735 struct pxa_cam {
736 unsigned long flags;
737 };
738
739 static const char *pxa_cam_driver_description = "PXA_Camera";
740
741 /*
742 * Format translation functions
743 */
744 static const struct pxa_camera_format_xlate
745 *pxa_mbus_xlate_by_fourcc(struct pxa_camera_format_xlate *user_formats,
746 unsigned int fourcc)
747 {
748 unsigned int i;
749
750 for (i = 0; user_formats[i].code; i++)
751 if (user_formats[i].host_fmt->fourcc == fourcc)
752 return user_formats + i;
753 return NULL;
754 }
755
756 static struct pxa_camera_format_xlate *pxa_mbus_build_fmts_xlate(
757 struct v4l2_device *v4l2_dev, struct v4l2_subdev *subdev,
758 int (*get_formats)(struct v4l2_device *, unsigned int,
759 struct pxa_camera_format_xlate *xlate))
760 {
761 unsigned int i, fmts = 0, raw_fmts = 0;
762 int ret;
763 struct v4l2_subdev_mbus_code_enum code = {
764 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
765 };
766 struct pxa_camera_format_xlate *user_formats;
767
768 while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) {
769 raw_fmts++;
770 code.index++;
771 }
772
773 /*
774 * First pass - only count formats this host-sensor
775 * configuration can provide
776 */
777 for (i = 0; i < raw_fmts; i++) {
778 ret = get_formats(v4l2_dev, i, NULL);
779 if (ret < 0)
780 return ERR_PTR(ret);
781 fmts += ret;
782 }
783
784 if (!fmts)
785 return ERR_PTR(-ENXIO);
786
787 user_formats = kcalloc(fmts + 1, sizeof(*user_formats), GFP_KERNEL);
788 if (!user_formats)
789 return ERR_PTR(-ENOMEM);
790
791 /* Second pass - actually fill data formats */
792 fmts = 0;
793 for (i = 0; i < raw_fmts; i++) {
794 ret = get_formats(v4l2_dev, i, user_formats + fmts);
795 if (ret < 0)
796 goto egfmt;
797 fmts += ret;
798 }
799 user_formats[fmts].code = 0;
800
801 return user_formats;
802 egfmt:
803 kfree(user_formats);
804 return ERR_PTR(ret);
805 }
806
807 /*
808 * Videobuf operations
809 */
810 static struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb)
811 {
812 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
813
814 return container_of(vbuf, struct pxa_buffer, vbuf);
815 }
816
817 static struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev)
818 {
819 return pcdev->v4l2_dev.dev;
820 }
821
822 static struct pxa_camera_dev *v4l2_dev_to_pcdev(struct v4l2_device *v4l2_dev)
823 {
824 return container_of(v4l2_dev, struct pxa_camera_dev, v4l2_dev);
825 }
826
827 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
828 enum pxa_camera_active_dma act_dma);
829
830 static void pxa_camera_dma_irq_y(void *data)
831 {
832 struct pxa_camera_dev *pcdev = data;
833
834 pxa_camera_dma_irq(pcdev, DMA_Y);
835 }
836
837 static void pxa_camera_dma_irq_u(void *data)
838 {
839 struct pxa_camera_dev *pcdev = data;
840
841 pxa_camera_dma_irq(pcdev, DMA_U);
842 }
843
844 static void pxa_camera_dma_irq_v(void *data)
845 {
846 struct pxa_camera_dev *pcdev = data;
847
848 pxa_camera_dma_irq(pcdev, DMA_V);
849 }
850
851 /**
852 * pxa_init_dma_channel - init dma descriptors
853 * @pcdev: pxa camera device
854 * @buf: pxa camera buffer
855 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
856 * @sg: dma scatter list
857 * @sglen: dma scatter list length
858 *
859 * Prepares the pxa dma descriptors to transfer one camera channel.
860 *
861 * Returns 0 if success or -ENOMEM if no memory is available
862 */
863 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
864 struct pxa_buffer *buf, int channel,
865 struct scatterlist *sg, int sglen)
866 {
867 struct dma_chan *dma_chan = pcdev->dma_chans[channel];
868 struct dma_async_tx_descriptor *tx;
869
870 tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM,
871 DMA_PREP_INTERRUPT | DMA_CTRL_REUSE);
872 if (!tx) {
873 dev_err(pcdev_to_dev(pcdev),
874 "dmaengine_prep_slave_sg failed\n");
875 goto fail;
876 }
877
878 tx->callback_param = pcdev;
879 switch (channel) {
880 case 0:
881 tx->callback = pxa_camera_dma_irq_y;
882 break;
883 case 1:
884 tx->callback = pxa_camera_dma_irq_u;
885 break;
886 case 2:
887 tx->callback = pxa_camera_dma_irq_v;
888 break;
889 }
890
891 buf->descs[channel] = tx;
892 return 0;
893 fail:
894 dev_dbg(pcdev_to_dev(pcdev),
895 "%s (vb=%p) dma_tx=%p\n",
896 __func__, buf, tx);
897
898 return -ENOMEM;
899 }
900
901 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
902 struct pxa_buffer *buf)
903 {
904 buf->active_dma = DMA_Y;
905 if (buf->nb_planes == 3)
906 buf->active_dma |= DMA_U | DMA_V;
907 }
908
909 /**
910 * pxa_dma_start_channels - start DMA channel for active buffer
911 * @pcdev: pxa camera device
912 *
913 * Initialize DMA channels to the beginning of the active video buffer, and
914 * start these channels.
915 */
916 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
917 {
918 int i;
919
920 for (i = 0; i < pcdev->channels; i++) {
921 dev_dbg(pcdev_to_dev(pcdev),
922 "%s (channel=%d)\n", __func__, i);
923 dma_async_issue_pending(pcdev->dma_chans[i]);
924 }
925 }
926
927 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
928 {
929 int i;
930
931 for (i = 0; i < pcdev->channels; i++) {
932 dev_dbg(pcdev_to_dev(pcdev),
933 "%s (channel=%d)\n", __func__, i);
934 dmaengine_terminate_all(pcdev->dma_chans[i]);
935 }
936 }
937
938 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
939 struct pxa_buffer *buf)
940 {
941 int i;
942
943 for (i = 0; i < pcdev->channels; i++) {
944 buf->cookie[i] = dmaengine_submit(buf->descs[i]);
945 dev_dbg(pcdev_to_dev(pcdev),
946 "%s (channel=%d) : submit vb=%p cookie=%d\n",
947 __func__, i, buf, buf->descs[i]->cookie);
948 }
949 }
950
951 /**
952 * pxa_camera_start_capture - start video capturing
953 * @pcdev: camera device
954 *
955 * Launch capturing. DMA channels should not be active yet. They should get
956 * activated at the end of frame interrupt, to capture only whole frames, and
957 * never begin the capture of a partial frame.
958 */
959 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
960 {
961 unsigned long cicr0;
962
963 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
964 __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR);
965 /* Enable End-Of-Frame Interrupt */
966 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
967 cicr0 &= ~CICR0_EOFM;
968 __raw_writel(cicr0, pcdev->base + CICR0);
969 }
970
971 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
972 {
973 unsigned long cicr0;
974
975 pxa_dma_stop_channels(pcdev);
976
977 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
978 __raw_writel(cicr0, pcdev->base + CICR0);
979
980 pcdev->active = NULL;
981 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
982 }
983
984 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
985 struct pxa_buffer *buf,
986 enum vb2_buffer_state state)
987 {
988 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
989 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
990
991 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
992 list_del_init(&buf->queue);
993 vb->timestamp = ktime_get_ns();
994 vbuf->sequence = pcdev->buf_sequence++;
995 vbuf->field = V4L2_FIELD_NONE;
996 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
997 dev_dbg(pcdev_to_dev(pcdev), "%s dequeued buffer (buf=0x%p)\n",
998 __func__, buf);
999
1000 if (list_empty(&pcdev->capture)) {
1001 pxa_camera_stop_capture(pcdev);
1002 return;
1003 }
1004
1005 pcdev->active = list_entry(pcdev->capture.next,
1006 struct pxa_buffer, queue);
1007 }
1008
1009 /**
1010 * pxa_camera_check_link_miss - check missed DMA linking
1011 * @pcdev: camera device
1012 * @last_submitted: an opaque DMA cookie for last submitted
1013 * @last_issued: an opaque DMA cookie for last issued
1014 *
1015 * The DMA chaining is done with DMA running. This means a tiny temporal window
1016 * remains, where a buffer is queued on the chain, while the chain is already
1017 * stopped. This means the tailed buffer would never be transferred by DMA.
1018 * This function restarts the capture for this corner case, where :
1019 * - DADR() == DADDR_STOP
1020 * - a videobuffer is queued on the pcdev->capture list
1021 *
1022 * Please check the "DMA hot chaining timeslice issue" in
1023 * Documentation/media/v4l-drivers/pxa_camera.rst
1024 *
1025 * Context: should only be called within the dma irq handler
1026 */
1027 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev,
1028 dma_cookie_t last_submitted,
1029 dma_cookie_t last_issued)
1030 {
1031 bool is_dma_stopped = last_submitted != last_issued;
1032
1033 dev_dbg(pcdev_to_dev(pcdev),
1034 "%s : top queued buffer=%p, is_dma_stopped=%d\n",
1035 __func__, pcdev->active, is_dma_stopped);
1036
1037 if (pcdev->active && is_dma_stopped)
1038 pxa_camera_start_capture(pcdev);
1039 }
1040
1041 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
1042 enum pxa_camera_active_dma act_dma)
1043 {
1044 struct pxa_buffer *buf, *last_buf;
1045 unsigned long flags;
1046 u32 camera_status, overrun;
1047 int chan;
1048 enum dma_status last_status;
1049 dma_cookie_t last_issued;
1050
1051 spin_lock_irqsave(&pcdev->lock, flags);
1052
1053 camera_status = __raw_readl(pcdev->base + CISR);
1054 dev_dbg(pcdev_to_dev(pcdev), "camera dma irq, cisr=0x%x dma=%d\n",
1055 camera_status, act_dma);
1056 overrun = CISR_IFO_0;
1057 if (pcdev->channels == 3)
1058 overrun |= CISR_IFO_1 | CISR_IFO_2;
1059
1060 /*
1061 * pcdev->active should not be NULL in DMA irq handler.
1062 *
1063 * But there is one corner case : if capture was stopped due to an
1064 * overrun of channel 1, and at that same channel 2 was completed.
1065 *
1066 * When handling the overrun in DMA irq for channel 1, we'll stop the
1067 * capture and restart it (and thus set pcdev->active to NULL). But the
1068 * DMA irq handler will already be pending for channel 2. So on entering
1069 * the DMA irq handler for channel 2 there will be no active buffer, yet
1070 * that is normal.
1071 */
1072 if (!pcdev->active)
1073 goto out;
1074
1075 buf = pcdev->active;
1076 WARN_ON(buf->inwork || list_empty(&buf->queue));
1077
1078 /*
1079 * It's normal if the last frame creates an overrun, as there
1080 * are no more DMA descriptors to fetch from QCI fifos
1081 */
1082 switch (act_dma) {
1083 case DMA_U:
1084 chan = 1;
1085 break;
1086 case DMA_V:
1087 chan = 2;
1088 break;
1089 default:
1090 chan = 0;
1091 break;
1092 }
1093 last_buf = list_entry(pcdev->capture.prev,
1094 struct pxa_buffer, queue);
1095 last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan],
1096 last_buf->cookie[chan],
1097 NULL, &last_issued);
1098 if (camera_status & overrun &&
1099 last_status != DMA_COMPLETE) {
1100 dev_dbg(pcdev_to_dev(pcdev), "FIFO overrun! CISR: %x\n",
1101 camera_status);
1102 pxa_camera_stop_capture(pcdev);
1103 list_for_each_entry(buf, &pcdev->capture, queue)
1104 pxa_dma_add_tail_buf(pcdev, buf);
1105 pxa_camera_start_capture(pcdev);
1106 goto out;
1107 }
1108 buf->active_dma &= ~act_dma;
1109 if (!buf->active_dma) {
1110 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_DONE);
1111 pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan],
1112 last_issued);
1113 }
1114
1115 out:
1116 spin_unlock_irqrestore(&pcdev->lock, flags);
1117 }
1118
1119 static u32 mclk_get_divisor(struct platform_device *pdev,
1120 struct pxa_camera_dev *pcdev)
1121 {
1122 unsigned long mclk = pcdev->mclk;
1123 u32 div;
1124 unsigned long lcdclk;
1125
1126 lcdclk = clk_get_rate(pcdev->clk);
1127 pcdev->ciclk = lcdclk;
1128
1129 /* mclk <= ciclk / 4 (27.4.2) */
1130 if (mclk > lcdclk / 4) {
1131 mclk = lcdclk / 4;
1132 dev_warn(&pdev->dev,
1133 "Limiting master clock to %lu\n", mclk);
1134 }
1135
1136 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
1137 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
1138
1139 /* If we're not supplying MCLK, leave it at 0 */
1140 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1141 pcdev->mclk = lcdclk / (2 * (div + 1));
1142
1143 dev_dbg(&pdev->dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
1144 lcdclk, mclk, div);
1145
1146 return div;
1147 }
1148
1149 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
1150 unsigned long pclk)
1151 {
1152 /* We want a timeout > 1 pixel time, not ">=" */
1153 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
1154
1155 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
1156 }
1157
1158 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
1159 {
1160 u32 cicr4 = 0;
1161
1162 /* disable all interrupts */
1163 __raw_writel(0x3ff, pcdev->base + CICR0);
1164
1165 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1166 cicr4 |= CICR4_PCLK_EN;
1167 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1168 cicr4 |= CICR4_MCLK_EN;
1169 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1170 cicr4 |= CICR4_PCP;
1171 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1172 cicr4 |= CICR4_HSP;
1173 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1174 cicr4 |= CICR4_VSP;
1175
1176 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
1177
1178 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1179 /* Initialise the timeout under the assumption pclk = mclk */
1180 recalculate_fifo_timeout(pcdev, pcdev->mclk);
1181 else
1182 /* "Safe default" - 13MHz */
1183 recalculate_fifo_timeout(pcdev, 13000000);
1184
1185 clk_prepare_enable(pcdev->clk);
1186 }
1187
1188 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
1189 {
1190 clk_disable_unprepare(pcdev->clk);
1191 }
1192
1193 static void pxa_camera_eof(unsigned long arg)
1194 {
1195 struct pxa_camera_dev *pcdev = (struct pxa_camera_dev *)arg;
1196 unsigned long cifr;
1197 struct pxa_buffer *buf;
1198
1199 dev_dbg(pcdev_to_dev(pcdev),
1200 "Camera interrupt status 0x%x\n",
1201 __raw_readl(pcdev->base + CISR));
1202
1203 /* Reset the FIFOs */
1204 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
1205 __raw_writel(cifr, pcdev->base + CIFR);
1206
1207 pcdev->active = list_first_entry(&pcdev->capture,
1208 struct pxa_buffer, queue);
1209 buf = pcdev->active;
1210 pxa_videobuf_set_actdma(pcdev, buf);
1211
1212 pxa_dma_start_channels(pcdev);
1213 }
1214
1215 static irqreturn_t pxa_camera_irq(int irq, void *data)
1216 {
1217 struct pxa_camera_dev *pcdev = data;
1218 unsigned long status, cicr0;
1219
1220 status = __raw_readl(pcdev->base + CISR);
1221 dev_dbg(pcdev_to_dev(pcdev),
1222 "Camera interrupt status 0x%lx\n", status);
1223
1224 if (!status)
1225 return IRQ_NONE;
1226
1227 __raw_writel(status, pcdev->base + CISR);
1228
1229 if (status & CISR_EOF) {
1230 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
1231 __raw_writel(cicr0, pcdev->base + CICR0);
1232 tasklet_schedule(&pcdev->task_eof);
1233 }
1234
1235 return IRQ_HANDLED;
1236 }
1237
1238 static int test_platform_param(struct pxa_camera_dev *pcdev,
1239 unsigned char buswidth, unsigned long *flags)
1240 {
1241 /*
1242 * Platform specified synchronization and pixel clock polarities are
1243 * only a recommendation and are only used during probing. The PXA270
1244 * quick capture interface supports both.
1245 */
1246 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1247 V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) |
1248 V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1249 V4L2_MBUS_HSYNC_ACTIVE_LOW |
1250 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
1251 V4L2_MBUS_VSYNC_ACTIVE_LOW |
1252 V4L2_MBUS_DATA_ACTIVE_HIGH |
1253 V4L2_MBUS_PCLK_SAMPLE_RISING |
1254 V4L2_MBUS_PCLK_SAMPLE_FALLING;
1255
1256 /* If requested data width is supported by the platform, use it */
1257 if ((1 << (buswidth - 1)) & pcdev->width_flags)
1258 return 0;
1259
1260 return -EINVAL;
1261 }
1262
1263 static void pxa_camera_setup_cicr(struct pxa_camera_dev *pcdev,
1264 unsigned long flags, __u32 pixfmt)
1265 {
1266 unsigned long dw, bpp;
1267 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1268 int ret = sensor_call(pcdev, sensor, g_skip_top_lines, &y_skip_top);
1269
1270 if (ret < 0)
1271 y_skip_top = 0;
1272
1273 /*
1274 * Datawidth is now guaranteed to be equal to one of the three values.
1275 * We fix bit-per-pixel equal to data-width...
1276 */
1277 switch (pcdev->current_fmt->host_fmt->bits_per_sample) {
1278 case 10:
1279 dw = 4;
1280 bpp = 0x40;
1281 break;
1282 case 9:
1283 dw = 3;
1284 bpp = 0x20;
1285 break;
1286 default:
1287 /*
1288 * Actually it can only be 8 now,
1289 * default is just to silence compiler warnings
1290 */
1291 case 8:
1292 dw = 2;
1293 bpp = 0;
1294 }
1295
1296 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1297 cicr4 |= CICR4_PCLK_EN;
1298 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1299 cicr4 |= CICR4_MCLK_EN;
1300 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1301 cicr4 |= CICR4_PCP;
1302 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1303 cicr4 |= CICR4_HSP;
1304 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1305 cicr4 |= CICR4_VSP;
1306
1307 cicr0 = __raw_readl(pcdev->base + CICR0);
1308 if (cicr0 & CICR0_ENB)
1309 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1310
1311 cicr1 = CICR1_PPL_VAL(pcdev->current_pix.width - 1) | bpp | dw;
1312
1313 switch (pixfmt) {
1314 case V4L2_PIX_FMT_YUV422P:
1315 pcdev->channels = 3;
1316 cicr1 |= CICR1_YCBCR_F;
1317 /*
1318 * Normally, pxa bus wants as input UYVY format. We allow all
1319 * reorderings of the YUV422 format, as no processing is done,
1320 * and the YUV stream is just passed through without any
1321 * transformation. Note that UYVY is the only format that
1322 * should be used if pxa framebuffer Overlay2 is used.
1323 */
1324 /* fall through */
1325 case V4L2_PIX_FMT_UYVY:
1326 case V4L2_PIX_FMT_VYUY:
1327 case V4L2_PIX_FMT_YUYV:
1328 case V4L2_PIX_FMT_YVYU:
1329 cicr1 |= CICR1_COLOR_SP_VAL(2);
1330 break;
1331 case V4L2_PIX_FMT_RGB555:
1332 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1333 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1334 break;
1335 case V4L2_PIX_FMT_RGB565:
1336 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1337 break;
1338 }
1339
1340 cicr2 = 0;
1341 cicr3 = CICR3_LPF_VAL(pcdev->current_pix.height - 1) |
1342 CICR3_BFW_VAL(min((u32)255, y_skip_top));
1343 cicr4 |= pcdev->mclk_divisor;
1344
1345 __raw_writel(cicr1, pcdev->base + CICR1);
1346 __raw_writel(cicr2, pcdev->base + CICR2);
1347 __raw_writel(cicr3, pcdev->base + CICR3);
1348 __raw_writel(cicr4, pcdev->base + CICR4);
1349
1350 /* CIF interrupts are not used, only DMA */
1351 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1352 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1353 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1354 __raw_writel(cicr0, pcdev->base + CICR0);
1355 }
1356
1357 /*
1358 * Videobuf2 section
1359 */
1360 static void pxa_buffer_cleanup(struct pxa_buffer *buf)
1361 {
1362 int i;
1363
1364 for (i = 0; i < 3 && buf->descs[i]; i++) {
1365 dmaengine_desc_free(buf->descs[i]);
1366 kfree(buf->sg[i]);
1367 buf->descs[i] = NULL;
1368 buf->sg[i] = NULL;
1369 buf->sg_len[i] = 0;
1370 buf->plane_sizes[i] = 0;
1371 }
1372 buf->nb_planes = 0;
1373 }
1374
1375 static int pxa_buffer_init(struct pxa_camera_dev *pcdev,
1376 struct pxa_buffer *buf)
1377 {
1378 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
1379 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
1380 int nb_channels = pcdev->channels;
1381 int i, ret = 0;
1382 unsigned long size = vb2_plane_size(vb, 0);
1383
1384 switch (nb_channels) {
1385 case 1:
1386 buf->plane_sizes[0] = size;
1387 break;
1388 case 3:
1389 buf->plane_sizes[0] = size / 2;
1390 buf->plane_sizes[1] = size / 4;
1391 buf->plane_sizes[2] = size / 4;
1392 break;
1393 default:
1394 return -EINVAL;
1395 };
1396 buf->nb_planes = nb_channels;
1397
1398 ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels,
1399 buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL);
1400 if (ret < 0) {
1401 dev_err(pcdev_to_dev(pcdev),
1402 "sg_split failed: %d\n", ret);
1403 return ret;
1404 }
1405 for (i = 0; i < nb_channels; i++) {
1406 ret = pxa_init_dma_channel(pcdev, buf, i,
1407 buf->sg[i], buf->sg_len[i]);
1408 if (ret) {
1409 pxa_buffer_cleanup(buf);
1410 return ret;
1411 }
1412 }
1413 INIT_LIST_HEAD(&buf->queue);
1414
1415 return ret;
1416 }
1417
1418 static void pxac_vb2_cleanup(struct vb2_buffer *vb)
1419 {
1420 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1421 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1422
1423 dev_dbg(pcdev_to_dev(pcdev),
1424 "%s(vb=%p)\n", __func__, vb);
1425 pxa_buffer_cleanup(buf);
1426 }
1427
1428 static void pxac_vb2_queue(struct vb2_buffer *vb)
1429 {
1430 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1431 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1432
1433 dev_dbg(pcdev_to_dev(pcdev),
1434 "%s(vb=%p) nb_channels=%d size=%lu active=%p\n",
1435 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0),
1436 pcdev->active);
1437
1438 list_add_tail(&buf->queue, &pcdev->capture);
1439
1440 pxa_dma_add_tail_buf(pcdev, buf);
1441 }
1442
1443 /*
1444 * Please check the DMA prepared buffer structure in :
1445 * Documentation/media/v4l-drivers/pxa_camera.rst
1446 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
1447 * modification while DMA chain is running will work anyway.
1448 */
1449 static int pxac_vb2_prepare(struct vb2_buffer *vb)
1450 {
1451 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1452 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1453 int ret = 0;
1454
1455 switch (pcdev->channels) {
1456 case 1:
1457 case 3:
1458 vb2_set_plane_payload(vb, 0, pcdev->current_pix.sizeimage);
1459 break;
1460 default:
1461 return -EINVAL;
1462 }
1463
1464 dev_dbg(pcdev_to_dev(pcdev),
1465 "%s (vb=%p) nb_channels=%d size=%lu\n",
1466 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0));
1467
1468 WARN_ON(!pcdev->current_fmt);
1469
1470 #ifdef DEBUG
1471 /*
1472 * This can be useful if you want to see if we actually fill
1473 * the buffer with something
1474 */
1475 for (i = 0; i < vb->num_planes; i++)
1476 memset((void *)vb2_plane_vaddr(vb, i),
1477 0xaa, vb2_get_plane_payload(vb, i));
1478 #endif
1479
1480 /*
1481 * I think, in buf_prepare you only have to protect global data,
1482 * the actual buffer is yours
1483 */
1484 buf->inwork = 0;
1485 pxa_videobuf_set_actdma(pcdev, buf);
1486
1487 return ret;
1488 }
1489
1490 static int pxac_vb2_init(struct vb2_buffer *vb)
1491 {
1492 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
1493 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
1494
1495 dev_dbg(pcdev_to_dev(pcdev),
1496 "%s(nb_channels=%d)\n",
1497 __func__, pcdev->channels);
1498
1499 return pxa_buffer_init(pcdev, buf);
1500 }
1501
1502 static int pxac_vb2_queue_setup(struct vb2_queue *vq,
1503 unsigned int *nbufs,
1504 unsigned int *num_planes, unsigned int sizes[],
1505 struct device *alloc_devs[])
1506 {
1507 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1508 int size = pcdev->current_pix.sizeimage;
1509
1510 dev_dbg(pcdev_to_dev(pcdev),
1511 "%s(vq=%p nbufs=%d num_planes=%d size=%d)\n",
1512 __func__, vq, *nbufs, *num_planes, size);
1513 /*
1514 * Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P
1515 * format, even if there are 3 planes Y, U and V, we reply there is only
1516 * one plane, containing Y, U and V data, one after the other.
1517 */
1518 if (*num_planes)
1519 return sizes[0] < size ? -EINVAL : 0;
1520
1521 *num_planes = 1;
1522 switch (pcdev->channels) {
1523 case 1:
1524 case 3:
1525 sizes[0] = size;
1526 break;
1527 default:
1528 return -EINVAL;
1529 }
1530
1531 if (!*nbufs)
1532 *nbufs = 1;
1533
1534 return 0;
1535 }
1536
1537 static int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
1538 {
1539 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1540
1541 dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n",
1542 __func__, count, pcdev->active);
1543
1544 pcdev->buf_sequence = 0;
1545 if (!pcdev->active)
1546 pxa_camera_start_capture(pcdev);
1547
1548 return 0;
1549 }
1550
1551 static void pxac_vb2_stop_streaming(struct vb2_queue *vq)
1552 {
1553 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1554 struct pxa_buffer *buf, *tmp;
1555
1556 dev_dbg(pcdev_to_dev(pcdev), "%s active=%p\n",
1557 __func__, pcdev->active);
1558 pxa_camera_stop_capture(pcdev);
1559
1560 list_for_each_entry_safe(buf, tmp, &pcdev->capture, queue)
1561 pxa_camera_wakeup(pcdev, buf, VB2_BUF_STATE_ERROR);
1562 }
1563
1564 static const struct vb2_ops pxac_vb2_ops = {
1565 .queue_setup = pxac_vb2_queue_setup,
1566 .buf_init = pxac_vb2_init,
1567 .buf_prepare = pxac_vb2_prepare,
1568 .buf_queue = pxac_vb2_queue,
1569 .buf_cleanup = pxac_vb2_cleanup,
1570 .start_streaming = pxac_vb2_start_streaming,
1571 .stop_streaming = pxac_vb2_stop_streaming,
1572 .wait_prepare = vb2_ops_wait_prepare,
1573 .wait_finish = vb2_ops_wait_finish,
1574 };
1575
1576 static int pxa_camera_init_videobuf2(struct pxa_camera_dev *pcdev)
1577 {
1578 int ret;
1579 struct vb2_queue *vq = &pcdev->vb2_vq;
1580
1581 memset(vq, 0, sizeof(*vq));
1582 vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1583 vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
1584 vq->drv_priv = pcdev;
1585 vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1586 vq->buf_struct_size = sizeof(struct pxa_buffer);
1587 vq->dev = pcdev->v4l2_dev.dev;
1588
1589 vq->ops = &pxac_vb2_ops;
1590 vq->mem_ops = &vb2_dma_sg_memops;
1591 vq->lock = &pcdev->mlock;
1592
1593 ret = vb2_queue_init(vq);
1594 dev_dbg(pcdev_to_dev(pcdev),
1595 "vb2_queue_init(vq=%p): %d\n", vq, ret);
1596
1597 return ret;
1598 }
1599
1600 /*
1601 * Video ioctls section
1602 */
1603 static int pxa_camera_set_bus_param(struct pxa_camera_dev *pcdev)
1604 {
1605 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1606 u32 pixfmt = pcdev->current_fmt->host_fmt->fourcc;
1607 unsigned long bus_flags, common_flags;
1608 int ret;
1609
1610 ret = test_platform_param(pcdev,
1611 pcdev->current_fmt->host_fmt->bits_per_sample,
1612 &bus_flags);
1613 if (ret < 0)
1614 return ret;
1615
1616 ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1617 if (!ret) {
1618 common_flags = pxa_mbus_config_compatible(&cfg,
1619 bus_flags);
1620 if (!common_flags) {
1621 dev_warn(pcdev_to_dev(pcdev),
1622 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1623 cfg.flags, bus_flags);
1624 return -EINVAL;
1625 }
1626 } else if (ret != -ENOIOCTLCMD) {
1627 return ret;
1628 } else {
1629 common_flags = bus_flags;
1630 }
1631
1632 pcdev->channels = 1;
1633
1634 /* Make choices, based on platform preferences */
1635 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1636 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1637 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1638 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1639 else
1640 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1641 }
1642
1643 if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
1644 (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
1645 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1646 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1647 else
1648 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
1649 }
1650
1651 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1652 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1653 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1654 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1655 else
1656 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1657 }
1658
1659 cfg.flags = common_flags;
1660 ret = sensor_call(pcdev, video, s_mbus_config, &cfg);
1661 if (ret < 0 && ret != -ENOIOCTLCMD) {
1662 dev_dbg(pcdev_to_dev(pcdev),
1663 "camera s_mbus_config(0x%lx) returned %d\n",
1664 common_flags, ret);
1665 return ret;
1666 }
1667
1668 pxa_camera_setup_cicr(pcdev, common_flags, pixfmt);
1669
1670 return 0;
1671 }
1672
1673 static int pxa_camera_try_bus_param(struct pxa_camera_dev *pcdev,
1674 unsigned char buswidth)
1675 {
1676 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1677 unsigned long bus_flags, common_flags;
1678 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1679
1680 if (ret < 0)
1681 return ret;
1682
1683 ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1684 if (!ret) {
1685 common_flags = pxa_mbus_config_compatible(&cfg,
1686 bus_flags);
1687 if (!common_flags) {
1688 dev_warn(pcdev_to_dev(pcdev),
1689 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1690 cfg.flags, bus_flags);
1691 return -EINVAL;
1692 }
1693 } else if (ret == -ENOIOCTLCMD) {
1694 ret = 0;
1695 }
1696
1697 return ret;
1698 }
1699
1700 static const struct pxa_mbus_pixelfmt pxa_camera_formats[] = {
1701 {
1702 .fourcc = V4L2_PIX_FMT_YUV422P,
1703 .name = "Planar YUV422 16 bit",
1704 .bits_per_sample = 8,
1705 .packing = PXA_MBUS_PACKING_2X8_PADHI,
1706 .order = PXA_MBUS_ORDER_LE,
1707 .layout = PXA_MBUS_LAYOUT_PLANAR_2Y_U_V,
1708 },
1709 };
1710
1711 /* This will be corrected as we get more formats */
1712 static bool pxa_camera_packing_supported(const struct pxa_mbus_pixelfmt *fmt)
1713 {
1714 return fmt->packing == PXA_MBUS_PACKING_NONE ||
1715 (fmt->bits_per_sample == 8 &&
1716 fmt->packing == PXA_MBUS_PACKING_2X8_PADHI) ||
1717 (fmt->bits_per_sample > 8 &&
1718 fmt->packing == PXA_MBUS_PACKING_EXTEND16);
1719 }
1720
1721 static int pxa_camera_get_formats(struct v4l2_device *v4l2_dev,
1722 unsigned int idx,
1723 struct pxa_camera_format_xlate *xlate)
1724 {
1725 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
1726 int formats = 0, ret;
1727 struct v4l2_subdev_mbus_code_enum code = {
1728 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1729 .index = idx,
1730 };
1731 const struct pxa_mbus_pixelfmt *fmt;
1732
1733 ret = sensor_call(pcdev, pad, enum_mbus_code, NULL, &code);
1734 if (ret < 0)
1735 /* No more formats */
1736 return 0;
1737
1738 fmt = pxa_mbus_get_fmtdesc(code.code);
1739 if (!fmt) {
1740 dev_err(pcdev_to_dev(pcdev),
1741 "Invalid format code #%u: %d\n", idx, code.code);
1742 return 0;
1743 }
1744
1745 /* This also checks support for the requested bits-per-sample */
1746 ret = pxa_camera_try_bus_param(pcdev, fmt->bits_per_sample);
1747 if (ret < 0)
1748 return 0;
1749
1750 switch (code.code) {
1751 case MEDIA_BUS_FMT_UYVY8_2X8:
1752 formats++;
1753 if (xlate) {
1754 xlate->host_fmt = &pxa_camera_formats[0];
1755 xlate->code = code.code;
1756 xlate++;
1757 dev_dbg(pcdev_to_dev(pcdev),
1758 "Providing format %s using code %d\n",
1759 pxa_camera_formats[0].name, code.code);
1760 }
1761 /* fall through */
1762 case MEDIA_BUS_FMT_VYUY8_2X8:
1763 case MEDIA_BUS_FMT_YUYV8_2X8:
1764 case MEDIA_BUS_FMT_YVYU8_2X8:
1765 case MEDIA_BUS_FMT_RGB565_2X8_LE:
1766 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
1767 if (xlate)
1768 dev_dbg(pcdev_to_dev(pcdev),
1769 "Providing format %s packed\n",
1770 fmt->name);
1771 break;
1772 default:
1773 if (!pxa_camera_packing_supported(fmt))
1774 return 0;
1775 if (xlate)
1776 dev_dbg(pcdev_to_dev(pcdev),
1777 "Providing format %s in pass-through mode\n",
1778 fmt->name);
1779 break;
1780 }
1781
1782 /* Generic pass-through */
1783 formats++;
1784 if (xlate) {
1785 xlate->host_fmt = fmt;
1786 xlate->code = code.code;
1787 xlate++;
1788 }
1789
1790 return formats;
1791 }
1792
1793 static int pxa_camera_build_formats(struct pxa_camera_dev *pcdev)
1794 {
1795 struct pxa_camera_format_xlate *xlate;
1796
1797 xlate = pxa_mbus_build_fmts_xlate(&pcdev->v4l2_dev, pcdev->sensor,
1798 pxa_camera_get_formats);
1799 if (IS_ERR(xlate))
1800 return PTR_ERR(xlate);
1801
1802 pcdev->user_formats = xlate;
1803 return 0;
1804 }
1805
1806 static void pxa_camera_destroy_formats(struct pxa_camera_dev *pcdev)
1807 {
1808 kfree(pcdev->user_formats);
1809 }
1810
1811 static int pxa_camera_check_frame(u32 width, u32 height)
1812 {
1813 /* limit to pxa hardware capabilities */
1814 return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1815 (width & 0x01);
1816 }
1817
1818 #ifdef CONFIG_VIDEO_ADV_DEBUG
1819 static int pxac_vidioc_g_register(struct file *file, void *priv,
1820 struct v4l2_dbg_register *reg)
1821 {
1822 struct pxa_camera_dev *pcdev = video_drvdata(file);
1823
1824 if (reg->reg > CIBR2)
1825 return -ERANGE;
1826
1827 reg->val = __raw_readl(pcdev->base + reg->reg);
1828 reg->size = sizeof(__u32);
1829 return 0;
1830 }
1831
1832 static int pxac_vidioc_s_register(struct file *file, void *priv,
1833 const struct v4l2_dbg_register *reg)
1834 {
1835 struct pxa_camera_dev *pcdev = video_drvdata(file);
1836
1837 if (reg->reg > CIBR2)
1838 return -ERANGE;
1839 if (reg->size != sizeof(__u32))
1840 return -EINVAL;
1841 __raw_writel(reg->val, pcdev->base + reg->reg);
1842 return 0;
1843 }
1844 #endif
1845
1846 static int pxac_vidioc_enum_fmt_vid_cap(struct file *filp, void *priv,
1847 struct v4l2_fmtdesc *f)
1848 {
1849 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1850 const struct pxa_mbus_pixelfmt *format;
1851 unsigned int idx;
1852
1853 for (idx = 0; pcdev->user_formats[idx].code; idx++);
1854 if (f->index >= idx)
1855 return -EINVAL;
1856
1857 format = pcdev->user_formats[f->index].host_fmt;
1858 f->pixelformat = format->fourcc;
1859 return 0;
1860 }
1861
1862 static int pxac_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1863 struct v4l2_format *f)
1864 {
1865 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1866 struct v4l2_pix_format *pix = &f->fmt.pix;
1867
1868 pix->width = pcdev->current_pix.width;
1869 pix->height = pcdev->current_pix.height;
1870 pix->bytesperline = pcdev->current_pix.bytesperline;
1871 pix->sizeimage = pcdev->current_pix.sizeimage;
1872 pix->field = pcdev->current_pix.field;
1873 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
1874 pix->colorspace = pcdev->current_pix.colorspace;
1875 dev_dbg(pcdev_to_dev(pcdev), "current_fmt->fourcc: 0x%08x\n",
1876 pcdev->current_fmt->host_fmt->fourcc);
1877 return 0;
1878 }
1879
1880 static int pxac_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1881 struct v4l2_format *f)
1882 {
1883 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1884 const struct pxa_camera_format_xlate *xlate;
1885 struct v4l2_pix_format *pix = &f->fmt.pix;
1886 struct v4l2_subdev_pad_config pad_cfg;
1887 struct v4l2_subdev_format format = {
1888 .which = V4L2_SUBDEV_FORMAT_TRY,
1889 };
1890 struct v4l2_mbus_framefmt *mf = &format.format;
1891 __u32 pixfmt = pix->pixelformat;
1892 int ret;
1893
1894 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats, pixfmt);
1895 if (!xlate) {
1896 dev_warn(pcdev_to_dev(pcdev), "Format %x not found\n", pixfmt);
1897 return -EINVAL;
1898 }
1899
1900 /*
1901 * Limit to pxa hardware capabilities. YUV422P planar format requires
1902 * images size to be a multiple of 16 bytes. If not, zeros will be
1903 * inserted between Y and U planes, and U and V planes, which violates
1904 * the YUV422P standard.
1905 */
1906 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1907 &pix->height, 32, 2048, 0,
1908 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1909
1910 v4l2_fill_mbus_format(mf, pix, xlate->code);
1911 ret = sensor_call(pcdev, pad, set_fmt, &pad_cfg, &format);
1912 if (ret < 0)
1913 return ret;
1914
1915 v4l2_fill_pix_format(pix, mf);
1916
1917 /* Only progressive video supported so far */
1918 switch (mf->field) {
1919 case V4L2_FIELD_ANY:
1920 case V4L2_FIELD_NONE:
1921 pix->field = V4L2_FIELD_NONE;
1922 break;
1923 default:
1924 /* TODO: support interlaced at least in pass-through mode */
1925 dev_err(pcdev_to_dev(pcdev), "Field type %d unsupported.\n",
1926 mf->field);
1927 return -EINVAL;
1928 }
1929
1930 ret = pxa_mbus_bytes_per_line(pix->width, xlate->host_fmt);
1931 if (ret < 0)
1932 return ret;
1933
1934 pix->bytesperline = ret;
1935 ret = pxa_mbus_image_size(xlate->host_fmt, pix->bytesperline,
1936 pix->height);
1937 if (ret < 0)
1938 return ret;
1939
1940 pix->sizeimage = ret;
1941 return 0;
1942 }
1943
1944 static int pxac_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1945 struct v4l2_format *f)
1946 {
1947 struct pxa_camera_dev *pcdev = video_drvdata(filp);
1948 const struct pxa_camera_format_xlate *xlate;
1949 struct v4l2_pix_format *pix = &f->fmt.pix;
1950 struct v4l2_subdev_format format = {
1951 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1952 };
1953 unsigned long flags;
1954 int ret, is_busy;
1955
1956 dev_dbg(pcdev_to_dev(pcdev),
1957 "s_fmt_vid_cap(pix=%dx%d:%x)\n",
1958 pix->width, pix->height, pix->pixelformat);
1959
1960 spin_lock_irqsave(&pcdev->lock, flags);
1961 is_busy = pcdev->active || vb2_is_busy(&pcdev->vb2_vq);
1962 spin_unlock_irqrestore(&pcdev->lock, flags);
1963
1964 if (is_busy)
1965 return -EBUSY;
1966
1967 ret = pxac_vidioc_try_fmt_vid_cap(filp, priv, f);
1968 if (ret)
1969 return ret;
1970
1971 xlate = pxa_mbus_xlate_by_fourcc(pcdev->user_formats,
1972 pix->pixelformat);
1973 v4l2_fill_mbus_format(&format.format, pix, xlate->code);
1974 ret = sensor_call(pcdev, pad, set_fmt, NULL, &format);
1975 if (ret < 0) {
1976 dev_warn(pcdev_to_dev(pcdev),
1977 "Failed to configure for format %x\n",
1978 pix->pixelformat);
1979 } else if (pxa_camera_check_frame(pix->width, pix->height)) {
1980 dev_warn(pcdev_to_dev(pcdev),
1981 "Camera driver produced an unsupported frame %dx%d\n",
1982 pix->width, pix->height);
1983 return -EINVAL;
1984 }
1985
1986 pcdev->current_fmt = xlate;
1987 pcdev->current_pix = *pix;
1988
1989 ret = pxa_camera_set_bus_param(pcdev);
1990 return ret;
1991 }
1992
1993 static int pxac_vidioc_querycap(struct file *file, void *priv,
1994 struct v4l2_capability *cap)
1995 {
1996 strscpy(cap->bus_info, "platform:pxa-camera", sizeof(cap->bus_info));
1997 strscpy(cap->driver, PXA_CAM_DRV_NAME, sizeof(cap->driver));
1998 strscpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1999 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
2000 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
2001
2002 return 0;
2003 }
2004
2005 static int pxac_vidioc_enum_input(struct file *file, void *priv,
2006 struct v4l2_input *i)
2007 {
2008 if (i->index > 0)
2009 return -EINVAL;
2010
2011 i->type = V4L2_INPUT_TYPE_CAMERA;
2012 strscpy(i->name, "Camera", sizeof(i->name));
2013
2014 return 0;
2015 }
2016
2017 static int pxac_vidioc_g_input(struct file *file, void *priv, unsigned int *i)
2018 {
2019 *i = 0;
2020
2021 return 0;
2022 }
2023
2024 static int pxac_vidioc_s_input(struct file *file, void *priv, unsigned int i)
2025 {
2026 if (i > 0)
2027 return -EINVAL;
2028
2029 return 0;
2030 }
2031
2032 static int pxac_sensor_set_power(struct pxa_camera_dev *pcdev, int on)
2033 {
2034 int ret;
2035
2036 ret = sensor_call(pcdev, core, s_power, on);
2037 if (ret == -ENOIOCTLCMD)
2038 ret = 0;
2039 if (ret) {
2040 dev_warn(pcdev_to_dev(pcdev),
2041 "Failed to put subdevice in %s mode: %d\n",
2042 on ? "normal operation" : "power saving", ret);
2043 }
2044
2045 return ret;
2046 }
2047
2048 static int pxac_fops_camera_open(struct file *filp)
2049 {
2050 struct pxa_camera_dev *pcdev = video_drvdata(filp);
2051 int ret;
2052
2053 mutex_lock(&pcdev->mlock);
2054 ret = v4l2_fh_open(filp);
2055 if (ret < 0)
2056 goto out;
2057
2058 if (!v4l2_fh_is_singular_file(filp))
2059 goto out;
2060
2061 ret = pxac_sensor_set_power(pcdev, 1);
2062 if (ret)
2063 v4l2_fh_release(filp);
2064 out:
2065 mutex_unlock(&pcdev->mlock);
2066 return ret;
2067 }
2068
2069 static int pxac_fops_camera_release(struct file *filp)
2070 {
2071 struct pxa_camera_dev *pcdev = video_drvdata(filp);
2072 int ret;
2073 bool fh_singular;
2074
2075 mutex_lock(&pcdev->mlock);
2076
2077 fh_singular = v4l2_fh_is_singular_file(filp);
2078
2079 ret = _vb2_fop_release(filp, NULL);
2080
2081 if (fh_singular)
2082 ret = pxac_sensor_set_power(pcdev, 0);
2083
2084 mutex_unlock(&pcdev->mlock);
2085
2086 return ret;
2087 }
2088
2089 static const struct v4l2_file_operations pxa_camera_fops = {
2090 .owner = THIS_MODULE,
2091 .open = pxac_fops_camera_open,
2092 .release = pxac_fops_camera_release,
2093 .read = vb2_fop_read,
2094 .poll = vb2_fop_poll,
2095 .mmap = vb2_fop_mmap,
2096 .unlocked_ioctl = video_ioctl2,
2097 };
2098
2099 static const struct v4l2_ioctl_ops pxa_camera_ioctl_ops = {
2100 .vidioc_querycap = pxac_vidioc_querycap,
2101
2102 .vidioc_enum_input = pxac_vidioc_enum_input,
2103 .vidioc_g_input = pxac_vidioc_g_input,
2104 .vidioc_s_input = pxac_vidioc_s_input,
2105
2106 .vidioc_enum_fmt_vid_cap = pxac_vidioc_enum_fmt_vid_cap,
2107 .vidioc_g_fmt_vid_cap = pxac_vidioc_g_fmt_vid_cap,
2108 .vidioc_s_fmt_vid_cap = pxac_vidioc_s_fmt_vid_cap,
2109 .vidioc_try_fmt_vid_cap = pxac_vidioc_try_fmt_vid_cap,
2110
2111 .vidioc_reqbufs = vb2_ioctl_reqbufs,
2112 .vidioc_create_bufs = vb2_ioctl_create_bufs,
2113 .vidioc_querybuf = vb2_ioctl_querybuf,
2114 .vidioc_qbuf = vb2_ioctl_qbuf,
2115 .vidioc_dqbuf = vb2_ioctl_dqbuf,
2116 .vidioc_expbuf = vb2_ioctl_expbuf,
2117 .vidioc_streamon = vb2_ioctl_streamon,
2118 .vidioc_streamoff = vb2_ioctl_streamoff,
2119 #ifdef CONFIG_VIDEO_ADV_DEBUG
2120 .vidioc_g_register = pxac_vidioc_g_register,
2121 .vidioc_s_register = pxac_vidioc_s_register,
2122 #endif
2123 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
2124 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
2125 };
2126
2127 static const struct v4l2_clk_ops pxa_camera_mclk_ops = {
2128 };
2129
2130 static const struct video_device pxa_camera_videodev_template = {
2131 .name = "pxa-camera",
2132 .minor = -1,
2133 .fops = &pxa_camera_fops,
2134 .ioctl_ops = &pxa_camera_ioctl_ops,
2135 .release = video_device_release_empty,
2136 .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING,
2137 };
2138
2139 static int pxa_camera_sensor_bound(struct v4l2_async_notifier *notifier,
2140 struct v4l2_subdev *subdev,
2141 struct v4l2_async_subdev *asd)
2142 {
2143 int err;
2144 struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
2145 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(v4l2_dev);
2146 struct video_device *vdev = &pcdev->vdev;
2147 struct v4l2_pix_format *pix = &pcdev->current_pix;
2148 struct v4l2_subdev_format format = {
2149 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2150 };
2151 struct v4l2_mbus_framefmt *mf = &format.format;
2152
2153 dev_info(pcdev_to_dev(pcdev), "%s(): trying to bind a device\n",
2154 __func__);
2155 mutex_lock(&pcdev->mlock);
2156 *vdev = pxa_camera_videodev_template;
2157 vdev->v4l2_dev = v4l2_dev;
2158 vdev->lock = &pcdev->mlock;
2159 pcdev->sensor = subdev;
2160 pcdev->vdev.queue = &pcdev->vb2_vq;
2161 pcdev->vdev.v4l2_dev = &pcdev->v4l2_dev;
2162 pcdev->vdev.ctrl_handler = subdev->ctrl_handler;
2163 video_set_drvdata(&pcdev->vdev, pcdev);
2164
2165 err = pxa_camera_build_formats(pcdev);
2166 if (err) {
2167 dev_err(pcdev_to_dev(pcdev), "building formats failed: %d\n",
2168 err);
2169 goto out;
2170 }
2171
2172 pcdev->current_fmt = pcdev->user_formats;
2173 pix->field = V4L2_FIELD_NONE;
2174 pix->width = DEFAULT_WIDTH;
2175 pix->height = DEFAULT_HEIGHT;
2176 pix->bytesperline =
2177 pxa_mbus_bytes_per_line(pix->width,
2178 pcdev->current_fmt->host_fmt);
2179 pix->sizeimage =
2180 pxa_mbus_image_size(pcdev->current_fmt->host_fmt,
2181 pix->bytesperline, pix->height);
2182 pix->pixelformat = pcdev->current_fmt->host_fmt->fourcc;
2183 v4l2_fill_mbus_format(mf, pix, pcdev->current_fmt->code);
2184
2185 err = pxac_sensor_set_power(pcdev, 1);
2186 if (err)
2187 goto out;
2188
2189 err = sensor_call(pcdev, pad, set_fmt, NULL, &format);
2190 if (err)
2191 goto out_sensor_poweroff;
2192
2193 v4l2_fill_pix_format(pix, mf);
2194 pr_info("%s(): colorspace=0x%x pixfmt=0x%x\n",
2195 __func__, pix->colorspace, pix->pixelformat);
2196
2197 err = pxa_camera_init_videobuf2(pcdev);
2198 if (err)
2199 goto out_sensor_poweroff;
2200
2201 err = video_register_device(&pcdev->vdev, VFL_TYPE_GRABBER, -1);
2202 if (err) {
2203 v4l2_err(v4l2_dev, "register video device failed: %d\n", err);
2204 pcdev->sensor = NULL;
2205 } else {
2206 dev_info(pcdev_to_dev(pcdev),
2207 "PXA Camera driver attached to camera %s\n",
2208 subdev->name);
2209 }
2210
2211 out_sensor_poweroff:
2212 err = pxac_sensor_set_power(pcdev, 0);
2213 out:
2214 mutex_unlock(&pcdev->mlock);
2215 return err;
2216 }
2217
2218 static void pxa_camera_sensor_unbind(struct v4l2_async_notifier *notifier,
2219 struct v4l2_subdev *subdev,
2220 struct v4l2_async_subdev *asd)
2221 {
2222 struct pxa_camera_dev *pcdev = v4l2_dev_to_pcdev(notifier->v4l2_dev);
2223
2224 mutex_lock(&pcdev->mlock);
2225 dev_info(pcdev_to_dev(pcdev),
2226 "PXA Camera driver detached from camera %s\n",
2227 subdev->name);
2228
2229 /* disable capture, disable interrupts */
2230 __raw_writel(0x3ff, pcdev->base + CICR0);
2231
2232 /* Stop DMA engine */
2233 pxa_dma_stop_channels(pcdev);
2234
2235 pxa_camera_destroy_formats(pcdev);
2236
2237 if (pcdev->mclk_clk) {
2238 v4l2_clk_unregister(pcdev->mclk_clk);
2239 pcdev->mclk_clk = NULL;
2240 }
2241
2242 video_unregister_device(&pcdev->vdev);
2243 pcdev->sensor = NULL;
2244
2245 mutex_unlock(&pcdev->mlock);
2246 }
2247
2248 static const struct v4l2_async_notifier_operations pxa_camera_sensor_ops = {
2249 .bound = pxa_camera_sensor_bound,
2250 .unbind = pxa_camera_sensor_unbind,
2251 };
2252
2253 /*
2254 * Driver probe, remove, suspend and resume operations
2255 */
2256 static int pxa_camera_suspend(struct device *dev)
2257 {
2258 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2259 int i = 0, ret = 0;
2260
2261 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
2262 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
2263 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
2264 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
2265 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
2266
2267 if (pcdev->sensor)
2268 ret = pxac_sensor_set_power(pcdev, 0);
2269
2270 return ret;
2271 }
2272
2273 static int pxa_camera_resume(struct device *dev)
2274 {
2275 struct pxa_camera_dev *pcdev = dev_get_drvdata(dev);
2276 int i = 0, ret = 0;
2277
2278 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
2279 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
2280 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
2281 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
2282 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
2283
2284 if (pcdev->sensor) {
2285 ret = pxac_sensor_set_power(pcdev, 1);
2286 }
2287
2288 /* Restart frame capture if active buffer exists */
2289 if (!ret && pcdev->active)
2290 pxa_camera_start_capture(pcdev);
2291
2292 return ret;
2293 }
2294
2295 static int pxa_camera_pdata_from_dt(struct device *dev,
2296 struct pxa_camera_dev *pcdev,
2297 struct v4l2_async_subdev *asd)
2298 {
2299 u32 mclk_rate;
2300 struct device_node *remote, *np = dev->of_node;
2301 struct v4l2_fwnode_endpoint ep = { .bus_type = 0 };
2302 int err = of_property_read_u32(np, "clock-frequency",
2303 &mclk_rate);
2304 if (!err) {
2305 pcdev->platform_flags |= PXA_CAMERA_MCLK_EN;
2306 pcdev->mclk = mclk_rate;
2307 }
2308
2309 np = of_graph_get_next_endpoint(np, NULL);
2310 if (!np) {
2311 dev_err(dev, "could not find endpoint\n");
2312 return -EINVAL;
2313 }
2314
2315 err = v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &ep);
2316 if (err) {
2317 dev_err(dev, "could not parse endpoint\n");
2318 goto out;
2319 }
2320
2321 switch (ep.bus.parallel.bus_width) {
2322 case 4:
2323 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4;
2324 break;
2325 case 5:
2326 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5;
2327 break;
2328 case 8:
2329 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8;
2330 break;
2331 case 9:
2332 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9;
2333 break;
2334 case 10:
2335 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2336 break;
2337 default:
2338 break;
2339 }
2340
2341 if (ep.bus.parallel.flags & V4L2_MBUS_MASTER)
2342 pcdev->platform_flags |= PXA_CAMERA_MASTER;
2343 if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2344 pcdev->platform_flags |= PXA_CAMERA_HSP;
2345 if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2346 pcdev->platform_flags |= PXA_CAMERA_VSP;
2347 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2348 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP;
2349 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
2350 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN;
2351
2352 asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
2353 remote = of_graph_get_remote_port(np);
2354 if (remote)
2355 asd->match.fwnode = of_fwnode_handle(remote);
2356 else
2357 dev_notice(dev, "no remote for %pOF\n", np);
2358
2359 out:
2360 of_node_put(np);
2361
2362 return err;
2363 }
2364
2365 static int pxa_camera_probe(struct platform_device *pdev)
2366 {
2367 struct pxa_camera_dev *pcdev;
2368 struct resource *res;
2369 void __iomem *base;
2370 struct dma_slave_config config = {
2371 .src_addr_width = 0,
2372 .src_maxburst = 8,
2373 .direction = DMA_DEV_TO_MEM,
2374 };
2375 char clk_name[V4L2_CLK_NAME_SIZE];
2376 int irq;
2377 int err = 0, i;
2378
2379 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2380 irq = platform_get_irq(pdev, 0);
2381 if (!res || irq < 0)
2382 return -ENODEV;
2383
2384 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
2385 if (!pcdev) {
2386 dev_err(&pdev->dev, "Could not allocate pcdev\n");
2387 return -ENOMEM;
2388 }
2389
2390 pcdev->clk = devm_clk_get(&pdev->dev, NULL);
2391 if (IS_ERR(pcdev->clk))
2392 return PTR_ERR(pcdev->clk);
2393
2394 pcdev->res = res;
2395
2396 pcdev->pdata = pdev->dev.platform_data;
2397 if (pcdev->pdata) {
2398 pcdev->platform_flags = pcdev->pdata->flags;
2399 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
2400 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2401 pcdev->asd.match.i2c.adapter_id =
2402 pcdev->pdata->sensor_i2c_adapter_id;
2403 pcdev->asd.match.i2c.address = pcdev->pdata->sensor_i2c_address;
2404 } else if (pdev->dev.of_node) {
2405 err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev, &pcdev->asd);
2406 } else {
2407 return -ENODEV;
2408 }
2409 if (err < 0)
2410 return err;
2411
2412 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
2413 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
2414 /*
2415 * Platform hasn't set available data widths. This is bad.
2416 * Warn and use a default.
2417 */
2418 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available data widths, using default 10 bit\n");
2419 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
2420 }
2421 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
2422 pcdev->width_flags = 1 << 7;
2423 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
2424 pcdev->width_flags |= 1 << 8;
2425 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
2426 pcdev->width_flags |= 1 << 9;
2427 if (!pcdev->mclk) {
2428 dev_warn(&pdev->dev,
2429 "mclk == 0! Please, fix your platform data. Using default 20MHz\n");
2430 pcdev->mclk = 20000000;
2431 }
2432
2433 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
2434
2435 INIT_LIST_HEAD(&pcdev->capture);
2436 spin_lock_init(&pcdev->lock);
2437 mutex_init(&pcdev->mlock);
2438
2439 /*
2440 * Request the regions.
2441 */
2442 base = devm_ioremap_resource(&pdev->dev, res);
2443 if (IS_ERR(base))
2444 return PTR_ERR(base);
2445
2446 pcdev->irq = irq;
2447 pcdev->base = base;
2448
2449 /* request dma */
2450 pcdev->dma_chans[0] = dma_request_slave_channel(&pdev->dev, "CI_Y");
2451 if (!pcdev->dma_chans[0]) {
2452 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2453 return -ENODEV;
2454 }
2455
2456 pcdev->dma_chans[1] = dma_request_slave_channel(&pdev->dev, "CI_U");
2457 if (!pcdev->dma_chans[1]) {
2458 dev_err(&pdev->dev, "Can't request DMA for Y\n");
2459 err = -ENODEV;
2460 goto exit_free_dma_y;
2461 }
2462
2463 pcdev->dma_chans[2] = dma_request_slave_channel(&pdev->dev, "CI_V");
2464 if (!pcdev->dma_chans[2]) {
2465 dev_err(&pdev->dev, "Can't request DMA for V\n");
2466 err = -ENODEV;
2467 goto exit_free_dma_u;
2468 }
2469
2470 for (i = 0; i < 3; i++) {
2471 config.src_addr = pcdev->res->start + CIBR0 + i * 8;
2472 err = dmaengine_slave_config(pcdev->dma_chans[i], &config);
2473 if (err < 0) {
2474 dev_err(&pdev->dev, "dma slave config failed: %d\n",
2475 err);
2476 goto exit_free_dma;
2477 }
2478 }
2479
2480 /* request irq */
2481 err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0,
2482 PXA_CAM_DRV_NAME, pcdev);
2483 if (err) {
2484 dev_err(&pdev->dev, "Camera interrupt register failed\n");
2485 goto exit_free_dma;
2486 }
2487
2488 tasklet_init(&pcdev->task_eof, pxa_camera_eof, (unsigned long)pcdev);
2489
2490 pxa_camera_activate(pcdev);
2491
2492 dev_set_drvdata(&pdev->dev, pcdev);
2493 err = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev);
2494 if (err)
2495 goto exit_deactivate;
2496
2497 v4l2_async_notifier_init(&pcdev->notifier);
2498
2499 err = v4l2_async_notifier_add_subdev(&pcdev->notifier, &pcdev->asd);
2500 if (err) {
2501 fwnode_handle_put(pcdev->asd.match.fwnode);
2502 goto exit_free_v4l2dev;
2503 }
2504
2505 pcdev->notifier.ops = &pxa_camera_sensor_ops;
2506
2507 if (!of_have_populated_dt())
2508 pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C;
2509
2510 err = pxa_camera_init_videobuf2(pcdev);
2511 if (err)
2512 goto exit_notifier_cleanup;
2513
2514 if (pcdev->mclk) {
2515 v4l2_clk_name_i2c(clk_name, sizeof(clk_name),
2516 pcdev->asd.match.i2c.adapter_id,
2517 pcdev->asd.match.i2c.address);
2518
2519 pcdev->mclk_clk = v4l2_clk_register(&pxa_camera_mclk_ops,
2520 clk_name, NULL);
2521 if (IS_ERR(pcdev->mclk_clk)) {
2522 err = PTR_ERR(pcdev->mclk_clk);
2523 goto exit_notifier_cleanup;
2524 }
2525 }
2526
2527 err = v4l2_async_notifier_register(&pcdev->v4l2_dev, &pcdev->notifier);
2528 if (err)
2529 goto exit_free_clk;
2530
2531 return 0;
2532 exit_free_clk:
2533 v4l2_clk_unregister(pcdev->mclk_clk);
2534 exit_notifier_cleanup:
2535 v4l2_async_notifier_cleanup(&pcdev->notifier);
2536 exit_free_v4l2dev:
2537 v4l2_device_unregister(&pcdev->v4l2_dev);
2538 exit_deactivate:
2539 pxa_camera_deactivate(pcdev);
2540 exit_free_dma:
2541 dma_release_channel(pcdev->dma_chans[2]);
2542 exit_free_dma_u:
2543 dma_release_channel(pcdev->dma_chans[1]);
2544 exit_free_dma_y:
2545 dma_release_channel(pcdev->dma_chans[0]);
2546 return err;
2547 }
2548
2549 static int pxa_camera_remove(struct platform_device *pdev)
2550 {
2551 struct pxa_camera_dev *pcdev = dev_get_drvdata(&pdev->dev);
2552
2553 pxa_camera_deactivate(pcdev);
2554 dma_release_channel(pcdev->dma_chans[0]);
2555 dma_release_channel(pcdev->dma_chans[1]);
2556 dma_release_channel(pcdev->dma_chans[2]);
2557
2558 v4l2_async_notifier_unregister(&pcdev->notifier);
2559 v4l2_async_notifier_cleanup(&pcdev->notifier);
2560
2561 if (pcdev->mclk_clk) {
2562 v4l2_clk_unregister(pcdev->mclk_clk);
2563 pcdev->mclk_clk = NULL;
2564 }
2565
2566 v4l2_device_unregister(&pcdev->v4l2_dev);
2567
2568 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
2569
2570 return 0;
2571 }
2572
2573 static const struct dev_pm_ops pxa_camera_pm = {
2574 .suspend = pxa_camera_suspend,
2575 .resume = pxa_camera_resume,
2576 };
2577
2578 static const struct of_device_id pxa_camera_of_match[] = {
2579 { .compatible = "marvell,pxa270-qci", },
2580 {},
2581 };
2582 MODULE_DEVICE_TABLE(of, pxa_camera_of_match);
2583
2584 static struct platform_driver pxa_camera_driver = {
2585 .driver = {
2586 .name = PXA_CAM_DRV_NAME,
2587 .pm = &pxa_camera_pm,
2588 .of_match_table = of_match_ptr(pxa_camera_of_match),
2589 },
2590 .probe = pxa_camera_probe,
2591 .remove = pxa_camera_remove,
2592 };
2593
2594 module_platform_driver(pxa_camera_driver);
2595
2596 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
2597 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
2598 MODULE_LICENSE("GPL");
2599 MODULE_VERSION(PXA_CAM_VERSION);
2600 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);
Linux with added FPC-III support