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blk-mq: always free hctx after request queue is freed
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_def.h
blob3d46975a5e5cf887aafe9df46d471f1bd424dbf5
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28 #include <linux/btree.h>
29
30 #include <scsi/scsi.h>
31 #include <scsi/scsi_host.h>
32 #include <scsi/scsi_device.h>
33 #include <scsi/scsi_cmnd.h>
34 #include <scsi/scsi_transport_fc.h>
35 #include <scsi/scsi_bsg_fc.h>
36
37 #include "qla_bsg.h"
38 #include "qla_nx.h"
39 #include "qla_nx2.h"
40 #include "qla_nvme.h"
41 #define QLA2XXX_DRIVER_NAME "qla2xxx"
42 #define QLA2XXX_APIDEV "ql2xapidev"
43 #define QLA2XXX_MANUFACTURER "QLogic Corporation"
44
45 /*
46 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
47 * but that's fine as we don't look at the last 24 ones for
48 * ISP2100 HBAs.
49 */
50 #define MAILBOX_REGISTER_COUNT_2100 8
51 #define MAILBOX_REGISTER_COUNT_2200 24
52 #define MAILBOX_REGISTER_COUNT 32
53
54 #define QLA2200A_RISC_ROM_VER 4
55 #define FPM_2300 6
56 #define FPM_2310 7
57
58 #include "qla_settings.h"
59
60 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
61
62 /*
63 * Data bit definitions
64 */
65 #define BIT_0 0x1
66 #define BIT_1 0x2
67 #define BIT_2 0x4
68 #define BIT_3 0x8
69 #define BIT_4 0x10
70 #define BIT_5 0x20
71 #define BIT_6 0x40
72 #define BIT_7 0x80
73 #define BIT_8 0x100
74 #define BIT_9 0x200
75 #define BIT_10 0x400
76 #define BIT_11 0x800
77 #define BIT_12 0x1000
78 #define BIT_13 0x2000
79 #define BIT_14 0x4000
80 #define BIT_15 0x8000
81 #define BIT_16 0x10000
82 #define BIT_17 0x20000
83 #define BIT_18 0x40000
84 #define BIT_19 0x80000
85 #define BIT_20 0x100000
86 #define BIT_21 0x200000
87 #define BIT_22 0x400000
88 #define BIT_23 0x800000
89 #define BIT_24 0x1000000
90 #define BIT_25 0x2000000
91 #define BIT_26 0x4000000
92 #define BIT_27 0x8000000
93 #define BIT_28 0x10000000
94 #define BIT_29 0x20000000
95 #define BIT_30 0x40000000
96 #define BIT_31 0x80000000
97
98 #define LSB(x) ((uint8_t)(x))
99 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
100
101 #define LSW(x) ((uint16_t)(x))
102 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
103
104 #define LSD(x) ((uint32_t)((uint64_t)(x)))
105 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
106
107 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
108
109 /*
110 * I/O register
111 */
112
113 #define RD_REG_BYTE(addr) readb(addr)
114 #define RD_REG_WORD(addr) readw(addr)
115 #define RD_REG_DWORD(addr) readl(addr)
116 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
117 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
118 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
119 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
120 #define WRT_REG_WORD(addr, data) writew(data,addr)
121 #define WRT_REG_DWORD(addr, data) writel(data,addr)
122
123 /*
124 * ISP83XX specific remote register addresses
125 */
126 #define QLA83XX_LED_PORT0 0x00201320
127 #define QLA83XX_LED_PORT1 0x00201328
128 #define QLA83XX_IDC_DEV_STATE 0x22102384
129 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380
130 #define QLA83XX_IDC_MINOR_VERSION 0x22102398
131 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388
132 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c
133 #define QLA83XX_IDC_CONTROL 0x22102390
134 #define QLA83XX_IDC_AUDIT 0x22102394
135 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
136 #define QLA83XX_DRIVER_LOCKID 0x22102104
137 #define QLA83XX_DRIVER_LOCK 0x8111c028
138 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c
139 #define QLA83XX_FLASH_LOCKID 0x22102100
140 #define QLA83XX_FLASH_LOCK 0x8111c010
141 #define QLA83XX_FLASH_UNLOCK 0x8111c014
142 #define QLA83XX_DEV_PARTINFO1 0x221023e0
143 #define QLA83XX_DEV_PARTINFO2 0x221023e4
144 #define QLA83XX_FW_HEARTBEAT 0x221020b0
145 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8
146 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac
147
148 /* 83XX: Macros defining 8200 AEN Reason codes */
149 #define IDC_DEVICE_STATE_CHANGE BIT_0
150 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
151 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
152 #define IDC_HEARTBEAT_FAILURE BIT_3
153
154 /* 83XX: Macros defining 8200 AEN Error-levels */
155 #define ERR_LEVEL_NON_FATAL 0x1
156 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2
157 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
158
159 /* 83XX: Macros for IDC Version */
160 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
161 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
162
163 /* 83XX: Macros for scheduling dpc tasks */
164 #define QLA83XX_NIC_CORE_RESET 0x1
165 #define QLA83XX_IDC_STATE_HANDLER 0x2
166 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
167
168 /* 83XX: Macros for defining IDC-Control bits */
169 #define QLA83XX_IDC_RESET_DISABLED BIT_0
170 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
171
172 /* 83XX: Macros for different timeouts */
173 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
174 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
175 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
176
177 /* 83XX: Macros for defining class in DEV-Partition Info register */
178 #define QLA83XX_CLASS_TYPE_NONE 0x0
179 #define QLA83XX_CLASS_TYPE_NIC 0x1
180 #define QLA83XX_CLASS_TYPE_FCOE 0x2
181 #define QLA83XX_CLASS_TYPE_ISCSI 0x3
182
183 /* 83XX: Macros for IDC Lock-Recovery stages */
184 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
185 * lock-recovery
186 */
187 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
188
189 /* 83XX: Macros for IDC Audit type */
190 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
191 * dev-state change to NEED-RESET
192 * or NEED-QUIESCENT
193 */
194 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
195 * reset-recovery completion is
196 * second
197 */
198 /* ISP2031: Values for laser on/off */
199 #define PORT_0_2031 0x00201340
200 #define PORT_1_2031 0x00201350
201 #define LASER_ON_2031 0x01800100
202 #define LASER_OFF_2031 0x01800180
203
204 /*
205 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
206 * 133Mhz slot.
207 */
208 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
209 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
210
211 /*
212 * Fibre Channel device definitions.
213 */
214 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
215 #define MAX_FIBRE_DEVICES_2100 512
216 #define MAX_FIBRE_DEVICES_2400 2048
217 #define MAX_FIBRE_DEVICES_LOOP 128
218 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
219 #define LOOPID_MAP_SIZE (ha->max_fibre_devices)
220 #define MAX_FIBRE_LUNS 0xFFFF
221 #define MAX_HOST_COUNT 16
222
223 /*
224 * Host adapter default definitions.
225 */
226 #define MAX_BUSES 1 /* We only have one bus today */
227 #define MIN_LUNS 8
228 #define MAX_LUNS MAX_FIBRE_LUNS
229 #define MAX_CMDS_PER_LUN 255
230
231 /*
232 * Fibre Channel device definitions.
233 */
234 #define SNS_LAST_LOOP_ID_2100 0xfe
235 #define SNS_LAST_LOOP_ID_2300 0x7ff
236
237 #define LAST_LOCAL_LOOP_ID 0x7d
238 #define SNS_FL_PORT 0x7e
239 #define FABRIC_CONTROLLER 0x7f
240 #define SIMPLE_NAME_SERVER 0x80
241 #define SNS_FIRST_LOOP_ID 0x81
242 #define MANAGEMENT_SERVER 0xfe
243 #define BROADCAST 0xff
244
245 /*
246 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
247 * valid range of an N-PORT id is 0 through 0x7ef.
248 */
249 #define NPH_LAST_HANDLE 0x7ee
250 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */
251 #define NPH_SNS 0x7fc /* FFFFFC */
252 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
253 #define NPH_F_PORT 0x7fe /* FFFFFE */
254 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
255
256 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
257
258 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
259 #include "qla_fw.h"
260
261 struct name_list_extended {
262 struct get_name_list_extended *l;
263 dma_addr_t ldma;
264 struct list_head fcports;
265 u32 size;
266 u8 sent;
267 };
268 /*
269 * Timeout timer counts in seconds
270 */
271 #define PORT_RETRY_TIME 1
272 #define LOOP_DOWN_TIMEOUT 60
273 #define LOOP_DOWN_TIME 255 /* 240 */
274 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
275
276 #define DEFAULT_OUTSTANDING_COMMANDS 4096
277 #define MIN_OUTSTANDING_COMMANDS 128
278
279 /* ISP request and response entry counts (37-65535) */
280 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
281 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
282 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
283 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */
284 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/
285 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
286 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
287 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
288 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
289 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
290 #define FW_DEF_EXCHANGES_CNT 2048
291 #define FW_MAX_EXCHANGES_CNT (32 * 1024)
292 #define REDUCE_EXCHANGES_CNT (8 * 1024)
293
294 struct req_que;
295 struct qla_tgt_sess;
296
297 /*
298 * SCSI Request Block
299 */
300 struct srb_cmd {
301 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
302 uint32_t request_sense_length;
303 uint32_t fw_sense_length;
304 uint8_t *request_sense_ptr;
305 void *ctx;
306 };
307
308 /*
309 * SRB flag definitions
310 */
311 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
312 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
313 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
314 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
315 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
316 #define SRB_WAKEUP_ON_COMP BIT_6
317 #define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */
318
319 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
320 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
321
322 /*
323 * 24 bit port ID type definition.
324 */
325 typedef union {
326 uint32_t b24 : 24;
327
328 struct {
329 #ifdef __BIG_ENDIAN
330 uint8_t domain;
331 uint8_t area;
332 uint8_t al_pa;
333 #elif defined(__LITTLE_ENDIAN)
334 uint8_t al_pa;
335 uint8_t area;
336 uint8_t domain;
337 #else
338 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
339 #endif
340 uint8_t rsvd_1;
341 } b;
342 } port_id_t;
343 #define INVALID_PORT_ID 0xFFFFFF
344
345 struct els_logo_payload {
346 uint8_t opcode;
347 uint8_t rsvd[3];
348 uint8_t s_id[3];
349 uint8_t rsvd1[1];
350 uint8_t wwpn[WWN_SIZE];
351 };
352
353 struct els_plogi_payload {
354 uint8_t opcode;
355 uint8_t rsvd[3];
356 uint8_t data[112];
357 };
358
359 struct ct_arg {
360 void *iocb;
361 u16 nport_handle;
362 dma_addr_t req_dma;
363 dma_addr_t rsp_dma;
364 u32 req_size;
365 u32 rsp_size;
366 u32 req_allocated_size;
367 u32 rsp_allocated_size;
368 void *req;
369 void *rsp;
370 port_id_t id;
371 };
372
373 /*
374 * SRB extensions.
375 */
376 struct srb_iocb {
377 union {
378 struct {
379 uint16_t flags;
380 #define SRB_LOGIN_RETRIED BIT_0
381 #define SRB_LOGIN_COND_PLOGI BIT_1
382 #define SRB_LOGIN_SKIP_PRLI BIT_2
383 #define SRB_LOGIN_NVME_PRLI BIT_3
384 #define SRB_LOGIN_PRLI_ONLY BIT_4
385 uint16_t data[2];
386 u32 iop[2];
387 } logio;
388 struct {
389 #define ELS_DCMD_TIMEOUT 20
390 #define ELS_DCMD_LOGO 0x5
391 uint32_t flags;
392 uint32_t els_cmd;
393 struct completion comp;
394 struct els_logo_payload *els_logo_pyld;
395 dma_addr_t els_logo_pyld_dma;
396 } els_logo;
397 struct {
398 #define ELS_DCMD_PLOGI 0x3
399 uint32_t flags;
400 uint32_t els_cmd;
401 struct completion comp;
402 struct els_plogi_payload *els_plogi_pyld;
403 struct els_plogi_payload *els_resp_pyld;
404 u32 tx_size;
405 u32 rx_size;
406 dma_addr_t els_plogi_pyld_dma;
407 dma_addr_t els_resp_pyld_dma;
408 uint32_t fw_status[3];
409 __le16 comp_status;
410 __le16 len;
411 } els_plogi;
412 struct {
413 /*
414 * Values for flags field below are as
415 * defined in tsk_mgmt_entry struct
416 * for control_flags field in qla_fw.h.
417 */
418 uint64_t lun;
419 uint32_t flags;
420 uint32_t data;
421 struct completion comp;
422 __le16 comp_status;
423 } tmf;
424 struct {
425 #define SRB_FXDISC_REQ_DMA_VALID BIT_0
426 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
427 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2
428 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3
429 #define FXDISC_TIMEOUT 20
430 uint8_t flags;
431 uint32_t req_len;
432 uint32_t rsp_len;
433 void *req_addr;
434 void *rsp_addr;
435 dma_addr_t req_dma_handle;
436 dma_addr_t rsp_dma_handle;
437 __le32 adapter_id;
438 __le32 adapter_id_hi;
439 __le16 req_func_type;
440 __le32 req_data;
441 __le32 req_data_extra;
442 __le32 result;
443 __le32 seq_number;
444 __le16 fw_flags;
445 struct completion fxiocb_comp;
446 __le32 reserved_0;
447 uint8_t reserved_1;
448 } fxiocb;
449 struct {
450 uint32_t cmd_hndl;
451 __le16 comp_status;
452 __le16 req_que_no;
453 struct completion comp;
454 } abt;
455 struct ct_arg ctarg;
456 #define MAX_IOCB_MB_REG 28
457 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
458 struct {
459 __le16 in_mb[MAX_IOCB_MB_REG]; /* from FW */
460 __le16 out_mb[MAX_IOCB_MB_REG]; /* to FW */
461 void *out, *in;
462 dma_addr_t out_dma, in_dma;
463 struct completion comp;
464 int rc;
465 } mbx;
466 struct {
467 struct imm_ntfy_from_isp *ntfy;
468 } nack;
469 struct {
470 __le16 comp_status;
471 uint16_t rsp_pyld_len;
472 uint8_t aen_op;
473 void *desc;
474
475 /* These are only used with ls4 requests */
476 int cmd_len;
477 int rsp_len;
478 dma_addr_t cmd_dma;
479 dma_addr_t rsp_dma;
480 enum nvmefc_fcp_datadir dir;
481 uint32_t dl;
482 uint32_t timeout_sec;
483 struct list_head entry;
484 } nvme;
485 struct {
486 u16 cmd;
487 u16 vp_index;
488 } ctrlvp;
489 } u;
490
491 struct timer_list timer;
492 void (*timeout)(void *);
493 };
494
495 /* Values for srb_ctx type */
496 #define SRB_LOGIN_CMD 1
497 #define SRB_LOGOUT_CMD 2
498 #define SRB_ELS_CMD_RPT 3
499 #define SRB_ELS_CMD_HST 4
500 #define SRB_CT_CMD 5
501 #define SRB_ADISC_CMD 6
502 #define SRB_TM_CMD 7
503 #define SRB_SCSI_CMD 8
504 #define SRB_BIDI_CMD 9
505 #define SRB_FXIOCB_DCMD 10
506 #define SRB_FXIOCB_BCMD 11
507 #define SRB_ABT_CMD 12
508 #define SRB_ELS_DCMD 13
509 #define SRB_MB_IOCB 14
510 #define SRB_CT_PTHRU_CMD 15
511 #define SRB_NACK_PLOGI 16
512 #define SRB_NACK_PRLI 17
513 #define SRB_NACK_LOGO 18
514 #define SRB_NVME_CMD 19
515 #define SRB_NVME_LS 20
516 #define SRB_PRLI_CMD 21
517 #define SRB_CTRL_VP 22
518 #define SRB_PRLO_CMD 23
519
520 enum {
521 TYPE_SRB,
522 TYPE_TGT_CMD,
523 TYPE_TGT_TMCMD, /* task management */
524 };
525
526 typedef struct srb {
527 /*
528 * Do not move cmd_type field, it needs to
529 * line up with qla_tgt_cmd->cmd_type
530 */
531 uint8_t cmd_type;
532 uint8_t pad[3];
533 atomic_t ref_count;
534 wait_queue_head_t nvme_ls_waitq;
535 struct fc_port *fcport;
536 struct scsi_qla_host *vha;
537 uint32_t handle;
538 uint16_t flags;
539 uint16_t type;
540 const char *name;
541 int iocbs;
542 struct qla_qpair *qpair;
543 struct list_head elem;
544 u32 gen1; /* scratch */
545 u32 gen2; /* scratch */
546 int rc;
547 int retry_count;
548 struct completion comp;
549 union {
550 struct srb_iocb iocb_cmd;
551 struct bsg_job *bsg_job;
552 struct srb_cmd scmd;
553 } u;
554 void (*done)(void *, int);
555 void (*free)(void *);
556 } srb_t;
557
558 #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
559 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
560 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
561
562 #define GET_CMD_SENSE_LEN(sp) \
563 (sp->u.scmd.request_sense_length)
564 #define SET_CMD_SENSE_LEN(sp, len) \
565 (sp->u.scmd.request_sense_length = len)
566 #define GET_CMD_SENSE_PTR(sp) \
567 (sp->u.scmd.request_sense_ptr)
568 #define SET_CMD_SENSE_PTR(sp, ptr) \
569 (sp->u.scmd.request_sense_ptr = ptr)
570 #define GET_FW_SENSE_LEN(sp) \
571 (sp->u.scmd.fw_sense_length)
572 #define SET_FW_SENSE_LEN(sp, len) \
573 (sp->u.scmd.fw_sense_length = len)
574
575 struct msg_echo_lb {
576 dma_addr_t send_dma;
577 dma_addr_t rcv_dma;
578 uint16_t req_sg_cnt;
579 uint16_t rsp_sg_cnt;
580 uint16_t options;
581 uint32_t transfer_size;
582 uint32_t iteration_count;
583 };
584
585 /*
586 * ISP I/O Register Set structure definitions.
587 */
588 struct device_reg_2xxx {
589 uint16_t flash_address; /* Flash BIOS address */
590 uint16_t flash_data; /* Flash BIOS data */
591 uint16_t unused_1[1]; /* Gap */
592 uint16_t ctrl_status; /* Control/Status */
593 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
594 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
595 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
596
597 uint16_t ictrl; /* Interrupt control */
598 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
599 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
600
601 uint16_t istatus; /* Interrupt status */
602 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
603
604 uint16_t semaphore; /* Semaphore */
605 uint16_t nvram; /* NVRAM register. */
606 #define NVR_DESELECT 0
607 #define NVR_BUSY BIT_15
608 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
609 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
610 #define NVR_DATA_IN BIT_3
611 #define NVR_DATA_OUT BIT_2
612 #define NVR_SELECT BIT_1
613 #define NVR_CLOCK BIT_0
614
615 #define NVR_WAIT_CNT 20000
616
617 union {
618 struct {
619 uint16_t mailbox0;
620 uint16_t mailbox1;
621 uint16_t mailbox2;
622 uint16_t mailbox3;
623 uint16_t mailbox4;
624 uint16_t mailbox5;
625 uint16_t mailbox6;
626 uint16_t mailbox7;
627 uint16_t unused_2[59]; /* Gap */
628 } __attribute__((packed)) isp2100;
629 struct {
630 /* Request Queue */
631 uint16_t req_q_in; /* In-Pointer */
632 uint16_t req_q_out; /* Out-Pointer */
633 /* Response Queue */
634 uint16_t rsp_q_in; /* In-Pointer */
635 uint16_t rsp_q_out; /* Out-Pointer */
636
637 /* RISC to Host Status */
638 uint32_t host_status;
639 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
640 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
641
642 /* Host to Host Semaphore */
643 uint16_t host_semaphore;
644 uint16_t unused_3[17]; /* Gap */
645 uint16_t mailbox0;
646 uint16_t mailbox1;
647 uint16_t mailbox2;
648 uint16_t mailbox3;
649 uint16_t mailbox4;
650 uint16_t mailbox5;
651 uint16_t mailbox6;
652 uint16_t mailbox7;
653 uint16_t mailbox8;
654 uint16_t mailbox9;
655 uint16_t mailbox10;
656 uint16_t mailbox11;
657 uint16_t mailbox12;
658 uint16_t mailbox13;
659 uint16_t mailbox14;
660 uint16_t mailbox15;
661 uint16_t mailbox16;
662 uint16_t mailbox17;
663 uint16_t mailbox18;
664 uint16_t mailbox19;
665 uint16_t mailbox20;
666 uint16_t mailbox21;
667 uint16_t mailbox22;
668 uint16_t mailbox23;
669 uint16_t mailbox24;
670 uint16_t mailbox25;
671 uint16_t mailbox26;
672 uint16_t mailbox27;
673 uint16_t mailbox28;
674 uint16_t mailbox29;
675 uint16_t mailbox30;
676 uint16_t mailbox31;
677 uint16_t fb_cmd;
678 uint16_t unused_4[10]; /* Gap */
679 } __attribute__((packed)) isp2300;
680 } u;
681
682 uint16_t fpm_diag_config;
683 uint16_t unused_5[0x4]; /* Gap */
684 uint16_t risc_hw;
685 uint16_t unused_5_1; /* Gap */
686 uint16_t pcr; /* Processor Control Register. */
687 uint16_t unused_6[0x5]; /* Gap */
688 uint16_t mctr; /* Memory Configuration and Timing. */
689 uint16_t unused_7[0x3]; /* Gap */
690 uint16_t fb_cmd_2100; /* Unused on 23XX */
691 uint16_t unused_8[0x3]; /* Gap */
692 uint16_t hccr; /* Host command & control register. */
693 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
694 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
695 /* HCCR commands */
696 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
697 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
698 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
699 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
700 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
701 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
702 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
703 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
704
705 uint16_t unused_9[5]; /* Gap */
706 uint16_t gpiod; /* GPIO Data register. */
707 uint16_t gpioe; /* GPIO Enable register. */
708 #define GPIO_LED_MASK 0x00C0
709 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
710 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
711 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
712 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
713 #define GPIO_LED_ALL_OFF 0x0000
714 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
715 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
716
717 union {
718 struct {
719 uint16_t unused_10[8]; /* Gap */
720 uint16_t mailbox8;
721 uint16_t mailbox9;
722 uint16_t mailbox10;
723 uint16_t mailbox11;
724 uint16_t mailbox12;
725 uint16_t mailbox13;
726 uint16_t mailbox14;
727 uint16_t mailbox15;
728 uint16_t mailbox16;
729 uint16_t mailbox17;
730 uint16_t mailbox18;
731 uint16_t mailbox19;
732 uint16_t mailbox20;
733 uint16_t mailbox21;
734 uint16_t mailbox22;
735 uint16_t mailbox23; /* Also probe reg. */
736 } __attribute__((packed)) isp2200;
737 } u_end;
738 };
739
740 struct device_reg_25xxmq {
741 uint32_t req_q_in;
742 uint32_t req_q_out;
743 uint32_t rsp_q_in;
744 uint32_t rsp_q_out;
745 uint32_t atio_q_in;
746 uint32_t atio_q_out;
747 };
748
749
750 struct device_reg_fx00 {
751 uint32_t mailbox0; /* 00 */
752 uint32_t mailbox1; /* 04 */
753 uint32_t mailbox2; /* 08 */
754 uint32_t mailbox3; /* 0C */
755 uint32_t mailbox4; /* 10 */
756 uint32_t mailbox5; /* 14 */
757 uint32_t mailbox6; /* 18 */
758 uint32_t mailbox7; /* 1C */
759 uint32_t mailbox8; /* 20 */
760 uint32_t mailbox9; /* 24 */
761 uint32_t mailbox10; /* 28 */
762 uint32_t mailbox11;
763 uint32_t mailbox12;
764 uint32_t mailbox13;
765 uint32_t mailbox14;
766 uint32_t mailbox15;
767 uint32_t mailbox16;
768 uint32_t mailbox17;
769 uint32_t mailbox18;
770 uint32_t mailbox19;
771 uint32_t mailbox20;
772 uint32_t mailbox21;
773 uint32_t mailbox22;
774 uint32_t mailbox23;
775 uint32_t mailbox24;
776 uint32_t mailbox25;
777 uint32_t mailbox26;
778 uint32_t mailbox27;
779 uint32_t mailbox28;
780 uint32_t mailbox29;
781 uint32_t mailbox30;
782 uint32_t mailbox31;
783 uint32_t aenmailbox0;
784 uint32_t aenmailbox1;
785 uint32_t aenmailbox2;
786 uint32_t aenmailbox3;
787 uint32_t aenmailbox4;
788 uint32_t aenmailbox5;
789 uint32_t aenmailbox6;
790 uint32_t aenmailbox7;
791 /* Request Queue. */
792 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */
793 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */
794 /* Response Queue. */
795 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */
796 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */
797 /* Init values shadowed on FW Up Event */
798 uint32_t initval0; /* B0 */
799 uint32_t initval1; /* B4 */
800 uint32_t initval2; /* B8 */
801 uint32_t initval3; /* BC */
802 uint32_t initval4; /* C0 */
803 uint32_t initval5; /* C4 */
804 uint32_t initval6; /* C8 */
805 uint32_t initval7; /* CC */
806 uint32_t fwheartbeat; /* D0 */
807 uint32_t pseudoaen; /* D4 */
808 };
809
810
811
812 typedef union {
813 struct device_reg_2xxx isp;
814 struct device_reg_24xx isp24;
815 struct device_reg_25xxmq isp25mq;
816 struct device_reg_82xx isp82;
817 struct device_reg_fx00 ispfx00;
818 } __iomem device_reg_t;
819
820 #define ISP_REQ_Q_IN(ha, reg) \
821 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
822 &(reg)->u.isp2100.mailbox4 : \
823 &(reg)->u.isp2300.req_q_in)
824 #define ISP_REQ_Q_OUT(ha, reg) \
825 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
826 &(reg)->u.isp2100.mailbox4 : \
827 &(reg)->u.isp2300.req_q_out)
828 #define ISP_RSP_Q_IN(ha, reg) \
829 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
830 &(reg)->u.isp2100.mailbox5 : \
831 &(reg)->u.isp2300.rsp_q_in)
832 #define ISP_RSP_Q_OUT(ha, reg) \
833 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
834 &(reg)->u.isp2100.mailbox5 : \
835 &(reg)->u.isp2300.rsp_q_out)
836
837 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
838 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
839
840 #define MAILBOX_REG(ha, reg, num) \
841 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
842 (num < 8 ? \
843 &(reg)->u.isp2100.mailbox0 + (num) : \
844 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
845 &(reg)->u.isp2300.mailbox0 + (num))
846 #define RD_MAILBOX_REG(ha, reg, num) \
847 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
848 #define WRT_MAILBOX_REG(ha, reg, num, data) \
849 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
850
851 #define FB_CMD_REG(ha, reg) \
852 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
853 &(reg)->fb_cmd_2100 : \
854 &(reg)->u.isp2300.fb_cmd)
855 #define RD_FB_CMD_REG(ha, reg) \
856 RD_REG_WORD(FB_CMD_REG(ha, reg))
857 #define WRT_FB_CMD_REG(ha, reg, data) \
858 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
859
860 typedef struct {
861 uint32_t out_mb; /* outbound from driver */
862 uint32_t in_mb; /* Incoming from RISC */
863 uint16_t mb[MAILBOX_REGISTER_COUNT];
864 long buf_size;
865 void *bufp;
866 uint32_t tov;
867 uint8_t flags;
868 #define MBX_DMA_IN BIT_0
869 #define MBX_DMA_OUT BIT_1
870 #define IOCTL_CMD BIT_2
871 } mbx_cmd_t;
872
873 struct mbx_cmd_32 {
874 uint32_t out_mb; /* outbound from driver */
875 uint32_t in_mb; /* Incoming from RISC */
876 uint32_t mb[MAILBOX_REGISTER_COUNT];
877 long buf_size;
878 void *bufp;
879 uint32_t tov;
880 uint8_t flags;
881 #define MBX_DMA_IN BIT_0
882 #define MBX_DMA_OUT BIT_1
883 #define IOCTL_CMD BIT_2
884 };
885
886
887 #define MBX_TOV_SECONDS 30
888
889 /*
890 * ISP product identification definitions in mailboxes after reset.
891 */
892 #define PROD_ID_1 0x4953
893 #define PROD_ID_2 0x0000
894 #define PROD_ID_2a 0x5020
895 #define PROD_ID_3 0x2020
896
897 /*
898 * ISP mailbox Self-Test status codes
899 */
900 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
901 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
902 #define MBS_BUSY 4 /* Busy. */
903
904 /*
905 * ISP mailbox command complete status codes
906 */
907 #define MBS_COMMAND_COMPLETE 0x4000
908 #define MBS_INVALID_COMMAND 0x4001
909 #define MBS_HOST_INTERFACE_ERROR 0x4002
910 #define MBS_TEST_FAILED 0x4003
911 #define MBS_COMMAND_ERROR 0x4005
912 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
913 #define MBS_PORT_ID_USED 0x4007
914 #define MBS_LOOP_ID_USED 0x4008
915 #define MBS_ALL_IDS_IN_USE 0x4009
916 #define MBS_NOT_LOGGED_IN 0x400A
917 #define MBS_LINK_DOWN_ERROR 0x400B
918 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
919
920 /*
921 * ISP mailbox asynchronous event status codes
922 */
923 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
924 #define MBA_RESET 0x8001 /* Reset Detected. */
925 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
926 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
927 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
928 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
929 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
930 /* occurred. */
931 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
932 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
933 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
934 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
935 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
936 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
937 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
938 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
939 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
940 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
941 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
942 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
943 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
944 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
945 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
946 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
947 /* used. */
948 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
949 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
950 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
951 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
952 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
953 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
954 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
955 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
956 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
957 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
958 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
959 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
960 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
961 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
962 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */
963 #define MBA_FW_STARTING 0x8051 /* Firmware starting */
964 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */
965 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */
966 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */
967 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */
968 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */
969 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */
970 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */
971 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change
972 Notification */
973 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */
974 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */
975 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */
976 /* 83XX FCoE specific */
977 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
978
979 /* Interrupt type codes */
980 #define INTR_ROM_MB_SUCCESS 0x1
981 #define INTR_ROM_MB_FAILED 0x2
982 #define INTR_MB_SUCCESS 0x10
983 #define INTR_MB_FAILED 0x11
984 #define INTR_ASYNC_EVENT 0x12
985 #define INTR_RSP_QUE_UPDATE 0x13
986 #define INTR_RSP_QUE_UPDATE_83XX 0x14
987 #define INTR_ATIO_QUE_UPDATE 0x1C
988 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D
989 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E
990
991 /* ISP mailbox loopback echo diagnostic error code */
992 #define MBS_LB_RESET 0x17
993 /*
994 * Firmware options 1, 2, 3.
995 */
996 #define FO1_AE_ON_LIPF8 BIT_0
997 #define FO1_AE_ALL_LIP_RESET BIT_1
998 #define FO1_CTIO_RETRY BIT_3
999 #define FO1_DISABLE_LIP_F7_SW BIT_4
1000 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
1001 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
1002 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
1003 #define FO1_SET_EMPHASIS_SWING BIT_8
1004 #define FO1_AE_AUTO_BYPASS BIT_9
1005 #define FO1_ENABLE_PURE_IOCB BIT_10
1006 #define FO1_AE_PLOGI_RJT BIT_11
1007 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
1008 #define FO1_AE_QUEUE_FULL BIT_13
1009
1010 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
1011 #define FO2_REV_LOOPBACK BIT_1
1012
1013 #define FO3_ENABLE_EMERG_IOCB BIT_0
1014 #define FO3_AE_RND_ERROR BIT_1
1015
1016 /* 24XX additional firmware options */
1017 #define ADD_FO_COUNT 3
1018 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
1019 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
1020
1021 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1022
1023 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
1024
1025 /*
1026 * ISP mailbox commands
1027 */
1028 #define MBC_LOAD_RAM 1 /* Load RAM. */
1029 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
1030 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
1031 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
1032 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
1033 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
1034 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
1035 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
1036 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
1037 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
1038 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
1039 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
1040 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
1041 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
1042 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
1043 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
1044 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
1045 #define MBC_RESET 0x18 /* Reset. */
1046 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
1047 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */
1048 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
1049 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
1050 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
1051 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
1052 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/
1053 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
1054 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
1055 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
1056 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
1057 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
1058 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
1059 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
1060 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
1061 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
1062 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
1063 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
1064 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
1065 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
1066 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
1067 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
1068 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */
1069 #define MBC_DATA_RATE 0x5d /* Data Rate */
1070 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
1071 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
1072 /* Initialization Procedure */
1073 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
1074 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
1075 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
1076 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
1077 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
1078 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
1079 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
1080 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
1081 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
1082 #define MBC_LIP_RESET 0x6c /* LIP reset. */
1083 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
1084 /* commandd. */
1085 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
1086 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
1087 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
1088 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
1089 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
1090 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
1091 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
1092 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
1093 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
1094 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
1095 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
1096
1097 /*
1098 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones
1099 * should be defined with MBC_MR_*
1100 */
1101 #define MBC_MR_DRV_SHUTDOWN 0x6A
1102
1103 /*
1104 * ISP24xx mailbox commands
1105 */
1106 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */
1107 #define MBC_READ_SERDES 0x4 /* Read serdes word. */
1108 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */
1109 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
1110 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
1111 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
1112 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
1113 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
1114 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
1115 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
1116 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
1117 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
1118 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */
1119 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
1120 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
1121 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
1122 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
1123 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
1124 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
1125 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */
1126 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
1127 #define MBC_PORT_RESET 0x120 /* Port Reset */
1128 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
1129 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
1130
1131 /*
1132 * ISP81xx mailbox commands
1133 */
1134 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
1135
1136 /*
1137 * ISP8044 mailbox commands
1138 */
1139 #define MBC_SET_GET_ETH_SERDES_REG 0x150
1140 #define HCS_WRITE_SERDES 0x3
1141 #define HCS_READ_SERDES 0x4
1142
1143 /* Firmware return data sizes */
1144 #define FCAL_MAP_SIZE 128
1145
1146 /* Mailbox bit definitions for out_mb and in_mb */
1147 #define MBX_31 BIT_31
1148 #define MBX_30 BIT_30
1149 #define MBX_29 BIT_29
1150 #define MBX_28 BIT_28
1151 #define MBX_27 BIT_27
1152 #define MBX_26 BIT_26
1153 #define MBX_25 BIT_25
1154 #define MBX_24 BIT_24
1155 #define MBX_23 BIT_23
1156 #define MBX_22 BIT_22
1157 #define MBX_21 BIT_21
1158 #define MBX_20 BIT_20
1159 #define MBX_19 BIT_19
1160 #define MBX_18 BIT_18
1161 #define MBX_17 BIT_17
1162 #define MBX_16 BIT_16
1163 #define MBX_15 BIT_15
1164 #define MBX_14 BIT_14
1165 #define MBX_13 BIT_13
1166 #define MBX_12 BIT_12
1167 #define MBX_11 BIT_11
1168 #define MBX_10 BIT_10
1169 #define MBX_9 BIT_9
1170 #define MBX_8 BIT_8
1171 #define MBX_7 BIT_7
1172 #define MBX_6 BIT_6
1173 #define MBX_5 BIT_5
1174 #define MBX_4 BIT_4
1175 #define MBX_3 BIT_3
1176 #define MBX_2 BIT_2
1177 #define MBX_1 BIT_1
1178 #define MBX_0 BIT_0
1179
1180 #define RNID_TYPE_PORT_LOGIN 0x7
1181 #define RNID_TYPE_SET_VERSION 0x9
1182 #define RNID_TYPE_ASIC_TEMP 0xC
1183
1184 /*
1185 * Firmware state codes from get firmware state mailbox command
1186 */
1187 #define FSTATE_CONFIG_WAIT 0
1188 #define FSTATE_WAIT_AL_PA 1
1189 #define FSTATE_WAIT_LOGIN 2
1190 #define FSTATE_READY 3
1191 #define FSTATE_LOSS_OF_SYNC 4
1192 #define FSTATE_ERROR 5
1193 #define FSTATE_REINIT 6
1194 #define FSTATE_NON_PART 7
1195
1196 #define FSTATE_CONFIG_CORRECT 0
1197 #define FSTATE_P2P_RCV_LIP 1
1198 #define FSTATE_P2P_CHOOSE_LOOP 2
1199 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
1200 #define FSTATE_FATAL_ERROR 4
1201 #define FSTATE_LOOP_BACK_CONN 5
1202
1203 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1204 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1205 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
1206 #define QLA27XX_PRIMARY_IMAGE 1
1207 #define QLA27XX_SECONDARY_IMAGE 2
1208
1209 /*
1210 * Port Database structure definition
1211 * Little endian except where noted.
1212 */
1213 #define PORT_DATABASE_SIZE 128 /* bytes */
1214 typedef struct {
1215 uint8_t options;
1216 uint8_t control;
1217 uint8_t master_state;
1218 uint8_t slave_state;
1219 uint8_t reserved[2];
1220 uint8_t hard_address;
1221 uint8_t reserved_1;
1222 uint8_t port_id[4];
1223 uint8_t node_name[WWN_SIZE];
1224 uint8_t port_name[WWN_SIZE];
1225 uint16_t execution_throttle;
1226 uint16_t execution_count;
1227 uint8_t reset_count;
1228 uint8_t reserved_2;
1229 uint16_t resource_allocation;
1230 uint16_t current_allocation;
1231 uint16_t queue_head;
1232 uint16_t queue_tail;
1233 uint16_t transmit_execution_list_next;
1234 uint16_t transmit_execution_list_previous;
1235 uint16_t common_features;
1236 uint16_t total_concurrent_sequences;
1237 uint16_t RO_by_information_category;
1238 uint8_t recipient;
1239 uint8_t initiator;
1240 uint16_t receive_data_size;
1241 uint16_t concurrent_sequences;
1242 uint16_t open_sequences_per_exchange;
1243 uint16_t lun_abort_flags;
1244 uint16_t lun_stop_flags;
1245 uint16_t stop_queue_head;
1246 uint16_t stop_queue_tail;
1247 uint16_t port_retry_timer;
1248 uint16_t next_sequence_id;
1249 uint16_t frame_count;
1250 uint16_t PRLI_payload_length;
1251 uint8_t prli_svc_param_word_0[2]; /* Big endian */
1252 /* Bits 15-0 of word 0 */
1253 uint8_t prli_svc_param_word_3[2]; /* Big endian */
1254 /* Bits 15-0 of word 3 */
1255 uint16_t loop_id;
1256 uint16_t extended_lun_info_list_pointer;
1257 uint16_t extended_lun_stop_list_pointer;
1258 } port_database_t;
1259
1260 /*
1261 * Port database slave/master states
1262 */
1263 #define PD_STATE_DISCOVERY 0
1264 #define PD_STATE_WAIT_DISCOVERY_ACK 1
1265 #define PD_STATE_PORT_LOGIN 2
1266 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1267 #define PD_STATE_PROCESS_LOGIN 4
1268 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1269 #define PD_STATE_PORT_LOGGED_IN 6
1270 #define PD_STATE_PORT_UNAVAILABLE 7
1271 #define PD_STATE_PROCESS_LOGOUT 8
1272 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1273 #define PD_STATE_PORT_LOGOUT 10
1274 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1275
1276
1277 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1278 #define QLA_ZIO_DISABLED 0
1279 #define QLA_ZIO_DEFAULT_TIMER 2
1280
1281 /*
1282 * ISP Initialization Control Block.
1283 * Little endian except where noted.
1284 */
1285 #define ICB_VERSION 1
1286 typedef struct {
1287 uint8_t version;
1288 uint8_t reserved_1;
1289
1290 /*
1291 * LSB BIT 0 = Enable Hard Loop Id
1292 * LSB BIT 1 = Enable Fairness
1293 * LSB BIT 2 = Enable Full-Duplex
1294 * LSB BIT 3 = Enable Fast Posting
1295 * LSB BIT 4 = Enable Target Mode
1296 * LSB BIT 5 = Disable Initiator Mode
1297 * LSB BIT 6 = Enable ADISC
1298 * LSB BIT 7 = Enable Target Inquiry Data
1299 *
1300 * MSB BIT 0 = Enable PDBC Notify
1301 * MSB BIT 1 = Non Participating LIP
1302 * MSB BIT 2 = Descending Loop ID Search
1303 * MSB BIT 3 = Acquire Loop ID in LIPA
1304 * MSB BIT 4 = Stop PortQ on Full Status
1305 * MSB BIT 5 = Full Login after LIP
1306 * MSB BIT 6 = Node Name Option
1307 * MSB BIT 7 = Ext IFWCB enable bit
1308 */
1309 uint8_t firmware_options[2];
1310
1311 uint16_t frame_payload_size;
1312 uint16_t max_iocb_allocation;
1313 uint16_t execution_throttle;
1314 uint8_t retry_count;
1315 uint8_t retry_delay; /* unused */
1316 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1317 uint16_t hard_address;
1318 uint8_t inquiry_data;
1319 uint8_t login_timeout;
1320 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1321
1322 uint16_t request_q_outpointer;
1323 uint16_t response_q_inpointer;
1324 uint16_t request_q_length;
1325 uint16_t response_q_length;
1326 uint32_t request_q_address[2];
1327 uint32_t response_q_address[2];
1328
1329 uint16_t lun_enables;
1330 uint8_t command_resource_count;
1331 uint8_t immediate_notify_resource_count;
1332 uint16_t timeout;
1333 uint8_t reserved_2[2];
1334
1335 /*
1336 * LSB BIT 0 = Timer Operation mode bit 0
1337 * LSB BIT 1 = Timer Operation mode bit 1
1338 * LSB BIT 2 = Timer Operation mode bit 2
1339 * LSB BIT 3 = Timer Operation mode bit 3
1340 * LSB BIT 4 = Init Config Mode bit 0
1341 * LSB BIT 5 = Init Config Mode bit 1
1342 * LSB BIT 6 = Init Config Mode bit 2
1343 * LSB BIT 7 = Enable Non part on LIHA failure
1344 *
1345 * MSB BIT 0 = Enable class 2
1346 * MSB BIT 1 = Enable ACK0
1347 * MSB BIT 2 =
1348 * MSB BIT 3 =
1349 * MSB BIT 4 = FC Tape Enable
1350 * MSB BIT 5 = Enable FC Confirm
1351 * MSB BIT 6 = Enable command queuing in target mode
1352 * MSB BIT 7 = No Logo On Link Down
1353 */
1354 uint8_t add_firmware_options[2];
1355
1356 uint8_t response_accumulation_timer;
1357 uint8_t interrupt_delay_timer;
1358
1359 /*
1360 * LSB BIT 0 = Enable Read xfr_rdy
1361 * LSB BIT 1 = Soft ID only
1362 * LSB BIT 2 =
1363 * LSB BIT 3 =
1364 * LSB BIT 4 = FCP RSP Payload [0]
1365 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1366 * LSB BIT 6 = Enable Out-of-Order frame handling
1367 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1368 *
1369 * MSB BIT 0 = Sbus enable - 2300
1370 * MSB BIT 1 =
1371 * MSB BIT 2 =
1372 * MSB BIT 3 =
1373 * MSB BIT 4 = LED mode
1374 * MSB BIT 5 = enable 50 ohm termination
1375 * MSB BIT 6 = Data Rate (2300 only)
1376 * MSB BIT 7 = Data Rate (2300 only)
1377 */
1378 uint8_t special_options[2];
1379
1380 uint8_t reserved_3[26];
1381 } init_cb_t;
1382
1383 /*
1384 * Get Link Status mailbox command return buffer.
1385 */
1386 #define GLSO_SEND_RPS BIT_0
1387 #define GLSO_USE_DID BIT_3
1388
1389 struct link_statistics {
1390 uint32_t link_fail_cnt;
1391 uint32_t loss_sync_cnt;
1392 uint32_t loss_sig_cnt;
1393 uint32_t prim_seq_err_cnt;
1394 uint32_t inval_xmit_word_cnt;
1395 uint32_t inval_crc_cnt;
1396 uint32_t lip_cnt;
1397 uint32_t link_up_cnt;
1398 uint32_t link_down_loop_init_tmo;
1399 uint32_t link_down_los;
1400 uint32_t link_down_loss_rcv_clk;
1401 uint32_t reserved0[5];
1402 uint32_t port_cfg_chg;
1403 uint32_t reserved1[11];
1404 uint32_t rsp_q_full;
1405 uint32_t atio_q_full;
1406 uint32_t drop_ae;
1407 uint32_t els_proto_err;
1408 uint32_t reserved2;
1409 uint32_t tx_frames;
1410 uint32_t rx_frames;
1411 uint32_t discarded_frames;
1412 uint32_t dropped_frames;
1413 uint32_t reserved3;
1414 uint32_t nos_rcvd;
1415 uint32_t reserved4[4];
1416 uint32_t tx_prjt;
1417 uint32_t rcv_exfail;
1418 uint32_t rcv_abts;
1419 uint32_t seq_frm_miss;
1420 uint32_t corr_err;
1421 uint32_t mb_rqst;
1422 uint32_t nport_full;
1423 uint32_t eofa;
1424 uint32_t reserved5;
1425 uint32_t fpm_recv_word_cnt_lo;
1426 uint32_t fpm_recv_word_cnt_hi;
1427 uint32_t fpm_disc_word_cnt_lo;
1428 uint32_t fpm_disc_word_cnt_hi;
1429 uint32_t fpm_xmit_word_cnt_lo;
1430 uint32_t fpm_xmit_word_cnt_hi;
1431 uint32_t reserved6[70];
1432 };
1433
1434 /*
1435 * NVRAM Command values.
1436 */
1437 #define NV_START_BIT BIT_2
1438 #define NV_WRITE_OP (BIT_26+BIT_24)
1439 #define NV_READ_OP (BIT_26+BIT_25)
1440 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1441 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1442 #define NV_DELAY_COUNT 10
1443
1444 /*
1445 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
1446 */
1447 typedef struct {
1448 /*
1449 * NVRAM header
1450 */
1451 uint8_t id[4];
1452 uint8_t nvram_version;
1453 uint8_t reserved_0;
1454
1455 /*
1456 * NVRAM RISC parameter block
1457 */
1458 uint8_t parameter_block_version;
1459 uint8_t reserved_1;
1460
1461 /*
1462 * LSB BIT 0 = Enable Hard Loop Id
1463 * LSB BIT 1 = Enable Fairness
1464 * LSB BIT 2 = Enable Full-Duplex
1465 * LSB BIT 3 = Enable Fast Posting
1466 * LSB BIT 4 = Enable Target Mode
1467 * LSB BIT 5 = Disable Initiator Mode
1468 * LSB BIT 6 = Enable ADISC
1469 * LSB BIT 7 = Enable Target Inquiry Data
1470 *
1471 * MSB BIT 0 = Enable PDBC Notify
1472 * MSB BIT 1 = Non Participating LIP
1473 * MSB BIT 2 = Descending Loop ID Search
1474 * MSB BIT 3 = Acquire Loop ID in LIPA
1475 * MSB BIT 4 = Stop PortQ on Full Status
1476 * MSB BIT 5 = Full Login after LIP
1477 * MSB BIT 6 = Node Name Option
1478 * MSB BIT 7 = Ext IFWCB enable bit
1479 */
1480 uint8_t firmware_options[2];
1481
1482 uint16_t frame_payload_size;
1483 uint16_t max_iocb_allocation;
1484 uint16_t execution_throttle;
1485 uint8_t retry_count;
1486 uint8_t retry_delay; /* unused */
1487 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1488 uint16_t hard_address;
1489 uint8_t inquiry_data;
1490 uint8_t login_timeout;
1491 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1492
1493 /*
1494 * LSB BIT 0 = Timer Operation mode bit 0
1495 * LSB BIT 1 = Timer Operation mode bit 1
1496 * LSB BIT 2 = Timer Operation mode bit 2
1497 * LSB BIT 3 = Timer Operation mode bit 3
1498 * LSB BIT 4 = Init Config Mode bit 0
1499 * LSB BIT 5 = Init Config Mode bit 1
1500 * LSB BIT 6 = Init Config Mode bit 2
1501 * LSB BIT 7 = Enable Non part on LIHA failure
1502 *
1503 * MSB BIT 0 = Enable class 2
1504 * MSB BIT 1 = Enable ACK0
1505 * MSB BIT 2 =
1506 * MSB BIT 3 =
1507 * MSB BIT 4 = FC Tape Enable
1508 * MSB BIT 5 = Enable FC Confirm
1509 * MSB BIT 6 = Enable command queuing in target mode
1510 * MSB BIT 7 = No Logo On Link Down
1511 */
1512 uint8_t add_firmware_options[2];
1513
1514 uint8_t response_accumulation_timer;
1515 uint8_t interrupt_delay_timer;
1516
1517 /*
1518 * LSB BIT 0 = Enable Read xfr_rdy
1519 * LSB BIT 1 = Soft ID only
1520 * LSB BIT 2 =
1521 * LSB BIT 3 =
1522 * LSB BIT 4 = FCP RSP Payload [0]
1523 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1524 * LSB BIT 6 = Enable Out-of-Order frame handling
1525 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1526 *
1527 * MSB BIT 0 = Sbus enable - 2300
1528 * MSB BIT 1 =
1529 * MSB BIT 2 =
1530 * MSB BIT 3 =
1531 * MSB BIT 4 = LED mode
1532 * MSB BIT 5 = enable 50 ohm termination
1533 * MSB BIT 6 = Data Rate (2300 only)
1534 * MSB BIT 7 = Data Rate (2300 only)
1535 */
1536 uint8_t special_options[2];
1537
1538 /* Reserved for expanded RISC parameter block */
1539 uint8_t reserved_2[22];
1540
1541 /*
1542 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1543 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1544 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1545 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1546 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1547 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1548 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1549 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1550 *
1551 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1552 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1553 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1554 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1555 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1556 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1557 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1558 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1559 *
1560 * LSB BIT 0 = Output Swing 1G bit 0
1561 * LSB BIT 1 = Output Swing 1G bit 1
1562 * LSB BIT 2 = Output Swing 1G bit 2
1563 * LSB BIT 3 = Output Emphasis 1G bit 0
1564 * LSB BIT 4 = Output Emphasis 1G bit 1
1565 * LSB BIT 5 = Output Swing 2G bit 0
1566 * LSB BIT 6 = Output Swing 2G bit 1
1567 * LSB BIT 7 = Output Swing 2G bit 2
1568 *
1569 * MSB BIT 0 = Output Emphasis 2G bit 0
1570 * MSB BIT 1 = Output Emphasis 2G bit 1
1571 * MSB BIT 2 = Output Enable
1572 * MSB BIT 3 =
1573 * MSB BIT 4 =
1574 * MSB BIT 5 =
1575 * MSB BIT 6 =
1576 * MSB BIT 7 =
1577 */
1578 uint8_t seriallink_options[4];
1579
1580 /*
1581 * NVRAM host parameter block
1582 *
1583 * LSB BIT 0 = Enable spinup delay
1584 * LSB BIT 1 = Disable BIOS
1585 * LSB BIT 2 = Enable Memory Map BIOS
1586 * LSB BIT 3 = Enable Selectable Boot
1587 * LSB BIT 4 = Disable RISC code load
1588 * LSB BIT 5 = Set cache line size 1
1589 * LSB BIT 6 = PCI Parity Disable
1590 * LSB BIT 7 = Enable extended logging
1591 *
1592 * MSB BIT 0 = Enable 64bit addressing
1593 * MSB BIT 1 = Enable lip reset
1594 * MSB BIT 2 = Enable lip full login
1595 * MSB BIT 3 = Enable target reset
1596 * MSB BIT 4 = Enable database storage
1597 * MSB BIT 5 = Enable cache flush read
1598 * MSB BIT 6 = Enable database load
1599 * MSB BIT 7 = Enable alternate WWN
1600 */
1601 uint8_t host_p[2];
1602
1603 uint8_t boot_node_name[WWN_SIZE];
1604 uint8_t boot_lun_number;
1605 uint8_t reset_delay;
1606 uint8_t port_down_retry_count;
1607 uint8_t boot_id_number;
1608 uint16_t max_luns_per_target;
1609 uint8_t fcode_boot_port_name[WWN_SIZE];
1610 uint8_t alternate_port_name[WWN_SIZE];
1611 uint8_t alternate_node_name[WWN_SIZE];
1612
1613 /*
1614 * BIT 0 = Selective Login
1615 * BIT 1 = Alt-Boot Enable
1616 * BIT 2 =
1617 * BIT 3 = Boot Order List
1618 * BIT 4 =
1619 * BIT 5 = Selective LUN
1620 * BIT 6 =
1621 * BIT 7 = unused
1622 */
1623 uint8_t efi_parameters;
1624
1625 uint8_t link_down_timeout;
1626
1627 uint8_t adapter_id[16];
1628
1629 uint8_t alt1_boot_node_name[WWN_SIZE];
1630 uint16_t alt1_boot_lun_number;
1631 uint8_t alt2_boot_node_name[WWN_SIZE];
1632 uint16_t alt2_boot_lun_number;
1633 uint8_t alt3_boot_node_name[WWN_SIZE];
1634 uint16_t alt3_boot_lun_number;
1635 uint8_t alt4_boot_node_name[WWN_SIZE];
1636 uint16_t alt4_boot_lun_number;
1637 uint8_t alt5_boot_node_name[WWN_SIZE];
1638 uint16_t alt5_boot_lun_number;
1639 uint8_t alt6_boot_node_name[WWN_SIZE];
1640 uint16_t alt6_boot_lun_number;
1641 uint8_t alt7_boot_node_name[WWN_SIZE];
1642 uint16_t alt7_boot_lun_number;
1643
1644 uint8_t reserved_3[2];
1645
1646 /* Offset 200-215 : Model Number */
1647 uint8_t model_number[16];
1648
1649 /* OEM related items */
1650 uint8_t oem_specific[16];
1651
1652 /*
1653 * NVRAM Adapter Features offset 232-239
1654 *
1655 * LSB BIT 0 = External GBIC
1656 * LSB BIT 1 = Risc RAM parity
1657 * LSB BIT 2 = Buffer Plus Module
1658 * LSB BIT 3 = Multi Chip Adapter
1659 * LSB BIT 4 = Internal connector
1660 * LSB BIT 5 =
1661 * LSB BIT 6 =
1662 * LSB BIT 7 =
1663 *
1664 * MSB BIT 0 =
1665 * MSB BIT 1 =
1666 * MSB BIT 2 =
1667 * MSB BIT 3 =
1668 * MSB BIT 4 =
1669 * MSB BIT 5 =
1670 * MSB BIT 6 =
1671 * MSB BIT 7 =
1672 */
1673 uint8_t adapter_features[2];
1674
1675 uint8_t reserved_4[16];
1676
1677 /* Subsystem vendor ID for ISP2200 */
1678 uint16_t subsystem_vendor_id_2200;
1679
1680 /* Subsystem device ID for ISP2200 */
1681 uint16_t subsystem_device_id_2200;
1682
1683 uint8_t reserved_5;
1684 uint8_t checksum;
1685 } nvram_t;
1686
1687 /*
1688 * ISP queue - response queue entry definition.
1689 */
1690 typedef struct {
1691 uint8_t entry_type; /* Entry type. */
1692 uint8_t entry_count; /* Entry count. */
1693 uint8_t sys_define; /* System defined. */
1694 uint8_t entry_status; /* Entry Status. */
1695 uint32_t handle; /* System defined handle */
1696 uint8_t data[52];
1697 uint32_t signature;
1698 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1699 } response_t;
1700
1701 /*
1702 * ISP queue - ATIO queue entry definition.
1703 */
1704 struct atio {
1705 uint8_t entry_type; /* Entry type. */
1706 uint8_t entry_count; /* Entry count. */
1707 __le16 attr_n_length;
1708 uint8_t data[56];
1709 uint32_t signature;
1710 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
1711 };
1712
1713 typedef union {
1714 uint16_t extended;
1715 struct {
1716 uint8_t reserved;
1717 uint8_t standard;
1718 } id;
1719 } target_id_t;
1720
1721 #define SET_TARGET_ID(ha, to, from) \
1722 do { \
1723 if (HAS_EXTENDED_IDS(ha)) \
1724 to.extended = cpu_to_le16(from); \
1725 else \
1726 to.id.standard = (uint8_t)from; \
1727 } while (0)
1728
1729 /*
1730 * ISP queue - command entry structure definition.
1731 */
1732 #define COMMAND_TYPE 0x11 /* Command entry */
1733 typedef struct {
1734 uint8_t entry_type; /* Entry type. */
1735 uint8_t entry_count; /* Entry count. */
1736 uint8_t sys_define; /* System defined. */
1737 uint8_t entry_status; /* Entry Status. */
1738 uint32_t handle; /* System handle. */
1739 target_id_t target; /* SCSI ID */
1740 uint16_t lun; /* SCSI LUN */
1741 uint16_t control_flags; /* Control flags. */
1742 #define CF_WRITE BIT_6
1743 #define CF_READ BIT_5
1744 #define CF_SIMPLE_TAG BIT_3
1745 #define CF_ORDERED_TAG BIT_2
1746 #define CF_HEAD_TAG BIT_1
1747 uint16_t reserved_1;
1748 uint16_t timeout; /* Command timeout. */
1749 uint16_t dseg_count; /* Data segment count. */
1750 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1751 uint32_t byte_count; /* Total byte count. */
1752 uint32_t dseg_0_address; /* Data segment 0 address. */
1753 uint32_t dseg_0_length; /* Data segment 0 length. */
1754 uint32_t dseg_1_address; /* Data segment 1 address. */
1755 uint32_t dseg_1_length; /* Data segment 1 length. */
1756 uint32_t dseg_2_address; /* Data segment 2 address. */
1757 uint32_t dseg_2_length; /* Data segment 2 length. */
1758 } cmd_entry_t;
1759
1760 /*
1761 * ISP queue - 64-Bit addressing, command entry structure definition.
1762 */
1763 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1764 typedef struct {
1765 uint8_t entry_type; /* Entry type. */
1766 uint8_t entry_count; /* Entry count. */
1767 uint8_t sys_define; /* System defined. */
1768 uint8_t entry_status; /* Entry Status. */
1769 uint32_t handle; /* System handle. */
1770 target_id_t target; /* SCSI ID */
1771 uint16_t lun; /* SCSI LUN */
1772 uint16_t control_flags; /* Control flags. */
1773 uint16_t reserved_1;
1774 uint16_t timeout; /* Command timeout. */
1775 uint16_t dseg_count; /* Data segment count. */
1776 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1777 uint32_t byte_count; /* Total byte count. */
1778 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1779 uint32_t dseg_0_length; /* Data segment 0 length. */
1780 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1781 uint32_t dseg_1_length; /* Data segment 1 length. */
1782 } cmd_a64_entry_t, request_t;
1783
1784 /*
1785 * ISP queue - continuation entry structure definition.
1786 */
1787 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1788 typedef struct {
1789 uint8_t entry_type; /* Entry type. */
1790 uint8_t entry_count; /* Entry count. */
1791 uint8_t sys_define; /* System defined. */
1792 uint8_t entry_status; /* Entry Status. */
1793 uint32_t reserved;
1794 uint32_t dseg_0_address; /* Data segment 0 address. */
1795 uint32_t dseg_0_length; /* Data segment 0 length. */
1796 uint32_t dseg_1_address; /* Data segment 1 address. */
1797 uint32_t dseg_1_length; /* Data segment 1 length. */
1798 uint32_t dseg_2_address; /* Data segment 2 address. */
1799 uint32_t dseg_2_length; /* Data segment 2 length. */
1800 uint32_t dseg_3_address; /* Data segment 3 address. */
1801 uint32_t dseg_3_length; /* Data segment 3 length. */
1802 uint32_t dseg_4_address; /* Data segment 4 address. */
1803 uint32_t dseg_4_length; /* Data segment 4 length. */
1804 uint32_t dseg_5_address; /* Data segment 5 address. */
1805 uint32_t dseg_5_length; /* Data segment 5 length. */
1806 uint32_t dseg_6_address; /* Data segment 6 address. */
1807 uint32_t dseg_6_length; /* Data segment 6 length. */
1808 } cont_entry_t;
1809
1810 /*
1811 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1812 */
1813 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1814 typedef struct {
1815 uint8_t entry_type; /* Entry type. */
1816 uint8_t entry_count; /* Entry count. */
1817 uint8_t sys_define; /* System defined. */
1818 uint8_t entry_status; /* Entry Status. */
1819 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1820 uint32_t dseg_0_length; /* Data segment 0 length. */
1821 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1822 uint32_t dseg_1_length; /* Data segment 1 length. */
1823 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1824 uint32_t dseg_2_length; /* Data segment 2 length. */
1825 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1826 uint32_t dseg_3_length; /* Data segment 3 length. */
1827 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1828 uint32_t dseg_4_length; /* Data segment 4 length. */
1829 } cont_a64_entry_t;
1830
1831 #define PO_MODE_DIF_INSERT 0
1832 #define PO_MODE_DIF_REMOVE 1
1833 #define PO_MODE_DIF_PASS 2
1834 #define PO_MODE_DIF_REPLACE 3
1835 #define PO_MODE_DIF_TCP_CKSUM 6
1836 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
1837 #define PO_DISABLE_GUARD_CHECK BIT_4
1838 #define PO_DISABLE_INCR_REF_TAG BIT_5
1839 #define PO_DIS_HEADER_MODE BIT_7
1840 #define PO_ENABLE_DIF_BUNDLING BIT_8
1841 #define PO_DIS_FRAME_MODE BIT_9
1842 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */
1843 #define PO_DIS_VALD_APP_REF_ESC BIT_11
1844
1845 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */
1846 #define PO_DIS_REF_TAG_REPL BIT_13
1847 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */
1848 #define PO_DIS_REF_TAG_VALD BIT_15
1849
1850 /*
1851 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1852 */
1853 struct crc_context {
1854 uint32_t handle; /* System handle. */
1855 __le32 ref_tag;
1856 __le16 app_tag;
1857 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1858 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
1859 __le16 guard_seed; /* Initial Guard Seed */
1860 __le16 prot_opts; /* Requested Data Protection Mode */
1861 __le16 blk_size; /* Data size in bytes */
1862 uint16_t runt_blk_guard; /* Guard value for runt block (tape
1863 * only) */
1864 __le32 byte_count; /* Total byte count/ total data
1865 * transfer count */
1866 union {
1867 struct {
1868 uint32_t reserved_1;
1869 uint16_t reserved_2;
1870 uint16_t reserved_3;
1871 uint32_t reserved_4;
1872 uint32_t data_address[2];
1873 uint32_t data_length;
1874 uint32_t reserved_5[2];
1875 uint32_t reserved_6;
1876 } nobundling;
1877 struct {
1878 __le32 dif_byte_count; /* Total DIF byte
1879 * count */
1880 uint16_t reserved_1;
1881 __le16 dseg_count; /* Data segment count */
1882 uint32_t reserved_2;
1883 uint32_t data_address[2];
1884 uint32_t data_length;
1885 uint32_t dif_address[2];
1886 uint32_t dif_length; /* Data segment 0
1887 * length */
1888 } bundling;
1889 } u;
1890
1891 struct fcp_cmnd fcp_cmnd;
1892 dma_addr_t crc_ctx_dma;
1893 /* List of DMA context transfers */
1894 struct list_head dsd_list;
1895
1896 /* List of DIF Bundling context DMA address */
1897 struct list_head ldif_dsd_list;
1898 u8 no_ldif_dsd;
1899
1900 struct list_head ldif_dma_hndl_list;
1901 u32 dif_bundl_len;
1902 u8 no_dif_bundl;
1903 /* This structure should not exceed 512 bytes */
1904 };
1905
1906 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1907 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1908
1909 /*
1910 * ISP queue - status entry structure definition.
1911 */
1912 #define STATUS_TYPE 0x03 /* Status entry. */
1913 typedef struct {
1914 uint8_t entry_type; /* Entry type. */
1915 uint8_t entry_count; /* Entry count. */
1916 uint8_t sys_define; /* System defined. */
1917 uint8_t entry_status; /* Entry Status. */
1918 uint32_t handle; /* System handle. */
1919 uint16_t scsi_status; /* SCSI status. */
1920 uint16_t comp_status; /* Completion status. */
1921 uint16_t state_flags; /* State flags. */
1922 uint16_t status_flags; /* Status flags. */
1923 uint16_t rsp_info_len; /* Response Info Length. */
1924 uint16_t req_sense_length; /* Request sense data length. */
1925 uint32_t residual_length; /* Residual transfer length. */
1926 uint8_t rsp_info[8]; /* FCP response information. */
1927 uint8_t req_sense_data[32]; /* Request sense data. */
1928 } sts_entry_t;
1929
1930 /*
1931 * Status entry entry status
1932 */
1933 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1934 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1935 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1936 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1937 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1938 #define RF_BUSY BIT_1 /* Busy */
1939 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1940 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1941 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1942 RF_INV_E_TYPE)
1943
1944 /*
1945 * Status entry SCSI status bit definitions.
1946 */
1947 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1948 #define SS_RESIDUAL_UNDER BIT_11
1949 #define SS_RESIDUAL_OVER BIT_10
1950 #define SS_SENSE_LEN_VALID BIT_9
1951 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1952 #define SS_SCSI_STATUS_BYTE 0xff
1953
1954 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1955 #define SS_BUSY_CONDITION BIT_3
1956 #define SS_CONDITION_MET BIT_2
1957 #define SS_CHECK_CONDITION BIT_1
1958
1959 /*
1960 * Status entry completion status
1961 */
1962 #define CS_COMPLETE 0x0 /* No errors */
1963 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1964 #define CS_DMA 0x2 /* A DMA direction error. */
1965 #define CS_TRANSPORT 0x3 /* Transport error. */
1966 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1967 #define CS_ABORTED 0x5 /* System aborted command. */
1968 #define CS_TIMEOUT 0x6 /* Timeout error. */
1969 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1970 #define CS_DIF_ERROR 0xC /* DIF error detected */
1971
1972 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1973 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1974 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1975 /* (selection timeout) */
1976 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1977 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1978 #define CS_PORT_BUSY 0x2B /* Port Busy */
1979 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1980 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request
1981 failure */
1982 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1983 #define CS_UNKNOWN 0x81 /* Driver defined */
1984 #define CS_RETRY 0x82 /* Driver defined */
1985 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1986
1987 #define CS_BIDIR_RD_OVERRUN 0x700
1988 #define CS_BIDIR_RD_WR_OVERRUN 0x707
1989 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
1990 #define CS_BIDIR_RD_UNDERRUN 0x1500
1991 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
1992 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515
1993 #define CS_BIDIR_DMA 0x200
1994 /*
1995 * Status entry status flags
1996 */
1997 #define SF_ABTS_TERMINATED BIT_10
1998 #define SF_LOGOUT_SENT BIT_13
1999
2000 /*
2001 * ISP queue - status continuation entry structure definition.
2002 */
2003 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
2004 typedef struct {
2005 uint8_t entry_type; /* Entry type. */
2006 uint8_t entry_count; /* Entry count. */
2007 uint8_t sys_define; /* System defined. */
2008 uint8_t entry_status; /* Entry Status. */
2009 uint8_t data[60]; /* data */
2010 } sts_cont_entry_t;
2011
2012 /*
2013 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
2014 * structure definition.
2015 */
2016 #define STATUS_TYPE_21 0x21 /* Status entry. */
2017 typedef struct {
2018 uint8_t entry_type; /* Entry type. */
2019 uint8_t entry_count; /* Entry count. */
2020 uint8_t handle_count; /* Handle count. */
2021 uint8_t entry_status; /* Entry Status. */
2022 uint32_t handle[15]; /* System handles. */
2023 } sts21_entry_t;
2024
2025 /*
2026 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
2027 * structure definition.
2028 */
2029 #define STATUS_TYPE_22 0x22 /* Status entry. */
2030 typedef struct {
2031 uint8_t entry_type; /* Entry type. */
2032 uint8_t entry_count; /* Entry count. */
2033 uint8_t handle_count; /* Handle count. */
2034 uint8_t entry_status; /* Entry Status. */
2035 uint16_t handle[30]; /* System handles. */
2036 } sts22_entry_t;
2037
2038 /*
2039 * ISP queue - marker entry structure definition.
2040 */
2041 #define MARKER_TYPE 0x04 /* Marker entry. */
2042 typedef struct {
2043 uint8_t entry_type; /* Entry type. */
2044 uint8_t entry_count; /* Entry count. */
2045 uint8_t handle_count; /* Handle count. */
2046 uint8_t entry_status; /* Entry Status. */
2047 uint32_t sys_define_2; /* System defined. */
2048 target_id_t target; /* SCSI ID */
2049 uint8_t modifier; /* Modifier (7-0). */
2050 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
2051 #define MK_SYNC_ID 1 /* Synchronize ID */
2052 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
2053 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
2054 /* clear port changed, */
2055 /* use sequence number. */
2056 uint8_t reserved_1;
2057 uint16_t sequence_number; /* Sequence number of event */
2058 uint16_t lun; /* SCSI LUN */
2059 uint8_t reserved_2[48];
2060 } mrk_entry_t;
2061
2062 /*
2063 * ISP queue - Management Server entry structure definition.
2064 */
2065 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
2066 typedef struct {
2067 uint8_t entry_type; /* Entry type. */
2068 uint8_t entry_count; /* Entry count. */
2069 uint8_t handle_count; /* Handle count. */
2070 uint8_t entry_status; /* Entry Status. */
2071 uint32_t handle1; /* System handle. */
2072 target_id_t loop_id;
2073 uint16_t status;
2074 uint16_t control_flags; /* Control flags. */
2075 uint16_t reserved2;
2076 uint16_t timeout;
2077 uint16_t cmd_dsd_count;
2078 uint16_t total_dsd_count;
2079 uint8_t type;
2080 uint8_t r_ctl;
2081 uint16_t rx_id;
2082 uint16_t reserved3;
2083 uint32_t handle2;
2084 uint32_t rsp_bytecount;
2085 uint32_t req_bytecount;
2086 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
2087 uint32_t dseg_req_length; /* Data segment 0 length. */
2088 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
2089 uint32_t dseg_rsp_length; /* Data segment 1 length. */
2090 } ms_iocb_entry_t;
2091
2092
2093 /*
2094 * ISP queue - Mailbox Command entry structure definition.
2095 */
2096 #define MBX_IOCB_TYPE 0x39
2097 struct mbx_entry {
2098 uint8_t entry_type;
2099 uint8_t entry_count;
2100 uint8_t sys_define1;
2101 /* Use sys_define1 for source type */
2102 #define SOURCE_SCSI 0x00
2103 #define SOURCE_IP 0x01
2104 #define SOURCE_VI 0x02
2105 #define SOURCE_SCTP 0x03
2106 #define SOURCE_MP 0x04
2107 #define SOURCE_MPIOCTL 0x05
2108 #define SOURCE_ASYNC_IOCB 0x07
2109
2110 uint8_t entry_status;
2111
2112 uint32_t handle;
2113 target_id_t loop_id;
2114
2115 uint16_t status;
2116 uint16_t state_flags;
2117 uint16_t status_flags;
2118
2119 uint32_t sys_define2[2];
2120
2121 uint16_t mb0;
2122 uint16_t mb1;
2123 uint16_t mb2;
2124 uint16_t mb3;
2125 uint16_t mb6;
2126 uint16_t mb7;
2127 uint16_t mb9;
2128 uint16_t mb10;
2129 uint32_t reserved_2[2];
2130 uint8_t node_name[WWN_SIZE];
2131 uint8_t port_name[WWN_SIZE];
2132 };
2133
2134 #ifndef IMMED_NOTIFY_TYPE
2135 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */
2136 /*
2137 * ISP queue - immediate notify entry structure definition.
2138 * This is sent by the ISP to the Target driver.
2139 * This IOCB would have report of events sent by the
2140 * initiator, that needs to be handled by the target
2141 * driver immediately.
2142 */
2143 struct imm_ntfy_from_isp {
2144 uint8_t entry_type; /* Entry type. */
2145 uint8_t entry_count; /* Entry count. */
2146 uint8_t sys_define; /* System defined. */
2147 uint8_t entry_status; /* Entry Status. */
2148 union {
2149 struct {
2150 uint32_t sys_define_2; /* System defined. */
2151 target_id_t target;
2152 uint16_t lun;
2153 uint8_t target_id;
2154 uint8_t reserved_1;
2155 uint16_t status_modifier;
2156 uint16_t status;
2157 uint16_t task_flags;
2158 uint16_t seq_id;
2159 uint16_t srr_rx_id;
2160 uint32_t srr_rel_offs;
2161 uint16_t srr_ui;
2162 #define SRR_IU_DATA_IN 0x1
2163 #define SRR_IU_DATA_OUT 0x5
2164 #define SRR_IU_STATUS 0x7
2165 uint16_t srr_ox_id;
2166 uint8_t reserved_2[28];
2167 } isp2x;
2168 struct {
2169 uint32_t reserved;
2170 uint16_t nport_handle;
2171 uint16_t reserved_2;
2172 uint16_t flags;
2173 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2174 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
2175 uint16_t srr_rx_id;
2176 uint16_t status;
2177 uint8_t status_subcode;
2178 uint8_t fw_handle;
2179 uint32_t exchange_address;
2180 uint32_t srr_rel_offs;
2181 uint16_t srr_ui;
2182 uint16_t srr_ox_id;
2183 union {
2184 struct {
2185 uint8_t node_name[8];
2186 } plogi; /* PLOGI/ADISC/PDISC */
2187 struct {
2188 /* PRLI word 3 bit 0-15 */
2189 uint16_t wd3_lo;
2190 uint8_t resv0[6];
2191 } prli;
2192 struct {
2193 uint8_t port_id[3];
2194 uint8_t resv1;
2195 uint16_t nport_handle;
2196 uint16_t resv2;
2197 } req_els;
2198 } u;
2199 uint8_t port_name[8];
2200 uint8_t resv3[3];
2201 uint8_t vp_index;
2202 uint32_t reserved_5;
2203 uint8_t port_id[3];
2204 uint8_t reserved_6;
2205 } isp24;
2206 } u;
2207 uint16_t reserved_7;
2208 uint16_t ox_id;
2209 } __packed;
2210 #endif
2211
2212 /*
2213 * ISP request and response queue entry sizes
2214 */
2215 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
2216 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
2217
2218
2219
2220 /*
2221 * Switch info gathering structure.
2222 */
2223 typedef struct {
2224 port_id_t d_id;
2225 uint8_t node_name[WWN_SIZE];
2226 uint8_t port_name[WWN_SIZE];
2227 uint8_t fabric_port_name[WWN_SIZE];
2228 uint16_t fp_speed;
2229 uint8_t fc4_type;
2230 uint8_t fc4f_nvme; /* nvme fc4 feature bits */
2231 } sw_info_t;
2232
2233 /* FCP-4 types */
2234 #define FC4_TYPE_FCP_SCSI 0x08
2235 #define FC4_TYPE_NVME 0x28
2236 #define FC4_TYPE_OTHER 0x0
2237 #define FC4_TYPE_UNKNOWN 0xff
2238
2239 /* mailbox command 4G & above */
2240 struct mbx_24xx_entry {
2241 uint8_t entry_type;
2242 uint8_t entry_count;
2243 uint8_t sys_define1;
2244 uint8_t entry_status;
2245 uint32_t handle;
2246 uint16_t mb[28];
2247 };
2248
2249 #define IOCB_SIZE 64
2250
2251 /*
2252 * Fibre channel port type.
2253 */
2254 typedef enum {
2255 FCT_UNKNOWN,
2256 FCT_RSCN,
2257 FCT_SWITCH,
2258 FCT_BROADCAST,
2259 FCT_INITIATOR,
2260 FCT_TARGET,
2261 FCT_NVME
2262 } fc_port_type_t;
2263
2264 enum qla_sess_deletion {
2265 QLA_SESS_DELETION_NONE = 0,
2266 QLA_SESS_DELETION_IN_PROGRESS,
2267 QLA_SESS_DELETED,
2268 };
2269
2270 enum qlt_plogi_link_t {
2271 QLT_PLOGI_LINK_SAME_WWN,
2272 QLT_PLOGI_LINK_CONFLICT,
2273 QLT_PLOGI_LINK_MAX
2274 };
2275
2276 struct qlt_plogi_ack_t {
2277 struct list_head list;
2278 struct imm_ntfy_from_isp iocb;
2279 port_id_t id;
2280 int ref_count;
2281 void *fcport;
2282 };
2283
2284 struct ct_sns_desc {
2285 struct ct_sns_pkt *ct_sns;
2286 dma_addr_t ct_sns_dma;
2287 };
2288
2289 enum discovery_state {
2290 DSC_DELETED,
2291 DSC_GNN_ID,
2292 DSC_GNL,
2293 DSC_LOGIN_PEND,
2294 DSC_LOGIN_FAILED,
2295 DSC_GPDB,
2296 DSC_UPD_FCPORT,
2297 DSC_LOGIN_COMPLETE,
2298 DSC_ADISC,
2299 DSC_DELETE_PEND,
2300 };
2301
2302 enum login_state { /* FW control Target side */
2303 DSC_LS_LLIOCB_SENT = 2,
2304 DSC_LS_PLOGI_PEND,
2305 DSC_LS_PLOGI_COMP,
2306 DSC_LS_PRLI_PEND,
2307 DSC_LS_PRLI_COMP,
2308 DSC_LS_PORT_UNAVAIL,
2309 DSC_LS_PRLO_PEND = 9,
2310 DSC_LS_LOGO_PEND,
2311 };
2312
2313 enum fcport_mgt_event {
2314 FCME_RELOGIN = 1,
2315 FCME_RSCN,
2316 FCME_PLOGI_DONE, /* Initiator side sent LLIOCB */
2317 FCME_PRLI_DONE,
2318 FCME_GNL_DONE,
2319 FCME_GPSC_DONE,
2320 FCME_GPDB_DONE,
2321 FCME_GPNID_DONE,
2322 FCME_GFFID_DONE,
2323 FCME_ADISC_DONE,
2324 FCME_GNNID_DONE,
2325 FCME_GFPNID_DONE,
2326 FCME_ELS_PLOGI_DONE,
2327 };
2328
2329 enum rscn_addr_format {
2330 RSCN_PORT_ADDR,
2331 RSCN_AREA_ADDR,
2332 RSCN_DOM_ADDR,
2333 RSCN_FAB_ADDR,
2334 };
2335
2336 /*
2337 * Fibre channel port structure.
2338 */
2339 typedef struct fc_port {
2340 struct list_head list;
2341 struct scsi_qla_host *vha;
2342
2343 uint8_t node_name[WWN_SIZE];
2344 uint8_t port_name[WWN_SIZE];
2345 port_id_t d_id;
2346 uint16_t loop_id;
2347 uint16_t old_loop_id;
2348
2349 unsigned int conf_compl_supported:1;
2350 unsigned int deleted:2;
2351 unsigned int free_pending:1;
2352 unsigned int local:1;
2353 unsigned int logout_on_delete:1;
2354 unsigned int logo_ack_needed:1;
2355 unsigned int keep_nport_handle:1;
2356 unsigned int send_els_logo:1;
2357 unsigned int login_pause:1;
2358 unsigned int login_succ:1;
2359 unsigned int query:1;
2360 unsigned int id_changed:1;
2361 unsigned int scan_needed:1;
2362
2363 struct work_struct nvme_del_work;
2364 struct completion nvme_del_done;
2365 uint32_t nvme_prli_service_param;
2366 #define NVME_PRLI_SP_CONF BIT_7
2367 #define NVME_PRLI_SP_INITIATOR BIT_5
2368 #define NVME_PRLI_SP_TARGET BIT_4
2369 #define NVME_PRLI_SP_DISCOVERY BIT_3
2370 #define NVME_PRLI_SP_FIRST_BURST BIT_0
2371 uint8_t nvme_flag;
2372 uint32_t nvme_first_burst_size;
2373 #define NVME_FLAG_REGISTERED 4
2374 #define NVME_FLAG_DELETING 2
2375 #define NVME_FLAG_RESETTING 1
2376
2377 struct fc_port *conflict;
2378 unsigned char logout_completed;
2379 int generation;
2380
2381 struct se_session *se_sess;
2382 struct kref sess_kref;
2383 struct qla_tgt *tgt;
2384 unsigned long expires;
2385 struct list_head del_list_entry;
2386 struct work_struct free_work;
2387 struct work_struct reg_work;
2388 uint64_t jiffies_at_registration;
2389 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2390
2391 uint16_t tgt_id;
2392 uint16_t old_tgt_id;
2393 uint16_t sec_since_registration;
2394
2395 uint8_t fcp_prio;
2396
2397 uint8_t fabric_port_name[WWN_SIZE];
2398 uint16_t fp_speed;
2399
2400 fc_port_type_t port_type;
2401
2402 atomic_t state;
2403 uint32_t flags;
2404
2405 int login_retry;
2406
2407 struct fc_rport *rport, *drport;
2408 u32 supported_classes;
2409
2410 uint8_t fc4_type;
2411 uint8_t fc4f_nvme;
2412 uint8_t scan_state;
2413 uint8_t n2n_flag;
2414
2415 unsigned long last_queue_full;
2416 unsigned long last_ramp_up;
2417
2418 uint16_t port_id;
2419
2420 struct nvme_fc_remote_port *nvme_remote_port;
2421
2422 unsigned long retry_delay_timestamp;
2423 struct qla_tgt_sess *tgt_session;
2424 struct ct_sns_desc ct_desc;
2425 enum discovery_state disc_state;
2426 enum discovery_state next_disc_state;
2427 enum login_state fw_login_state;
2428 unsigned long dm_login_expire;
2429 unsigned long plogi_nack_done_deadline;
2430
2431 u32 login_gen, last_login_gen;
2432 u32 rscn_gen, last_rscn_gen;
2433 u32 chip_reset;
2434 struct list_head gnl_entry;
2435 struct work_struct del_work;
2436 u8 iocb[IOCB_SIZE];
2437 u8 current_login_state;
2438 u8 last_login_state;
2439 u16 n2n_link_reset_cnt;
2440 u16 n2n_chip_reset;
2441 } fc_port_t;
2442
2443 #define QLA_FCPORT_SCAN 1
2444 #define QLA_FCPORT_FOUND 2
2445
2446 struct event_arg {
2447 enum fcport_mgt_event event;
2448 fc_port_t *fcport;
2449 srb_t *sp;
2450 port_id_t id;
2451 u16 data[2], rc;
2452 u8 port_name[WWN_SIZE];
2453 u32 iop[2];
2454 };
2455
2456 #include "qla_mr.h"
2457
2458 /*
2459 * Fibre channel port/lun states.
2460 */
2461 #define FCS_UNCONFIGURED 1
2462 #define FCS_DEVICE_DEAD 2
2463 #define FCS_DEVICE_LOST 3
2464 #define FCS_ONLINE 4
2465
2466 static const char * const port_state_str[] = {
2467 "Unknown",
2468 "UNCONFIGURED",
2469 "DEAD",
2470 "LOST",
2471 "ONLINE"
2472 };
2473
2474 /*
2475 * FC port flags.
2476 */
2477 #define FCF_FABRIC_DEVICE BIT_0
2478 #define FCF_LOGIN_NEEDED BIT_1
2479 #define FCF_FCP2_DEVICE BIT_2
2480 #define FCF_ASYNC_SENT BIT_3
2481 #define FCF_CONF_COMP_SUPPORTED BIT_4
2482 #define FCF_ASYNC_ACTIVE BIT_5
2483
2484 /* No loop ID flag. */
2485 #define FC_NO_LOOP_ID 0x1000
2486
2487 /*
2488 * FC-CT interface
2489 *
2490 * NOTE: All structures are big-endian in form.
2491 */
2492
2493 #define CT_REJECT_RESPONSE 0x8001
2494 #define CT_ACCEPT_RESPONSE 0x8002
2495 #define CT_REASON_INVALID_COMMAND_CODE 0x01
2496 #define CT_REASON_CANNOT_PERFORM 0x09
2497 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2498 #define CT_EXPL_ALREADY_REGISTERED 0x10
2499 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2500 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2501 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2502 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2503 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2504 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2505 #define CT_EXPL_HBA_NOT_REGISTERED 0x17
2506 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2507 #define CT_EXPL_PORT_NOT_REGISTERED 0x21
2508 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2509 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2510
2511 #define NS_N_PORT_TYPE 0x01
2512 #define NS_NL_PORT_TYPE 0x02
2513 #define NS_NX_PORT_TYPE 0x7F
2514
2515 #define GA_NXT_CMD 0x100
2516 #define GA_NXT_REQ_SIZE (16 + 4)
2517 #define GA_NXT_RSP_SIZE (16 + 620)
2518
2519 #define GPN_FT_CMD 0x172
2520 #define GPN_FT_REQ_SIZE (16 + 4)
2521 #define GNN_FT_CMD 0x173
2522 #define GNN_FT_REQ_SIZE (16 + 4)
2523
2524 #define GID_PT_CMD 0x1A1
2525 #define GID_PT_REQ_SIZE (16 + 4)
2526
2527 #define GPN_ID_CMD 0x112
2528 #define GPN_ID_REQ_SIZE (16 + 4)
2529 #define GPN_ID_RSP_SIZE (16 + 8)
2530
2531 #define GNN_ID_CMD 0x113
2532 #define GNN_ID_REQ_SIZE (16 + 4)
2533 #define GNN_ID_RSP_SIZE (16 + 8)
2534
2535 #define GFT_ID_CMD 0x117
2536 #define GFT_ID_REQ_SIZE (16 + 4)
2537 #define GFT_ID_RSP_SIZE (16 + 32)
2538
2539 #define GID_PN_CMD 0x121
2540 #define GID_PN_REQ_SIZE (16 + 8)
2541 #define GID_PN_RSP_SIZE (16 + 4)
2542
2543 #define RFT_ID_CMD 0x217
2544 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
2545 #define RFT_ID_RSP_SIZE 16
2546
2547 #define RFF_ID_CMD 0x21F
2548 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2549 #define RFF_ID_RSP_SIZE 16
2550
2551 #define RNN_ID_CMD 0x213
2552 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
2553 #define RNN_ID_RSP_SIZE 16
2554
2555 #define RSNN_NN_CMD 0x239
2556 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2557 #define RSNN_NN_RSP_SIZE 16
2558
2559 #define GFPN_ID_CMD 0x11C
2560 #define GFPN_ID_REQ_SIZE (16 + 4)
2561 #define GFPN_ID_RSP_SIZE (16 + 8)
2562
2563 #define GPSC_CMD 0x127
2564 #define GPSC_REQ_SIZE (16 + 8)
2565 #define GPSC_RSP_SIZE (16 + 2 + 2)
2566
2567 #define GFF_ID_CMD 0x011F
2568 #define GFF_ID_REQ_SIZE (16 + 4)
2569 #define GFF_ID_RSP_SIZE (16 + 128)
2570
2571 /*
2572 * HBA attribute types.
2573 */
2574 #define FDMI_HBA_ATTR_COUNT 9
2575 #define FDMIV2_HBA_ATTR_COUNT 17
2576 #define FDMI_HBA_NODE_NAME 0x1
2577 #define FDMI_HBA_MANUFACTURER 0x2
2578 #define FDMI_HBA_SERIAL_NUMBER 0x3
2579 #define FDMI_HBA_MODEL 0x4
2580 #define FDMI_HBA_MODEL_DESCRIPTION 0x5
2581 #define FDMI_HBA_HARDWARE_VERSION 0x6
2582 #define FDMI_HBA_DRIVER_VERSION 0x7
2583 #define FDMI_HBA_OPTION_ROM_VERSION 0x8
2584 #define FDMI_HBA_FIRMWARE_VERSION 0x9
2585 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2586 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2587 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2588 #define FDMI_HBA_VENDOR_ID 0xd
2589 #define FDMI_HBA_NUM_PORTS 0xe
2590 #define FDMI_HBA_FABRIC_NAME 0xf
2591 #define FDMI_HBA_BOOT_BIOS_NAME 0x10
2592 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0
2593
2594 struct ct_fdmi_hba_attr {
2595 uint16_t type;
2596 uint16_t len;
2597 union {
2598 uint8_t node_name[WWN_SIZE];
2599 uint8_t manufacturer[64];
2600 uint8_t serial_num[32];
2601 uint8_t model[16+1];
2602 uint8_t model_desc[80];
2603 uint8_t hw_version[32];
2604 uint8_t driver_version[32];
2605 uint8_t orom_version[16];
2606 uint8_t fw_version[32];
2607 uint8_t os_version[128];
2608 uint32_t max_ct_len;
2609 } a;
2610 };
2611
2612 struct ct_fdmi_hba_attributes {
2613 uint32_t count;
2614 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
2615 };
2616
2617 struct ct_fdmiv2_hba_attr {
2618 uint16_t type;
2619 uint16_t len;
2620 union {
2621 uint8_t node_name[WWN_SIZE];
2622 uint8_t manufacturer[64];
2623 uint8_t serial_num[32];
2624 uint8_t model[16+1];
2625 uint8_t model_desc[80];
2626 uint8_t hw_version[16];
2627 uint8_t driver_version[32];
2628 uint8_t orom_version[16];
2629 uint8_t fw_version[32];
2630 uint8_t os_version[128];
2631 uint32_t max_ct_len;
2632 uint8_t sym_name[256];
2633 uint32_t vendor_id;
2634 uint32_t num_ports;
2635 uint8_t fabric_name[WWN_SIZE];
2636 uint8_t bios_name[32];
2637 uint8_t vendor_identifier[8];
2638 } a;
2639 };
2640
2641 struct ct_fdmiv2_hba_attributes {
2642 uint32_t count;
2643 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT];
2644 };
2645
2646 /*
2647 * Port attribute types.
2648 */
2649 #define FDMI_PORT_ATTR_COUNT 6
2650 #define FDMIV2_PORT_ATTR_COUNT 16
2651 #define FDMI_PORT_FC4_TYPES 0x1
2652 #define FDMI_PORT_SUPPORT_SPEED 0x2
2653 #define FDMI_PORT_CURRENT_SPEED 0x3
2654 #define FDMI_PORT_MAX_FRAME_SIZE 0x4
2655 #define FDMI_PORT_OS_DEVICE_NAME 0x5
2656 #define FDMI_PORT_HOST_NAME 0x6
2657 #define FDMI_PORT_NODE_NAME 0x7
2658 #define FDMI_PORT_NAME 0x8
2659 #define FDMI_PORT_SYM_NAME 0x9
2660 #define FDMI_PORT_TYPE 0xa
2661 #define FDMI_PORT_SUPP_COS 0xb
2662 #define FDMI_PORT_FABRIC_NAME 0xc
2663 #define FDMI_PORT_FC4_TYPE 0xd
2664 #define FDMI_PORT_STATE 0x101
2665 #define FDMI_PORT_COUNT 0x102
2666 #define FDMI_PORT_ID 0x103
2667
2668 #define FDMI_PORT_SPEED_1GB 0x1
2669 #define FDMI_PORT_SPEED_2GB 0x2
2670 #define FDMI_PORT_SPEED_10GB 0x4
2671 #define FDMI_PORT_SPEED_4GB 0x8
2672 #define FDMI_PORT_SPEED_8GB 0x10
2673 #define FDMI_PORT_SPEED_16GB 0x20
2674 #define FDMI_PORT_SPEED_32GB 0x40
2675 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
2676
2677 #define FC_CLASS_2 0x04
2678 #define FC_CLASS_3 0x08
2679 #define FC_CLASS_2_3 0x0C
2680
2681 struct ct_fdmiv2_port_attr {
2682 uint16_t type;
2683 uint16_t len;
2684 union {
2685 uint8_t fc4_types[32];
2686 uint32_t sup_speed;
2687 uint32_t cur_speed;
2688 uint32_t max_frame_size;
2689 uint8_t os_dev_name[32];
2690 uint8_t host_name[256];
2691 uint8_t node_name[WWN_SIZE];
2692 uint8_t port_name[WWN_SIZE];
2693 uint8_t port_sym_name[128];
2694 uint32_t port_type;
2695 uint32_t port_supported_cos;
2696 uint8_t fabric_name[WWN_SIZE];
2697 uint8_t port_fc4_type[32];
2698 uint32_t port_state;
2699 uint32_t num_ports;
2700 uint32_t port_id;
2701 } a;
2702 };
2703
2704 /*
2705 * Port Attribute Block.
2706 */
2707 struct ct_fdmiv2_port_attributes {
2708 uint32_t count;
2709 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT];
2710 };
2711
2712 struct ct_fdmi_port_attr {
2713 uint16_t type;
2714 uint16_t len;
2715 union {
2716 uint8_t fc4_types[32];
2717 uint32_t sup_speed;
2718 uint32_t cur_speed;
2719 uint32_t max_frame_size;
2720 uint8_t os_dev_name[32];
2721 uint8_t host_name[256];
2722 } a;
2723 };
2724
2725 struct ct_fdmi_port_attributes {
2726 uint32_t count;
2727 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
2728 };
2729
2730 /* FDMI definitions. */
2731 #define GRHL_CMD 0x100
2732 #define GHAT_CMD 0x101
2733 #define GRPL_CMD 0x102
2734 #define GPAT_CMD 0x110
2735
2736 #define RHBA_CMD 0x200
2737 #define RHBA_RSP_SIZE 16
2738
2739 #define RHAT_CMD 0x201
2740 #define RPRT_CMD 0x210
2741
2742 #define RPA_CMD 0x211
2743 #define RPA_RSP_SIZE 16
2744
2745 #define DHBA_CMD 0x300
2746 #define DHBA_REQ_SIZE (16 + 8)
2747 #define DHBA_RSP_SIZE 16
2748
2749 #define DHAT_CMD 0x301
2750 #define DPRT_CMD 0x310
2751 #define DPA_CMD 0x311
2752
2753 /* CT command header -- request/response common fields */
2754 struct ct_cmd_hdr {
2755 uint8_t revision;
2756 uint8_t in_id[3];
2757 uint8_t gs_type;
2758 uint8_t gs_subtype;
2759 uint8_t options;
2760 uint8_t reserved;
2761 };
2762
2763 /* CT command request */
2764 struct ct_sns_req {
2765 struct ct_cmd_hdr header;
2766 uint16_t command;
2767 uint16_t max_rsp_size;
2768 uint8_t fragment_id;
2769 uint8_t reserved[3];
2770
2771 union {
2772 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
2773 struct {
2774 uint8_t reserved;
2775 uint8_t port_id[3];
2776 } port_id;
2777
2778 struct {
2779 uint8_t reserved;
2780 uint8_t domain;
2781 uint8_t area;
2782 uint8_t port_type;
2783 } gpn_ft;
2784
2785 struct {
2786 uint8_t port_type;
2787 uint8_t domain;
2788 uint8_t area;
2789 uint8_t reserved;
2790 } gid_pt;
2791
2792 struct {
2793 uint8_t reserved;
2794 uint8_t port_id[3];
2795 uint8_t fc4_types[32];
2796 } rft_id;
2797
2798 struct {
2799 uint8_t reserved;
2800 uint8_t port_id[3];
2801 uint16_t reserved2;
2802 uint8_t fc4_feature;
2803 uint8_t fc4_type;
2804 } rff_id;
2805
2806 struct {
2807 uint8_t reserved;
2808 uint8_t port_id[3];
2809 uint8_t node_name[8];
2810 } rnn_id;
2811
2812 struct {
2813 uint8_t node_name[8];
2814 uint8_t name_len;
2815 uint8_t sym_node_name[255];
2816 } rsnn_nn;
2817
2818 struct {
2819 uint8_t hba_identifier[8];
2820 } ghat;
2821
2822 struct {
2823 uint8_t hba_identifier[8];
2824 uint32_t entry_count;
2825 uint8_t port_name[8];
2826 struct ct_fdmi_hba_attributes attrs;
2827 } rhba;
2828
2829 struct {
2830 uint8_t hba_identifier[8];
2831 uint32_t entry_count;
2832 uint8_t port_name[8];
2833 struct ct_fdmiv2_hba_attributes attrs;
2834 } rhba2;
2835
2836 struct {
2837 uint8_t hba_identifier[8];
2838 struct ct_fdmi_hba_attributes attrs;
2839 } rhat;
2840
2841 struct {
2842 uint8_t port_name[8];
2843 struct ct_fdmi_port_attributes attrs;
2844 } rpa;
2845
2846 struct {
2847 uint8_t port_name[8];
2848 struct ct_fdmiv2_port_attributes attrs;
2849 } rpa2;
2850
2851 struct {
2852 uint8_t port_name[8];
2853 } dhba;
2854
2855 struct {
2856 uint8_t port_name[8];
2857 } dhat;
2858
2859 struct {
2860 uint8_t port_name[8];
2861 } dprt;
2862
2863 struct {
2864 uint8_t port_name[8];
2865 } dpa;
2866
2867 struct {
2868 uint8_t port_name[8];
2869 } gpsc;
2870
2871 struct {
2872 uint8_t reserved;
2873 uint8_t port_id[3];
2874 } gff_id;
2875
2876 struct {
2877 uint8_t port_name[8];
2878 } gid_pn;
2879 } req;
2880 };
2881
2882 /* CT command response header */
2883 struct ct_rsp_hdr {
2884 struct ct_cmd_hdr header;
2885 uint16_t response;
2886 uint16_t residual;
2887 uint8_t fragment_id;
2888 uint8_t reason_code;
2889 uint8_t explanation_code;
2890 uint8_t vendor_unique;
2891 };
2892
2893 struct ct_sns_gid_pt_data {
2894 uint8_t control_byte;
2895 uint8_t port_id[3];
2896 };
2897
2898 /* It's the same for both GPN_FT and GNN_FT */
2899 struct ct_sns_gpnft_rsp {
2900 struct {
2901 struct ct_cmd_hdr header;
2902 uint16_t response;
2903 uint16_t residual;
2904 uint8_t fragment_id;
2905 uint8_t reason_code;
2906 uint8_t explanation_code;
2907 uint8_t vendor_unique;
2908 };
2909 /* Assume the largest number of targets for the union */
2910 struct ct_sns_gpn_ft_data {
2911 u8 control_byte;
2912 u8 port_id[3];
2913 u32 reserved;
2914 u8 port_name[8];
2915 } entries[1];
2916 };
2917
2918 /* CT command response */
2919 struct ct_sns_rsp {
2920 struct ct_rsp_hdr header;
2921
2922 union {
2923 struct {
2924 uint8_t port_type;
2925 uint8_t port_id[3];
2926 uint8_t port_name[8];
2927 uint8_t sym_port_name_len;
2928 uint8_t sym_port_name[255];
2929 uint8_t node_name[8];
2930 uint8_t sym_node_name_len;
2931 uint8_t sym_node_name[255];
2932 uint8_t init_proc_assoc[8];
2933 uint8_t node_ip_addr[16];
2934 uint8_t class_of_service[4];
2935 uint8_t fc4_types[32];
2936 uint8_t ip_address[16];
2937 uint8_t fabric_port_name[8];
2938 uint8_t reserved;
2939 uint8_t hard_address[3];
2940 } ga_nxt;
2941
2942 struct {
2943 /* Assume the largest number of targets for the union */
2944 struct ct_sns_gid_pt_data
2945 entries[MAX_FIBRE_DEVICES_MAX];
2946 } gid_pt;
2947
2948 struct {
2949 uint8_t port_name[8];
2950 } gpn_id;
2951
2952 struct {
2953 uint8_t node_name[8];
2954 } gnn_id;
2955
2956 struct {
2957 uint8_t fc4_types[32];
2958 } gft_id;
2959
2960 struct {
2961 uint32_t entry_count;
2962 uint8_t port_name[8];
2963 struct ct_fdmi_hba_attributes attrs;
2964 } ghat;
2965
2966 struct {
2967 uint8_t port_name[8];
2968 } gfpn_id;
2969
2970 struct {
2971 uint16_t speeds;
2972 uint16_t speed;
2973 } gpsc;
2974
2975 #define GFF_FCP_SCSI_OFFSET 7
2976 #define GFF_NVME_OFFSET 23 /* type = 28h */
2977 struct {
2978 uint8_t fc4_features[128];
2979 } gff_id;
2980 struct {
2981 uint8_t reserved;
2982 uint8_t port_id[3];
2983 } gid_pn;
2984 } rsp;
2985 };
2986
2987 struct ct_sns_pkt {
2988 union {
2989 struct ct_sns_req req;
2990 struct ct_sns_rsp rsp;
2991 } p;
2992 };
2993
2994 struct ct_sns_gpnft_pkt {
2995 union {
2996 struct ct_sns_req req;
2997 struct ct_sns_gpnft_rsp rsp;
2998 } p;
2999 };
3000
3001 enum scan_flags_t {
3002 SF_SCANNING = BIT_0,
3003 SF_QUEUED = BIT_1,
3004 };
3005
3006 enum fc4type_t {
3007 FS_FC4TYPE_FCP = BIT_0,
3008 FS_FC4TYPE_NVME = BIT_1,
3009 };
3010
3011 struct fab_scan_rp {
3012 port_id_t id;
3013 enum fc4type_t fc4type;
3014 u8 port_name[8];
3015 u8 node_name[8];
3016 };
3017
3018 struct fab_scan {
3019 struct fab_scan_rp *l;
3020 u32 size;
3021 u16 scan_retry;
3022 #define MAX_SCAN_RETRIES 5
3023 enum scan_flags_t scan_flags;
3024 struct delayed_work scan_work;
3025 };
3026
3027 /*
3028 * SNS command structures -- for 2200 compatibility.
3029 */
3030 #define RFT_ID_SNS_SCMD_LEN 22
3031 #define RFT_ID_SNS_CMD_SIZE 60
3032 #define RFT_ID_SNS_DATA_SIZE 16
3033
3034 #define RNN_ID_SNS_SCMD_LEN 10
3035 #define RNN_ID_SNS_CMD_SIZE 36
3036 #define RNN_ID_SNS_DATA_SIZE 16
3037
3038 #define GA_NXT_SNS_SCMD_LEN 6
3039 #define GA_NXT_SNS_CMD_SIZE 28
3040 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
3041
3042 #define GID_PT_SNS_SCMD_LEN 6
3043 #define GID_PT_SNS_CMD_SIZE 28
3044 /*
3045 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
3046 * adapters.
3047 */
3048 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
3049
3050 #define GPN_ID_SNS_SCMD_LEN 6
3051 #define GPN_ID_SNS_CMD_SIZE 28
3052 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
3053
3054 #define GNN_ID_SNS_SCMD_LEN 6
3055 #define GNN_ID_SNS_CMD_SIZE 28
3056 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
3057
3058 struct sns_cmd_pkt {
3059 union {
3060 struct {
3061 uint16_t buffer_length;
3062 uint16_t reserved_1;
3063 uint32_t buffer_address[2];
3064 uint16_t subcommand_length;
3065 uint16_t reserved_2;
3066 uint16_t subcommand;
3067 uint16_t size;
3068 uint32_t reserved_3;
3069 uint8_t param[36];
3070 } cmd;
3071
3072 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
3073 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
3074 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
3075 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
3076 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
3077 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
3078 } p;
3079 };
3080
3081 struct fw_blob {
3082 char *name;
3083 uint32_t segs[4];
3084 const struct firmware *fw;
3085 };
3086
3087 /* Return data from MBC_GET_ID_LIST call. */
3088 struct gid_list_info {
3089 uint8_t al_pa;
3090 uint8_t area;
3091 uint8_t domain;
3092 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
3093 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
3094 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
3095 };
3096
3097 /* NPIV */
3098 typedef struct vport_info {
3099 uint8_t port_name[WWN_SIZE];
3100 uint8_t node_name[WWN_SIZE];
3101 int vp_id;
3102 uint16_t loop_id;
3103 unsigned long host_no;
3104 uint8_t port_id[3];
3105 int loop_state;
3106 } vport_info_t;
3107
3108 typedef struct vport_params {
3109 uint8_t port_name[WWN_SIZE];
3110 uint8_t node_name[WWN_SIZE];
3111 uint32_t options;
3112 #define VP_OPTS_RETRY_ENABLE BIT_0
3113 #define VP_OPTS_VP_DISABLE BIT_1
3114 } vport_params_t;
3115
3116 /* NPIV - return codes of VP create and modify */
3117 #define VP_RET_CODE_OK 0
3118 #define VP_RET_CODE_FATAL 1
3119 #define VP_RET_CODE_WRONG_ID 2
3120 #define VP_RET_CODE_WWPN 3
3121 #define VP_RET_CODE_RESOURCES 4
3122 #define VP_RET_CODE_NO_MEM 5
3123 #define VP_RET_CODE_NOT_FOUND 6
3124
3125 struct qla_hw_data;
3126 struct rsp_que;
3127 /*
3128 * ISP operations
3129 */
3130 struct isp_operations {
3131
3132 int (*pci_config) (struct scsi_qla_host *);
3133 void (*reset_chip) (struct scsi_qla_host *);
3134 int (*chip_diag) (struct scsi_qla_host *);
3135 void (*config_rings) (struct scsi_qla_host *);
3136 void (*reset_adapter) (struct scsi_qla_host *);
3137 int (*nvram_config) (struct scsi_qla_host *);
3138 void (*update_fw_options) (struct scsi_qla_host *);
3139 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
3140
3141 char * (*pci_info_str) (struct scsi_qla_host *, char *);
3142 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
3143
3144 irq_handler_t intr_handler;
3145 void (*enable_intrs) (struct qla_hw_data *);
3146 void (*disable_intrs) (struct qla_hw_data *);
3147
3148 int (*abort_command) (srb_t *);
3149 int (*target_reset) (struct fc_port *, uint64_t, int);
3150 int (*lun_reset) (struct fc_port *, uint64_t, int);
3151 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
3152 uint8_t, uint8_t, uint16_t *, uint8_t);
3153 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
3154 uint8_t, uint8_t);
3155
3156 uint16_t (*calc_req_entries) (uint16_t);
3157 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
3158 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
3159 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
3160 uint32_t);
3161
3162 uint8_t *(*read_nvram) (struct scsi_qla_host *, uint8_t *,
3163 uint32_t, uint32_t);
3164 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
3165 uint32_t);
3166
3167 void (*fw_dump) (struct scsi_qla_host *, int);
3168
3169 int (*beacon_on) (struct scsi_qla_host *);
3170 int (*beacon_off) (struct scsi_qla_host *);
3171 void (*beacon_blink) (struct scsi_qla_host *);
3172
3173 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
3174 uint32_t, uint32_t);
3175 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
3176 uint32_t);
3177
3178 int (*get_flash_version) (struct scsi_qla_host *, void *);
3179 int (*start_scsi) (srb_t *);
3180 int (*start_scsi_mq) (srb_t *);
3181 int (*abort_isp) (struct scsi_qla_host *);
3182 int (*iospace_config)(struct qla_hw_data*);
3183 int (*initialize_adapter)(struct scsi_qla_host *);
3184 };
3185
3186 /* MSI-X Support *************************************************************/
3187
3188 #define QLA_MSIX_CHIP_REV_24XX 3
3189 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
3190 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
3191
3192 #define QLA_BASE_VECTORS 2 /* default + RSP */
3193 #define QLA_MSIX_RSP_Q 0x01
3194 #define QLA_ATIO_VECTOR 0x02
3195 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
3196
3197 #define QLA_MIDX_DEFAULT 0
3198 #define QLA_MIDX_RSP_Q 1
3199 #define QLA_PCI_MSIX_CONTROL 0xa2
3200 #define QLA_83XX_PCI_MSIX_CONTROL 0x92
3201
3202 struct scsi_qla_host;
3203
3204
3205 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */
3206
3207 struct qla_msix_entry {
3208 int have_irq;
3209 int in_use;
3210 uint32_t vector;
3211 uint16_t entry;
3212 char name[30];
3213 void *handle;
3214 int cpuid;
3215 };
3216
3217 #define WATCH_INTERVAL 1 /* number of seconds */
3218
3219 /* Work events. */
3220 enum qla_work_type {
3221 QLA_EVT_AEN,
3222 QLA_EVT_IDC_ACK,
3223 QLA_EVT_ASYNC_LOGIN,
3224 QLA_EVT_ASYNC_LOGOUT,
3225 QLA_EVT_ASYNC_LOGOUT_DONE,
3226 QLA_EVT_ASYNC_ADISC,
3227 QLA_EVT_UEVENT,
3228 QLA_EVT_AENFX,
3229 QLA_EVT_GPNID,
3230 QLA_EVT_UNMAP,
3231 QLA_EVT_NEW_SESS,
3232 QLA_EVT_GPDB,
3233 QLA_EVT_PRLI,
3234 QLA_EVT_GPSC,
3235 QLA_EVT_GNL,
3236 QLA_EVT_NACK,
3237 QLA_EVT_RELOGIN,
3238 QLA_EVT_ASYNC_PRLO,
3239 QLA_EVT_ASYNC_PRLO_DONE,
3240 QLA_EVT_GPNFT,
3241 QLA_EVT_GPNFT_DONE,
3242 QLA_EVT_GNNFT_DONE,
3243 QLA_EVT_GNNID,
3244 QLA_EVT_GFPNID,
3245 QLA_EVT_SP_RETRY,
3246 QLA_EVT_IIDMA,
3247 QLA_EVT_ELS_PLOGI,
3248 };
3249
3250
3251 struct qla_work_evt {
3252 struct list_head list;
3253 enum qla_work_type type;
3254 u32 flags;
3255 #define QLA_EVT_FLAG_FREE 0x1
3256
3257 union {
3258 struct {
3259 enum fc_host_event_code code;
3260 u32 data;
3261 } aen;
3262 struct {
3263 #define QLA_IDC_ACK_REGS 7
3264 uint16_t mb[QLA_IDC_ACK_REGS];
3265 } idc_ack;
3266 struct {
3267 struct fc_port *fcport;
3268 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
3269 u16 data[2];
3270 } logio;
3271 struct {
3272 u32 code;
3273 #define QLA_UEVENT_CODE_FW_DUMP 0
3274 } uevent;
3275 struct {
3276 uint32_t evtcode;
3277 uint32_t mbx[8];
3278 uint32_t count;
3279 } aenfx;
3280 struct {
3281 srb_t *sp;
3282 } iosb;
3283 struct {
3284 port_id_t id;
3285 } gpnid;
3286 struct {
3287 port_id_t id;
3288 u8 port_name[8];
3289 u8 node_name[8];
3290 void *pla;
3291 u8 fc4_type;
3292 } new_sess;
3293 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */
3294 fc_port_t *fcport;
3295 u8 opt;
3296 } fcport;
3297 struct {
3298 fc_port_t *fcport;
3299 u8 iocb[IOCB_SIZE];
3300 int type;
3301 } nack;
3302 struct {
3303 u8 fc4_type;
3304 srb_t *sp;
3305 } gpnft;
3306 } u;
3307 };
3308
3309 struct qla_chip_state_84xx {
3310 struct list_head list;
3311 struct kref kref;
3312
3313 void *bus;
3314 spinlock_t access_lock;
3315 struct mutex fw_update_mutex;
3316 uint32_t fw_update;
3317 uint32_t op_fw_version;
3318 uint32_t op_fw_size;
3319 uint32_t op_fw_seq_size;
3320 uint32_t diag_fw_version;
3321 uint32_t gold_fw_version;
3322 };
3323
3324 struct qla_dif_statistics {
3325 uint64_t dif_input_bytes;
3326 uint64_t dif_output_bytes;
3327 uint64_t dif_input_requests;
3328 uint64_t dif_output_requests;
3329 uint32_t dif_guard_err;
3330 uint32_t dif_ref_tag_err;
3331 uint32_t dif_app_tag_err;
3332 };
3333
3334 struct qla_statistics {
3335 uint32_t total_isp_aborts;
3336 uint64_t input_bytes;
3337 uint64_t output_bytes;
3338 uint64_t input_requests;
3339 uint64_t output_requests;
3340 uint32_t control_requests;
3341
3342 uint64_t jiffies_at_last_reset;
3343 uint32_t stat_max_pend_cmds;
3344 uint32_t stat_max_qfull_cmds_alloc;
3345 uint32_t stat_max_qfull_cmds_dropped;
3346
3347 struct qla_dif_statistics qla_dif_stats;
3348 };
3349
3350 struct bidi_statistics {
3351 unsigned long long io_count;
3352 unsigned long long transfer_bytes;
3353 };
3354
3355 struct qla_tc_param {
3356 struct scsi_qla_host *vha;
3357 uint32_t blk_sz;
3358 uint32_t bufflen;
3359 struct scatterlist *sg;
3360 struct scatterlist *prot_sg;
3361 struct crc_context *ctx;
3362 uint8_t *ctx_dsd_alloced;
3363 };
3364
3365 /* Multi queue support */
3366 #define MBC_INITIALIZE_MULTIQ 0x1f
3367 #define QLA_QUE_PAGE 0X1000
3368 #define QLA_MQ_SIZE 32
3369 #define QLA_MAX_QUEUES 256
3370 #define ISP_QUE_REG(ha, id) \
3371 ((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \
3372 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3373 ((void __iomem *)ha->iobase))
3374 #define QLA_REQ_QUE_ID(tag) \
3375 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
3376 #define QLA_DEFAULT_QUE_QOS 5
3377 #define QLA_PRECONFIG_VPORTS 32
3378 #define QLA_MAX_VPORTS_QLA24XX 128
3379 #define QLA_MAX_VPORTS_QLA25XX 256
3380
3381 struct qla_tgt_counters {
3382 uint64_t qla_core_sbt_cmd;
3383 uint64_t core_qla_que_buf;
3384 uint64_t qla_core_ret_ctio;
3385 uint64_t core_qla_snd_status;
3386 uint64_t qla_core_ret_sta_ctio;
3387 uint64_t core_qla_free_cmd;
3388 uint64_t num_q_full_sent;
3389 uint64_t num_alloc_iocb_failed;
3390 uint64_t num_term_xchg_sent;
3391 };
3392
3393 struct qla_qpair;
3394
3395 /* Response queue data structure */
3396 struct rsp_que {
3397 dma_addr_t dma;
3398 response_t *ring;
3399 response_t *ring_ptr;
3400 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
3401 uint32_t __iomem *rsp_q_out;
3402 uint16_t ring_index;
3403 uint16_t out_ptr;
3404 uint16_t *in_ptr; /* queue shadow in index */
3405 uint16_t length;
3406 uint16_t options;
3407 uint16_t rid;
3408 uint16_t id;
3409 uint16_t vp_idx;
3410 struct qla_hw_data *hw;
3411 struct qla_msix_entry *msix;
3412 struct req_que *req;
3413 srb_t *status_srb; /* status continuation entry */
3414 struct qla_qpair *qpair;
3415
3416 dma_addr_t dma_fx00;
3417 response_t *ring_fx00;
3418 uint16_t length_fx00;
3419 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
3420 };
3421
3422 /* Request queue data structure */
3423 struct req_que {
3424 dma_addr_t dma;
3425 request_t *ring;
3426 request_t *ring_ptr;
3427 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
3428 uint32_t __iomem *req_q_out;
3429 uint16_t ring_index;
3430 uint16_t in_ptr;
3431 uint16_t *out_ptr; /* queue shadow out index */
3432 uint16_t cnt;
3433 uint16_t length;
3434 uint16_t options;
3435 uint16_t rid;
3436 uint16_t id;
3437 uint16_t qos;
3438 uint16_t vp_idx;
3439 struct rsp_que *rsp;
3440 srb_t **outstanding_cmds;
3441 uint32_t current_outstanding_cmd;
3442 uint16_t num_outstanding_cmds;
3443 int max_q_depth;
3444
3445 dma_addr_t dma_fx00;
3446 request_t *ring_fx00;
3447 uint16_t length_fx00;
3448 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
3449 };
3450
3451 /*Queue pair data structure */
3452 struct qla_qpair {
3453 spinlock_t qp_lock;
3454 atomic_t ref_count;
3455 uint32_t lun_cnt;
3456 /*
3457 * For qpair 0, qp_lock_ptr will point at hardware_lock due to
3458 * legacy code. For other Qpair(s), it will point at qp_lock.
3459 */
3460 spinlock_t *qp_lock_ptr;
3461 struct scsi_qla_host *vha;
3462 u32 chip_reset;
3463
3464 /* distill these fields down to 'online=0/1'
3465 * ha->flags.eeh_busy
3466 * ha->flags.pci_channel_io_perm_failure
3467 * base_vha->loop_state
3468 */
3469 uint32_t online:1;
3470 /* move vha->flags.difdix_supported here */
3471 uint32_t difdix_supported:1;
3472 uint32_t delete_in_progress:1;
3473 uint32_t fw_started:1;
3474 uint32_t enable_class_2:1;
3475 uint32_t enable_explicit_conf:1;
3476 uint32_t use_shadow_reg:1;
3477
3478 uint16_t id; /* qp number used with FW */
3479 uint16_t vp_idx; /* vport ID */
3480 mempool_t *srb_mempool;
3481
3482 struct pci_dev *pdev;
3483 void (*reqq_start_iocbs)(struct qla_qpair *);
3484
3485 /* to do: New driver: move queues to here instead of pointers */
3486 struct req_que *req;
3487 struct rsp_que *rsp;
3488 struct atio_que *atio;
3489 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */
3490 struct qla_hw_data *hw;
3491 struct work_struct q_work;
3492 struct list_head qp_list_elem; /* vha->qp_list */
3493 struct list_head hints_list;
3494 uint16_t cpuid;
3495 uint16_t retry_term_cnt;
3496 uint32_t retry_term_exchg_addr;
3497 uint64_t retry_term_jiff;
3498 struct qla_tgt_counters tgt_counters;
3499 };
3500
3501 /* Place holder for FW buffer parameters */
3502 struct qlfc_fw {
3503 void *fw_buf;
3504 dma_addr_t fw_dma;
3505 uint32_t len;
3506 };
3507
3508 struct scsi_qlt_host {
3509 void *target_lport_ptr;
3510 struct mutex tgt_mutex;
3511 struct mutex tgt_host_action_mutex;
3512 struct qla_tgt *qla_tgt;
3513 };
3514
3515 struct qlt_hw_data {
3516 /* Protected by hw lock */
3517 uint32_t node_name_set:1;
3518
3519 dma_addr_t atio_dma; /* Physical address. */
3520 struct atio *atio_ring; /* Base virtual address */
3521 struct atio *atio_ring_ptr; /* Current address. */
3522 uint16_t atio_ring_index; /* Current index. */
3523 uint16_t atio_q_length;
3524 uint32_t __iomem *atio_q_in;
3525 uint32_t __iomem *atio_q_out;
3526
3527 struct qla_tgt_func_tmpl *tgt_ops;
3528 struct qla_tgt_vp_map *tgt_vp_map;
3529
3530 int saved_set;
3531 uint16_t saved_exchange_count;
3532 uint32_t saved_firmware_options_1;
3533 uint32_t saved_firmware_options_2;
3534 uint32_t saved_firmware_options_3;
3535 uint8_t saved_firmware_options[2];
3536 uint8_t saved_add_firmware_options[2];
3537
3538 uint8_t tgt_node_name[WWN_SIZE];
3539
3540 struct dentry *dfs_tgt_sess;
3541 struct dentry *dfs_tgt_port_database;
3542 struct dentry *dfs_naqp;
3543
3544 struct list_head q_full_list;
3545 uint32_t num_pend_cmds;
3546 uint32_t num_qfull_cmds_alloc;
3547 uint32_t num_qfull_cmds_dropped;
3548 spinlock_t q_full_lock;
3549 uint32_t leak_exchg_thresh_hold;
3550 spinlock_t sess_lock;
3551 int num_act_qpairs;
3552 #define DEFAULT_NAQP 2
3553 spinlock_t atio_lock ____cacheline_aligned;
3554 struct btree_head32 host_map;
3555 };
3556
3557 #define MAX_QFULL_CMDS_ALLOC 8192
3558 #define Q_FULL_THRESH_HOLD_PERCENT 90
3559 #define Q_FULL_THRESH_HOLD(ha) \
3560 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
3561
3562 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */
3563
3564 /*
3565 * Qlogic host adapter specific data structure.
3566 */
3567 struct qla_hw_data {
3568 struct pci_dev *pdev;
3569 /* SRB cache. */
3570 #define SRB_MIN_REQ 128
3571 mempool_t *srb_mempool;
3572
3573 volatile struct {
3574 uint32_t mbox_int :1;
3575 uint32_t mbox_busy :1;
3576 uint32_t disable_risc_code_load :1;
3577 uint32_t enable_64bit_addressing :1;
3578 uint32_t enable_lip_reset :1;
3579 uint32_t enable_target_reset :1;
3580 uint32_t enable_lip_full_login :1;
3581 uint32_t enable_led_scheme :1;
3582
3583 uint32_t msi_enabled :1;
3584 uint32_t msix_enabled :1;
3585 uint32_t disable_serdes :1;
3586 uint32_t gpsc_supported :1;
3587 uint32_t npiv_supported :1;
3588 uint32_t pci_channel_io_perm_failure :1;
3589 uint32_t fce_enabled :1;
3590 uint32_t fac_supported :1;
3591
3592 uint32_t chip_reset_done :1;
3593 uint32_t running_gold_fw :1;
3594 uint32_t eeh_busy :1;
3595 uint32_t disable_msix_handshake :1;
3596 uint32_t fcp_prio_enabled :1;
3597 uint32_t isp82xx_fw_hung:1;
3598 uint32_t nic_core_hung:1;
3599
3600 uint32_t quiesce_owner:1;
3601 uint32_t nic_core_reset_hdlr_active:1;
3602 uint32_t nic_core_reset_owner:1;
3603 uint32_t isp82xx_no_md_cap:1;
3604 uint32_t host_shutting_down:1;
3605 uint32_t idc_compl_status:1;
3606 uint32_t mr_reset_hdlr_active:1;
3607 uint32_t mr_intr_valid:1;
3608
3609 uint32_t dport_enabled:1;
3610 uint32_t fawwpn_enabled:1;
3611 uint32_t exlogins_enabled:1;
3612 uint32_t exchoffld_enabled:1;
3613
3614 uint32_t lip_ae:1;
3615 uint32_t n2n_ae:1;
3616 uint32_t fw_started:1;
3617 uint32_t fw_init_done:1;
3618
3619 uint32_t detected_lr_sfp:1;
3620 uint32_t using_lr_setting:1;
3621 uint32_t rida_fmt2:1;
3622 uint32_t purge_mbox:1;
3623 uint32_t n2n_bigger:1;
3624 } flags;
3625
3626 uint16_t max_exchg;
3627 uint16_t long_range_distance; /* 32G & above */
3628 #define LR_DISTANCE_5K 1
3629 #define LR_DISTANCE_10K 0
3630
3631 /* This spinlock is used to protect "io transactions", you must
3632 * acquire it before doing any IO to the card, eg with RD_REG*() and
3633 * WRT_REG*() for the duration of your entire commandtransaction.
3634 *
3635 * This spinlock is of lower priority than the io request lock.
3636 */
3637
3638 spinlock_t hardware_lock ____cacheline_aligned;
3639 int bars;
3640 int mem_only;
3641 device_reg_t *iobase; /* Base I/O address */
3642 resource_size_t pio_address;
3643
3644 #define MIN_IOBASE_LEN 0x100
3645 dma_addr_t bar0_hdl;
3646
3647 void __iomem *cregbase;
3648 dma_addr_t bar2_hdl;
3649 #define BAR0_LEN_FX00 (1024 * 1024)
3650 #define BAR2_LEN_FX00 (128 * 1024)
3651
3652 uint32_t rqstq_intr_code;
3653 uint32_t mbx_intr_code;
3654 uint32_t req_que_len;
3655 uint32_t rsp_que_len;
3656 uint32_t req_que_off;
3657 uint32_t rsp_que_off;
3658
3659 /* Multi queue data structs */
3660 device_reg_t *mqiobase;
3661 device_reg_t *msixbase;
3662 uint16_t msix_count;
3663 uint8_t mqenable;
3664 struct req_que **req_q_map;
3665 struct rsp_que **rsp_q_map;
3666 struct qla_qpair **queue_pair_map;
3667 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3668 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3669 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
3670 / sizeof(unsigned long)];
3671 uint8_t max_req_queues;
3672 uint8_t max_rsp_queues;
3673 uint8_t max_qpairs;
3674 uint8_t num_qpairs;
3675 struct qla_qpair *base_qpair;
3676 struct qla_npiv_entry *npiv_info;
3677 uint16_t nvram_npiv_size;
3678
3679 uint16_t switch_cap;
3680 #define FLOGI_SEQ_DEL BIT_8
3681 #define FLOGI_MID_SUPPORT BIT_10
3682 #define FLOGI_VSAN_SUPPORT BIT_12
3683 #define FLOGI_SP_SUPPORT BIT_13
3684
3685 uint8_t port_no; /* Physical port of adapter */
3686 uint8_t exch_starvation;
3687
3688 /* Timeout timers. */
3689 uint8_t loop_down_abort_time; /* port down timer */
3690 atomic_t loop_down_timer; /* loop down timer */
3691 uint8_t link_down_timeout; /* link down timeout */
3692 uint16_t max_loop_id;
3693 uint16_t max_fibre_devices; /* Maximum number of targets */
3694
3695 uint16_t fb_rev;
3696 uint16_t min_external_loopid; /* First external loop Id */
3697
3698 #define PORT_SPEED_UNKNOWN 0xFFFF
3699 #define PORT_SPEED_1GB 0x00
3700 #define PORT_SPEED_2GB 0x01
3701 #define PORT_SPEED_AUTO 0x02
3702 #define PORT_SPEED_4GB 0x03
3703 #define PORT_SPEED_8GB 0x04
3704 #define PORT_SPEED_16GB 0x05
3705 #define PORT_SPEED_32GB 0x06
3706 #define PORT_SPEED_10GB 0x13
3707 uint16_t link_data_rate; /* F/W operating speed */
3708 uint16_t set_data_rate; /* Set by user */
3709
3710 uint8_t current_topology;
3711 uint8_t prev_topology;
3712 #define ISP_CFG_NL 1
3713 #define ISP_CFG_N 2
3714 #define ISP_CFG_FL 4
3715 #define ISP_CFG_F 8
3716
3717 uint8_t operating_mode; /* F/W operating mode */
3718 #define LOOP 0
3719 #define P2P 1
3720 #define LOOP_P2P 2
3721 #define P2P_LOOP 3
3722 uint8_t interrupts_on;
3723 uint32_t isp_abort_cnt;
3724 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
3725 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
3726 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
3727 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
3728 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
3729 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
3730 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
3731 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
3732
3733 uint32_t isp_type;
3734 #define DT_ISP2100 BIT_0
3735 #define DT_ISP2200 BIT_1
3736 #define DT_ISP2300 BIT_2
3737 #define DT_ISP2312 BIT_3
3738 #define DT_ISP2322 BIT_4
3739 #define DT_ISP6312 BIT_5
3740 #define DT_ISP6322 BIT_6
3741 #define DT_ISP2422 BIT_7
3742 #define DT_ISP2432 BIT_8
3743 #define DT_ISP5422 BIT_9
3744 #define DT_ISP5432 BIT_10
3745 #define DT_ISP2532 BIT_11
3746 #define DT_ISP8432 BIT_12
3747 #define DT_ISP8001 BIT_13
3748 #define DT_ISP8021 BIT_14
3749 #define DT_ISP2031 BIT_15
3750 #define DT_ISP8031 BIT_16
3751 #define DT_ISPFX00 BIT_17
3752 #define DT_ISP8044 BIT_18
3753 #define DT_ISP2071 BIT_19
3754 #define DT_ISP2271 BIT_20
3755 #define DT_ISP2261 BIT_21
3756 #define DT_ISP_LAST (DT_ISP2261 << 1)
3757
3758 uint32_t device_type;
3759 #define DT_T10_PI BIT_25
3760 #define DT_IIDMA BIT_26
3761 #define DT_FWI2 BIT_27
3762 #define DT_ZIO_SUPPORTED BIT_28
3763 #define DT_OEM_001 BIT_29
3764 #define DT_ISP2200A BIT_30
3765 #define DT_EXTENDED_IDS BIT_31
3766
3767 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
3768 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
3769 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
3770 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
3771 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
3772 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
3773 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
3774 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
3775 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
3776 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
3777 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
3778 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
3779 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
3780 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
3781 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
3782 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
3783 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
3784 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
3785 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
3786 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
3787 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
3788 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
3789 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
3790 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
3791
3792 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
3793 IS_QLA6312(ha) || IS_QLA6322(ha))
3794 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
3795 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
3796 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
3797 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
3798 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
3799 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
3800 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
3801 IS_QLA84XX(ha))
3802 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
3803 IS_QLA8031(ha) || IS_QLA8044(ha))
3804 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
3805 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
3806 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
3807 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
3808 IS_QLA8044(ha) || IS_QLA27XX(ha))
3809 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3810 IS_QLA27XX(ha))
3811 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
3812 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3813 IS_QLA27XX(ha))
3814 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3815 IS_QLA27XX(ha))
3816 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
3817
3818 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
3819 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
3820 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
3821 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
3822 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
3823 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
3824 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
3825 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
3826 IS_QLA27XX(ha))
3827 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha)))
3828 /* Bit 21 of fw_attributes decides the MCTP capabilities */
3829 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
3830 ((ha)->fw_attributes_ext[0] & BIT_0))
3831 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3832 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3833 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
3834 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3835 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
3836 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
3837 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3838 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
3839 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha))
3840 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3841 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3842 #define IS_EXCHG_OFFLD_CAPABLE(ha) \
3843 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
3844 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
3845 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
3846 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\
3847 IS_QLA83XX(ha) || IS_QLA27XX(ha))
3848
3849 /* HBA serial number */
3850 uint8_t serial0;
3851 uint8_t serial1;
3852 uint8_t serial2;
3853
3854 /* NVRAM configuration data */
3855 #define MAX_NVRAM_SIZE 4096
3856 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
3857 uint16_t nvram_size;
3858 uint16_t nvram_base;
3859 void *nvram;
3860 uint16_t vpd_size;
3861 uint16_t vpd_base;
3862 void *vpd;
3863
3864 uint16_t loop_reset_delay;
3865 uint8_t retry_count;
3866 uint8_t login_timeout;
3867 uint16_t r_a_tov;
3868 int port_down_retry_count;
3869 uint8_t mbx_count;
3870 uint8_t aen_mbx_count;
3871 atomic_t num_pend_mbx_stage1;
3872 atomic_t num_pend_mbx_stage2;
3873 atomic_t num_pend_mbx_stage3;
3874 uint16_t frame_payload_size;
3875
3876 uint32_t login_retry_count;
3877 /* SNS command interfaces. */
3878 ms_iocb_entry_t *ms_iocb;
3879 dma_addr_t ms_iocb_dma;
3880 struct ct_sns_pkt *ct_sns;
3881 dma_addr_t ct_sns_dma;
3882 /* SNS command interfaces for 2200. */
3883 struct sns_cmd_pkt *sns_cmd;
3884 dma_addr_t sns_cmd_dma;
3885
3886 #define SFP_DEV_SIZE 512
3887 #define SFP_BLOCK_SIZE 64
3888 void *sfp_data;
3889 dma_addr_t sfp_data_dma;
3890
3891 #define XGMAC_DATA_SIZE 4096
3892 void *xgmac_data;
3893 dma_addr_t xgmac_data_dma;
3894
3895 #define DCBX_TLV_DATA_SIZE 4096
3896 void *dcbx_tlv;
3897 dma_addr_t dcbx_tlv_dma;
3898
3899 struct task_struct *dpc_thread;
3900 uint8_t dpc_active; /* DPC routine is active */
3901
3902 dma_addr_t gid_list_dma;
3903 struct gid_list_info *gid_list;
3904 int gid_list_info_size;
3905
3906 /* Small DMA pool allocations -- maximum 256 bytes in length. */
3907 #define DMA_POOL_SIZE 256
3908 struct dma_pool *s_dma_pool;
3909
3910 dma_addr_t init_cb_dma;
3911 init_cb_t *init_cb;
3912 int init_cb_size;
3913 dma_addr_t ex_init_cb_dma;
3914 struct ex_init_cb_81xx *ex_init_cb;
3915
3916 void *async_pd;
3917 dma_addr_t async_pd_dma;
3918
3919 #define ENABLE_EXTENDED_LOGIN BIT_7
3920
3921 /* Extended Logins */
3922 void *exlogin_buf;
3923 dma_addr_t exlogin_buf_dma;
3924 int exlogin_size;
3925
3926 #define ENABLE_EXCHANGE_OFFLD BIT_2
3927
3928 /* Exchange Offload */
3929 void *exchoffld_buf;
3930 dma_addr_t exchoffld_buf_dma;
3931 int exchoffld_size;
3932 int exchoffld_count;
3933
3934 /* n2n */
3935 struct els_plogi_payload plogi_els_payld;
3936
3937 void *swl;
3938
3939 /* These are used by mailbox operations. */
3940 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
3941 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
3942 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
3943
3944 mbx_cmd_t *mcp;
3945 struct mbx_cmd_32 *mcp32;
3946
3947 unsigned long mbx_cmd_flags;
3948 #define MBX_INTERRUPT 1
3949 #define MBX_INTR_WAIT 2
3950 #define MBX_UPDATE_FLASH_ACTIVE 3
3951
3952 struct mutex vport_lock; /* Virtual port synchronization */
3953 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
3954 struct mutex mq_lock; /* multi-queue synchronization */
3955 struct completion mbx_cmd_comp; /* Serialize mbx access */
3956 struct completion mbx_intr_comp; /* Used for completion notification */
3957 struct completion dcbx_comp; /* For set port config notification */
3958 struct completion lb_portup_comp; /* Used to wait for link up during
3959 * loopback */
3960 #define DCBX_COMP_TIMEOUT 20
3961 #define LB_PORTUP_COMP_TIMEOUT 10
3962
3963 int notify_dcbx_comp;
3964 int notify_lb_portup_comp;
3965 struct mutex selflogin_lock;
3966
3967 /* Basic firmware related information. */
3968 uint16_t fw_major_version;
3969 uint16_t fw_minor_version;
3970 uint16_t fw_subminor_version;
3971 uint16_t fw_attributes;
3972 uint16_t fw_attributes_h;
3973 #define FW_ATTR_H_NVME_FBURST BIT_1
3974 #define FW_ATTR_H_NVME BIT_10
3975 #define FW_ATTR_H_NVME_UPDATED BIT_14
3976
3977 uint16_t fw_attributes_ext[2];
3978 uint32_t fw_memory_size;
3979 uint32_t fw_transfer_size;
3980 uint32_t fw_srisc_address;
3981 #define RISC_START_ADDRESS_2100 0x1000
3982 #define RISC_START_ADDRESS_2300 0x800
3983 #define RISC_START_ADDRESS_2400 0x100000
3984
3985 uint16_t orig_fw_tgt_xcb_count;
3986 uint16_t cur_fw_tgt_xcb_count;
3987 uint16_t orig_fw_xcb_count;
3988 uint16_t cur_fw_xcb_count;
3989 uint16_t orig_fw_iocb_count;
3990 uint16_t cur_fw_iocb_count;
3991 uint16_t fw_max_fcf_count;
3992
3993 uint32_t fw_shared_ram_start;
3994 uint32_t fw_shared_ram_end;
3995 uint32_t fw_ddr_ram_start;
3996 uint32_t fw_ddr_ram_end;
3997
3998 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
3999 uint8_t fw_seriallink_options[4];
4000 uint16_t fw_seriallink_options24[4];
4001
4002 uint8_t mpi_version[3];
4003 uint32_t mpi_capabilities;
4004 uint8_t phy_version[3];
4005 uint8_t pep_version[3];
4006
4007 /* Firmware dump template */
4008 void *fw_dump_template;
4009 uint32_t fw_dump_template_len;
4010 /* Firmware dump information. */
4011 struct qla2xxx_fw_dump *fw_dump;
4012 uint32_t fw_dump_len;
4013 int fw_dumped;
4014 unsigned long fw_dump_cap_flags;
4015 #define RISC_PAUSE_CMPL 0
4016 #define DMA_SHUTDOWN_CMPL 1
4017 #define ISP_RESET_CMPL 2
4018 #define RISC_RDY_AFT_RESET 3
4019 #define RISC_SRAM_DUMP_CMPL 4
4020 #define RISC_EXT_MEM_DUMP_CMPL 5
4021 #define ISP_MBX_RDY 6
4022 #define ISP_SOFT_RESET_CMPL 7
4023 int fw_dump_reading;
4024 int prev_minidump_failed;
4025 dma_addr_t eft_dma;
4026 void *eft;
4027 /* Current size of mctp dump is 0x086064 bytes */
4028 #define MCTP_DUMP_SIZE 0x086064
4029 dma_addr_t mctp_dump_dma;
4030 void *mctp_dump;
4031 int mctp_dumped;
4032 int mctp_dump_reading;
4033 uint32_t chain_offset;
4034 struct dentry *dfs_dir;
4035 struct dentry *dfs_fce;
4036 struct dentry *dfs_tgt_counters;
4037 struct dentry *dfs_fw_resource_cnt;
4038
4039 dma_addr_t fce_dma;
4040 void *fce;
4041 uint32_t fce_bufs;
4042 uint16_t fce_mb[8];
4043 uint64_t fce_wr, fce_rd;
4044 struct mutex fce_mutex;
4045
4046 uint32_t pci_attr;
4047 uint16_t chip_revision;
4048
4049 uint16_t product_id[4];
4050
4051 uint8_t model_number[16+1];
4052 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
4053 char model_desc[80];
4054 uint8_t adapter_id[16+1];
4055
4056 /* Option ROM information. */
4057 char *optrom_buffer;
4058 uint32_t optrom_size;
4059 int optrom_state;
4060 #define QLA_SWAITING 0
4061 #define QLA_SREADING 1
4062 #define QLA_SWRITING 2
4063 uint32_t optrom_region_start;
4064 uint32_t optrom_region_size;
4065 struct mutex optrom_mutex;
4066
4067 /* PCI expansion ROM image information. */
4068 #define ROM_CODE_TYPE_BIOS 0
4069 #define ROM_CODE_TYPE_FCODE 1
4070 #define ROM_CODE_TYPE_EFI 3
4071 uint8_t bios_revision[2];
4072 uint8_t efi_revision[2];
4073 uint8_t fcode_revision[16];
4074 uint32_t fw_revision[4];
4075
4076 uint32_t gold_fw_version[4];
4077
4078 /* Offsets for flash/nvram access (set to ~0 if not used). */
4079 uint32_t flash_conf_off;
4080 uint32_t flash_data_off;
4081 uint32_t nvram_conf_off;
4082 uint32_t nvram_data_off;
4083
4084 uint32_t fdt_wrt_disable;
4085 uint32_t fdt_wrt_enable;
4086 uint32_t fdt_erase_cmd;
4087 uint32_t fdt_block_size;
4088 uint32_t fdt_unprotect_sec_cmd;
4089 uint32_t fdt_protect_sec_cmd;
4090 uint32_t fdt_wrt_sts_reg_cmd;
4091
4092 uint32_t flt_region_flt;
4093 uint32_t flt_region_fdt;
4094 uint32_t flt_region_boot;
4095 uint32_t flt_region_boot_sec;
4096 uint32_t flt_region_fw;
4097 uint32_t flt_region_fw_sec;
4098 uint32_t flt_region_vpd_nvram;
4099 uint32_t flt_region_vpd;
4100 uint32_t flt_region_vpd_sec;
4101 uint32_t flt_region_nvram;
4102 uint32_t flt_region_npiv_conf;
4103 uint32_t flt_region_gold_fw;
4104 uint32_t flt_region_fcp_prio;
4105 uint32_t flt_region_bootload;
4106 uint32_t flt_region_img_status_pri;
4107 uint32_t flt_region_img_status_sec;
4108 uint8_t active_image;
4109
4110 /* Needed for BEACON */
4111 uint16_t beacon_blink_led;
4112 uint8_t beacon_color_state;
4113 #define QLA_LED_GRN_ON 0x01
4114 #define QLA_LED_YLW_ON 0x02
4115 #define QLA_LED_ABR_ON 0x04
4116 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
4117 /* ISP2322: red, green, amber. */
4118 uint16_t zio_mode;
4119 uint16_t zio_timer;
4120
4121 struct qla_msix_entry *msix_entries;
4122
4123 struct list_head vp_list; /* list of VP */
4124 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
4125 sizeof(unsigned long)];
4126 uint16_t num_vhosts; /* number of vports created */
4127 uint16_t num_vsans; /* number of vsan created */
4128 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
4129 int cur_vport_count;
4130
4131 struct qla_chip_state_84xx *cs84xx;
4132 struct isp_operations *isp_ops;
4133 struct workqueue_struct *wq;
4134 struct qlfc_fw fw_buf;
4135
4136 /* FCP_CMND priority support */
4137 struct qla_fcp_prio_cfg *fcp_prio_cfg;
4138
4139 struct dma_pool *dl_dma_pool;
4140 #define DSD_LIST_DMA_POOL_SIZE 512
4141
4142 struct dma_pool *fcp_cmnd_dma_pool;
4143 mempool_t *ctx_mempool;
4144 #define FCP_CMND_DMA_POOL_SIZE 512
4145
4146 void __iomem *nx_pcibase; /* Base I/O address */
4147 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */
4148 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */
4149
4150 uint32_t crb_win;
4151 uint32_t curr_window;
4152 uint32_t ddr_mn_window;
4153 unsigned long mn_win_crb;
4154 unsigned long ms_win_crb;
4155 int qdr_sn_window;
4156 uint32_t fcoe_dev_init_timeout;
4157 uint32_t fcoe_reset_timeout;
4158 rwlock_t hw_lock;
4159 uint16_t portnum; /* port number */
4160 int link_width;
4161 struct fw_blob *hablob;
4162 struct qla82xx_legacy_intr_set nx_legacy_intr;
4163
4164 uint16_t gbl_dsd_inuse;
4165 uint16_t gbl_dsd_avail;
4166 struct list_head gbl_dsd_list;
4167 #define NUM_DSD_CHAIN 4096
4168
4169 uint8_t fw_type;
4170 __le32 file_prd_off; /* File firmware product offset */
4171
4172 uint32_t md_template_size;
4173 void *md_tmplt_hdr;
4174 dma_addr_t md_tmplt_hdr_dma;
4175 void *md_dump;
4176 uint32_t md_dump_size;
4177
4178 void *loop_id_map;
4179
4180 /* QLA83XX IDC specific fields */
4181 uint32_t idc_audit_ts;
4182 uint32_t idc_extend_tmo;
4183
4184 /* DPC low-priority workqueue */
4185 struct workqueue_struct *dpc_lp_wq;
4186 struct work_struct idc_aen;
4187 /* DPC high-priority workqueue */
4188 struct workqueue_struct *dpc_hp_wq;
4189 struct work_struct nic_core_reset;
4190 struct work_struct idc_state_handler;
4191 struct work_struct nic_core_unrecoverable;
4192 struct work_struct board_disable;
4193
4194 struct mr_data_fx00 mr;
4195 uint32_t chip_reset;
4196
4197 struct qlt_hw_data tgt;
4198 int allow_cna_fw_dump;
4199 uint32_t fw_ability_mask;
4200 uint16_t min_link_speed;
4201 uint16_t max_speed_sup;
4202
4203 /* DMA pool for the DIF bundling buffers */
4204 struct dma_pool *dif_bundl_pool;
4205 #define DIF_BUNDLING_DMA_POOL_SIZE 1024
4206 struct {
4207 struct {
4208 struct list_head head;
4209 uint count;
4210 } good;
4211 struct {
4212 struct list_head head;
4213 uint count;
4214 } unusable;
4215 } pool;
4216
4217 unsigned long long dif_bundle_crossed_pages;
4218 unsigned long long dif_bundle_reads;
4219 unsigned long long dif_bundle_writes;
4220 unsigned long long dif_bundle_kallocs;
4221 unsigned long long dif_bundle_dma_allocs;
4222
4223 atomic_t nvme_active_aen_cnt;
4224 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */
4225
4226 atomic_t zio_threshold;
4227 uint16_t last_zio_threshold;
4228 #define DEFAULT_ZIO_THRESHOLD 5
4229 };
4230
4231 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL
4232 #define FW_ABILITY_MAX_SPEED_16G 0x0
4233 #define FW_ABILITY_MAX_SPEED_32G 0x1
4234 #define FW_ABILITY_MAX_SPEED(ha) \
4235 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
4236
4237 #define QLA_GET_DATA_RATE 0
4238 #define QLA_SET_DATA_RATE_NOLR 1
4239 #define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */
4240
4241 /*
4242 * Qlogic scsi host structure
4243 */
4244 typedef struct scsi_qla_host {
4245 struct list_head list;
4246 struct list_head vp_fcports; /* list of fcports */
4247 struct list_head work_list;
4248 spinlock_t work_lock;
4249 struct work_struct iocb_work;
4250
4251 /* Commonly used flags and state information. */
4252 struct Scsi_Host *host;
4253 unsigned long host_no;
4254 uint8_t host_str[16];
4255
4256 volatile struct {
4257 uint32_t init_done :1;
4258 uint32_t online :1;
4259 uint32_t reset_active :1;
4260
4261 uint32_t management_server_logged_in :1;
4262 uint32_t process_response_queue :1;
4263 uint32_t difdix_supported:1;
4264 uint32_t delete_progress:1;
4265
4266 uint32_t fw_tgt_reported:1;
4267 uint32_t bbcr_enable:1;
4268 uint32_t qpairs_available:1;
4269 uint32_t qpairs_req_created:1;
4270 uint32_t qpairs_rsp_created:1;
4271 uint32_t nvme_enabled:1;
4272 uint32_t nvme_first_burst:1;
4273 } flags;
4274
4275 atomic_t loop_state;
4276 #define LOOP_TIMEOUT 1
4277 #define LOOP_DOWN 2
4278 #define LOOP_UP 3
4279 #define LOOP_UPDATE 4
4280 #define LOOP_READY 5
4281 #define LOOP_DEAD 6
4282
4283 unsigned long relogin_jif;
4284 unsigned long dpc_flags;
4285 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
4286 #define RESET_ACTIVE 1
4287 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
4288 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
4289 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
4290 #define LOOP_RESYNC_ACTIVE 5
4291 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
4292 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
4293 #define RELOGIN_NEEDED 8
4294 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
4295 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
4296 #define BEACON_BLINK_NEEDED 11
4297 #define REGISTER_FDMI_NEEDED 12
4298 #define FCPORT_UPDATE_NEEDED 13
4299 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
4300 #define UNLOADING 15
4301 #define NPIV_CONFIG_NEEDED 16
4302 #define ISP_UNRECOVERABLE 17
4303 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
4304 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
4305 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
4306 #define N2N_LINK_RESET 21
4307 #define PORT_UPDATE_NEEDED 22
4308 #define FX00_RESET_RECOVERY 23
4309 #define FX00_TARGET_SCAN 24
4310 #define FX00_CRITEMP_RECOVERY 25
4311 #define FX00_HOST_INFO_RESEND 26
4312 #define QPAIR_ONLINE_CHECK_NEEDED 27
4313 #define SET_NVME_ZIO_THRESHOLD_NEEDED 28
4314 #define DETECT_SFP_CHANGE 29
4315 #define N2N_LOGIN_NEEDED 30
4316 #define IOCB_WORK_ACTIVE 31
4317 #define SET_ZIO_THRESHOLD_NEEDED 32
4318
4319 unsigned long pci_flags;
4320 #define PFLG_DISCONNECTED 0 /* PCI device removed */
4321 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */
4322 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */
4323
4324 uint32_t device_flags;
4325 #define SWITCH_FOUND BIT_0
4326 #define DFLG_NO_CABLE BIT_1
4327 #define DFLG_DEV_FAILED BIT_5
4328
4329 /* ISP configuration data. */
4330 uint16_t loop_id; /* Host adapter loop id */
4331 uint16_t self_login_loop_id; /* host adapter loop id
4332 * get it on self login
4333 */
4334 fc_port_t bidir_fcport; /* fcport used for bidir cmnds
4335 * no need of allocating it for
4336 * each command
4337 */
4338
4339 port_id_t d_id; /* Host adapter port id */
4340 uint8_t marker_needed;
4341 uint16_t mgmt_svr_loop_id;
4342
4343
4344
4345 /* Timeout timers. */
4346 uint8_t loop_down_abort_time; /* port down timer */
4347 atomic_t loop_down_timer; /* loop down timer */
4348 uint8_t link_down_timeout; /* link down timeout */
4349
4350 uint32_t timer_active;
4351 struct timer_list timer;
4352
4353 uint8_t node_name[WWN_SIZE];
4354 uint8_t port_name[WWN_SIZE];
4355 uint8_t fabric_node_name[WWN_SIZE];
4356
4357 struct nvme_fc_local_port *nvme_local_port;
4358 struct completion nvme_del_done;
4359 struct list_head nvme_rport_list;
4360
4361 uint16_t fcoe_vlan_id;
4362 uint16_t fcoe_fcf_idx;
4363 uint8_t fcoe_vn_port_mac[6];
4364
4365 /* list of commands waiting on workqueue */
4366 struct list_head qla_cmd_list;
4367 struct list_head qla_sess_op_cmd_list;
4368 struct list_head unknown_atio_list;
4369 spinlock_t cmd_list_lock;
4370 struct delayed_work unknown_atio_work;
4371
4372 /* Counter to detect races between ELS and RSCN events */
4373 atomic_t generation_tick;
4374 /* Time when global fcport update has been scheduled */
4375 int total_fcport_update_gen;
4376 /* List of pending LOGOs, protected by tgt_mutex */
4377 struct list_head logo_list;
4378 /* List of pending PLOGI acks, protected by hw lock */
4379 struct list_head plogi_ack_list;
4380
4381 struct list_head qp_list;
4382
4383 uint32_t vp_abort_cnt;
4384
4385 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
4386 uint16_t vp_idx; /* vport ID */
4387 struct qla_qpair *qpair; /* base qpair */
4388
4389 unsigned long vp_flags;
4390 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
4391 #define VP_CREATE_NEEDED 1
4392 #define VP_BIND_NEEDED 2
4393 #define VP_DELETE_NEEDED 3
4394 #define VP_SCR_NEEDED 4 /* State Change Request registration */
4395 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */
4396 atomic_t vp_state;
4397 #define VP_OFFLINE 0
4398 #define VP_ACTIVE 1
4399 #define VP_FAILED 2
4400 // #define VP_DISABLE 3
4401 uint16_t vp_err_state;
4402 uint16_t vp_prev_err_state;
4403 #define VP_ERR_UNKWN 0
4404 #define VP_ERR_PORTDWN 1
4405 #define VP_ERR_FAB_UNSUPPORTED 2
4406 #define VP_ERR_FAB_NORESOURCES 3
4407 #define VP_ERR_FAB_LOGOUT 4
4408 #define VP_ERR_ADAP_NORESOURCES 5
4409 struct qla_hw_data *hw;
4410 struct scsi_qlt_host vha_tgt;
4411 struct req_que *req;
4412 int fw_heartbeat_counter;
4413 int seconds_since_last_heartbeat;
4414 struct fc_host_statistics fc_host_stat;
4415 struct qla_statistics qla_stats;
4416 struct bidi_statistics bidi_stats;
4417 atomic_t vref_count;
4418 struct qla8044_reset_template reset_tmplt;
4419 uint16_t bbcr;
4420
4421 uint16_t u_ql2xexchoffld;
4422 uint16_t u_ql2xiniexchg;
4423 uint16_t qlini_mode;
4424 uint16_t ql2xexchoffld;
4425 uint16_t ql2xiniexchg;
4426
4427 struct name_list_extended gnl;
4428 /* Count of active session/fcport */
4429 int fcport_count;
4430 wait_queue_head_t fcport_waitQ;
4431 wait_queue_head_t vref_waitq;
4432 uint8_t min_link_speed_feat;
4433 uint8_t n2n_node_name[WWN_SIZE];
4434 uint8_t n2n_port_name[WWN_SIZE];
4435 uint16_t n2n_id;
4436 struct list_head gpnid_list;
4437 struct fab_scan scan;
4438
4439 unsigned int irq_offset;
4440 } scsi_qla_host_t;
4441
4442 struct qla27xx_image_status {
4443 uint8_t image_status_mask;
4444 uint16_t generation_number;
4445 uint8_t reserved[3];
4446 uint8_t ver_minor;
4447 uint8_t ver_major;
4448 uint32_t checksum;
4449 uint32_t signature;
4450 } __packed;
4451
4452 #define SET_VP_IDX 1
4453 #define SET_AL_PA 2
4454 #define RESET_VP_IDX 3
4455 #define RESET_AL_PA 4
4456 struct qla_tgt_vp_map {
4457 uint8_t idx;
4458 scsi_qla_host_t *vha;
4459 };
4460
4461 struct qla2_sgx {
4462 dma_addr_t dma_addr; /* OUT */
4463 uint32_t dma_len; /* OUT */
4464
4465 uint32_t tot_bytes; /* IN */
4466 struct scatterlist *cur_sg; /* IN */
4467
4468 /* for book keeping, bzero on initial invocation */
4469 uint32_t bytes_consumed;
4470 uint32_t num_bytes;
4471 uint32_t tot_partial;
4472
4473 /* for debugging */
4474 uint32_t num_sg;
4475 srb_t *sp;
4476 };
4477
4478 #define QLA_FW_STARTED(_ha) { \
4479 int i; \
4480 _ha->flags.fw_started = 1; \
4481 _ha->base_qpair->fw_started = 1; \
4482 for (i = 0; i < _ha->max_qpairs; i++) { \
4483 if (_ha->queue_pair_map[i]) \
4484 _ha->queue_pair_map[i]->fw_started = 1; \
4485 } \
4486 }
4487
4488 #define QLA_FW_STOPPED(_ha) { \
4489 int i; \
4490 _ha->flags.fw_started = 0; \
4491 _ha->base_qpair->fw_started = 0; \
4492 for (i = 0; i < _ha->max_qpairs; i++) { \
4493 if (_ha->queue_pair_map[i]) \
4494 _ha->queue_pair_map[i]->fw_started = 0; \
4495 } \
4496 }
4497
4498 /*
4499 * Macros to help code, maintain, etc.
4500 */
4501 #define LOOP_TRANSITION(ha) \
4502 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4503 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
4504 atomic_read(&ha->loop_state) == LOOP_DOWN)
4505
4506 #define STATE_TRANSITION(ha) \
4507 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4508 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
4509
4510 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
4511 atomic_inc(&__vha->vref_count); \
4512 mb(); \
4513 if (__vha->flags.delete_progress) { \
4514 atomic_dec(&__vha->vref_count); \
4515 wake_up(&__vha->vref_waitq); \
4516 __bail = 1; \
4517 } else { \
4518 __bail = 0; \
4519 } \
4520 } while (0)
4521
4522 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
4523 atomic_dec(&__vha->vref_count); \
4524 wake_up(&__vha->vref_waitq); \
4525 } while (0) \
4526
4527 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
4528 atomic_inc(&__qpair->ref_count); \
4529 mb(); \
4530 if (__qpair->delete_in_progress) { \
4531 atomic_dec(&__qpair->ref_count); \
4532 __bail = 1; \
4533 } else { \
4534 __bail = 0; \
4535 } \
4536 } while (0)
4537
4538 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
4539 atomic_dec(&__qpair->ref_count); \
4540
4541
4542 #define QLA_ENA_CONF(_ha) {\
4543 int i;\
4544 _ha->base_qpair->enable_explicit_conf = 1; \
4545 for (i = 0; i < _ha->max_qpairs; i++) { \
4546 if (_ha->queue_pair_map[i]) \
4547 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \
4548 } \
4549 }
4550
4551 #define QLA_DIS_CONF(_ha) {\
4552 int i;\
4553 _ha->base_qpair->enable_explicit_conf = 0; \
4554 for (i = 0; i < _ha->max_qpairs; i++) { \
4555 if (_ha->queue_pair_map[i]) \
4556 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \
4557 } \
4558 }
4559
4560 /*
4561 * qla2x00 local function return status codes
4562 */
4563 #define MBS_MASK 0x3fff
4564
4565 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
4566 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
4567 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
4568 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
4569 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
4570 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
4571 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
4572 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
4573 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
4574 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
4575
4576 #define QLA_FUNCTION_TIMEOUT 0x100
4577 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
4578 #define QLA_FUNCTION_FAILED 0x102
4579 #define QLA_MEMORY_ALLOC_FAILED 0x103
4580 #define QLA_LOCK_TIMEOUT 0x104
4581 #define QLA_ABORTED 0x105
4582 #define QLA_SUSPENDED 0x106
4583 #define QLA_BUSY 0x107
4584 #define QLA_ALREADY_REGISTERED 0x109
4585
4586 #define NVRAM_DELAY() udelay(10)
4587
4588 /*
4589 * Flash support definitions
4590 */
4591 #define OPTROM_SIZE_2300 0x20000
4592 #define OPTROM_SIZE_2322 0x100000
4593 #define OPTROM_SIZE_24XX 0x100000
4594 #define OPTROM_SIZE_25XX 0x200000
4595 #define OPTROM_SIZE_81XX 0x400000
4596 #define OPTROM_SIZE_82XX 0x800000
4597 #define OPTROM_SIZE_83XX 0x1000000
4598
4599 #define OPTROM_BURST_SIZE 0x1000
4600 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
4601
4602 #define QLA_DSDS_PER_IOCB 37
4603
4604 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
4605
4606 #define QLA_SG_ALL 1024
4607
4608 enum nexus_wait_type {
4609 WAIT_HOST = 0,
4610 WAIT_TARGET,
4611 WAIT_LUN,
4612 };
4613
4614 /* Refer to SNIA SFF 8247 */
4615 struct sff_8247_a0 {
4616 u8 txid; /* transceiver id */
4617 u8 ext_txid;
4618 u8 connector;
4619 /* compliance code */
4620 u8 eth_infi_cc3; /* ethernet, inifiband */
4621 u8 sonet_cc4[2];
4622 u8 eth_cc6;
4623 /* link length */
4624 #define FC_LL_VL BIT_7 /* very long */
4625 #define FC_LL_S BIT_6 /* Short */
4626 #define FC_LL_I BIT_5 /* Intermidiate*/
4627 #define FC_LL_L BIT_4 /* Long */
4628 #define FC_LL_M BIT_3 /* Medium */
4629 #define FC_LL_SA BIT_2 /* ShortWave laser */
4630 #define FC_LL_LC BIT_1 /* LongWave laser */
4631 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */
4632 u8 fc_ll_cc7;
4633 /* FC technology */
4634 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */
4635 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */
4636 #define FC_TEC_SL BIT_5 /* short wave with OFC */
4637 #define FC_TEC_LL BIT_4 /* Longwave Laser */
4638 #define FC_TEC_ACT BIT_3 /* Active cable */
4639 #define FC_TEC_PAS BIT_2 /* Passive cable */
4640 u8 fc_tec_cc8;
4641 /* Transmission Media */
4642 #define FC_MED_TW BIT_7 /* Twin Ax */
4643 #define FC_MED_TP BIT_6 /* Twited Pair */
4644 #define FC_MED_MI BIT_5 /* Min Coax */
4645 #define FC_MED_TV BIT_4 /* Video Coax */
4646 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */
4647 #define FC_MED_M5 BIT_2 /* Multimode, 50um */
4648 #define FC_MED_SM BIT_0 /* Single Mode */
4649 u8 fc_med_cc9;
4650 /* speed FC_SP_12: 12*100M = 1200 MB/s */
4651 #define FC_SP_12 BIT_7
4652 #define FC_SP_8 BIT_6
4653 #define FC_SP_16 BIT_5
4654 #define FC_SP_4 BIT_4
4655 #define FC_SP_32 BIT_3
4656 #define FC_SP_2 BIT_2
4657 #define FC_SP_1 BIT_0
4658 u8 fc_sp_cc10;
4659 u8 encode;
4660 u8 bitrate;
4661 u8 rate_id;
4662 u8 length_km; /* offset 14/eh */
4663 u8 length_100m;
4664 u8 length_50um_10m;
4665 u8 length_62um_10m;
4666 u8 length_om4_10m;
4667 u8 length_om3_10m;
4668 #define SFF_VEN_NAME_LEN 16
4669 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */
4670 u8 tx_compat;
4671 u8 vendor_oui[3];
4672 #define SFF_PART_NAME_LEN 16
4673 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */
4674 u8 vendor_rev[4];
4675 u8 wavelength[2];
4676 u8 resv;
4677 u8 cc_base;
4678 u8 options[2]; /* offset 64 */
4679 u8 br_max;
4680 u8 br_min;
4681 u8 vendor_sn[16];
4682 u8 date_code[8];
4683 u8 diag;
4684 u8 enh_options;
4685 u8 sff_revision;
4686 u8 cc_ext;
4687 u8 vendor_specific[32];
4688 u8 resv2[128];
4689 };
4690
4691 #define AUTO_DETECT_SFP_SUPPORT(_vha)\
4692 (ql2xautodetectsfp && !_vha->vp_idx && \
4693 (IS_QLA25XX(_vha->hw) || IS_QLA81XX(_vha->hw) ||\
4694 IS_QLA83XX(_vha->hw) || IS_QLA27XX(_vha->hw)))
4695
4696 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
4697 (IS_QLA27XX(_ha) || IS_QLA83XX(_ha)))
4698
4699 #define SAVE_TOPO(_ha) { \
4700 if (_ha->current_topology) \
4701 _ha->prev_topology = _ha->current_topology; \
4702 }
4703
4704 #define N2N_TOPO(ha) \
4705 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \
4706 ha->current_topology == ISP_CFG_N || \
4707 !ha->current_topology)
4708
4709 #include "qla_target.h"
4710 #include "qla_gbl.h"
4711 #include "qla_dbg.h"
4712 #include "qla_inline.h"
4713 #endif
Linux with added FPC-III support