arch/arc/boot/dts/nsimosci_hs_idu.dts

   1 /*
   2  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 /include/ "skeleton_hs_idu.dtsi"
  11
  12 / {
  13         model = "snps,nsimosci_hs-smp";
  14         compatible = "snps,nsimosci_hs";
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17         interrupt-parent = <&core_intc>;
  18
  19         chosen {
  20                 /* this is for console on serial */
  21                 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24 print-fatal-signals=1";
  22         };
  23
  24         aliases {
  25                 serial0 = &uart0;
  26         };
  27
  28         fpga {
  29                 compatible = "simple-bus";
  30                 #address-cells = <1>;
  31                 #size-cells = <1>;
  32
  33                 /* child and parent address space 1:1 mapped */
  34                 ranges;
  35
  36                 core_clk: core_clk {
  37                         #clock-cells = <0>;
  38                         compatible = "fixed-clock";
  39                         clock-frequency = <5000000>;
  40                 };
  41
  42                 core_intc: core-interrupt-controller {
  43                         compatible = "snps,archs-intc";
  44                         interrupt-controller;
  45                         #interrupt-cells = <1>;
  46                 };
  47
  48                 idu_intc: idu-interrupt-controller {
  49                         compatible = "snps,archs-idu-intc";
  50                         interrupt-controller;
  51                         interrupt-parent = <&core_intc>;
  52                         #interrupt-cells = <1>;
  53                 };
  54
  55                 uart0: serial@f0000000 {
  56                         compatible = "ns8250";
  57                         reg = <0xf0000000 0x2000>;
  58                         interrupt-parent = <&idu_intc>;
  59                         interrupts = <0>;
  60                         clock-frequency = <3686400>;
  61                         baud = <115200>;
  62                         reg-shift = <2>;
  63                         reg-io-width = <4>;
  64                         no-loopback-test = <1>;
  65                 };
  66
  67                 pguclk: pguclk {
  68                         #clock-cells = <0>;
  69                         compatible = "fixed-clock";
  70                         clock-frequency = <25175000>;
  71                 };
  72
  73                 pgu@f9000000 {
  74                         compatible = "snps,arcpgu";
  75                         reg = <0xf9000000 0x400>;
  76                         clocks = <&pguclk>;
  77                         clock-names = "pxlclk";
  78                 };
  79
  80                 ps2: ps2@f9001000 {
  81                         compatible = "snps,arc_ps2";
  82                         reg = <0xf9000400 0x14>;
  83                         interrupts = <3>;
  84                         interrupt-parent = <&idu_intc>;
  85                         interrupt-names = "arc_ps2_irq";
  86                 };
  87
  88                 eth0: ethernet@f0003000 {
  89                         compatible = "ezchip,nps-mgt-enet";
  90                         reg = <0xf0003000 0x44>;
  91                         interrupt-parent = <&idu_intc>;
  92                         interrupts = <1>;
  93                 };
  94
  95                 arcpct0: pct {
  96                         compatible = "snps,archs-pct";
  97                         #interrupt-cells = <1>;
  98                         interrupts = <20>;
  99                 };
 100         };
 101 };