arch/arc/include/asm/cache.h

   1 /*
   2  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #ifndef __ARC_ASM_CACHE_H
  10 #define __ARC_ASM_CACHE_H
  11
  12 /* In case $$ not config, setup a dummy number for rest of kernel */
  13 #ifndef CONFIG_ARC_CACHE_LINE_SHIFT
  14 #define L1_CACHE_SHIFT          6
  15 #else
  16 #define L1_CACHE_SHIFT          CONFIG_ARC_CACHE_LINE_SHIFT
  17 #endif
  18
  19 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
  20 #define CACHE_LINE_MASK         (~(L1_CACHE_BYTES - 1))
  21
  22 /*
  23  * ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF)
  24  * Ideal for wiring memory mapped peripherals as we don't need to do
  25  * explicit uncached accesses (LD.di/ST.di) hence more portable drivers
  26  */
  27 #define ARC_UNCACHED_ADDR_SPACE 0xc0000000
  28
  29 #ifndef __ASSEMBLY__
  30
  31 /* Uncached access macros */
  32 #define arc_read_uncached_32(ptr)       \
  33 ({                                      \
  34         unsigned int __ret;             \
  35         __asm__ __volatile__(           \
  36         "       ld.di %0, [%1]  \n"     \
  37         : "=r"(__ret)                   \
  38         : "r"(ptr));                    \
  39         __ret;                          \
  40 })
  41
  42 #define arc_write_uncached_32(ptr, data)\
  43 ({                                      \
  44         __asm__ __volatile__(           \
  45         "       st.di %0, [%1]  \n"     \
  46         :                               \
  47         : "r"(data), "r"(ptr));         \
  48 })
  49
  50 /* Largest line length for either L1 or L2 is 128 bytes */
  51 #define SMP_CACHE_BYTES         128
  52 #define cache_line_size()       SMP_CACHE_BYTES
  53 #define ARCH_DMA_MINALIGN       SMP_CACHE_BYTES
  54
  55 /*
  56  * Make sure slab-allocated buffers are 64-bit aligned when atomic64_t uses
  57  * ARCv2 64-bit atomics (LLOCKD/SCONDD). This guarantess runtime 64-bit
  58  * alignment for any atomic64_t embedded in buffer.
  59  * Default ARCH_SLAB_MINALIGN is __alignof__(long long) which has a relaxed
  60  * value of 4 (and not 8) in ARC ABI.
  61  */
  62 #if defined(CONFIG_ARC_HAS_LL64) && defined(CONFIG_ARC_HAS_LLSC)
  63 #define ARCH_SLAB_MINALIGN      8
  64 #endif
  65
  66 extern void arc_cache_init(void);
  67 extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
  68 extern void read_decode_cache_bcr(void);
  69
  70 extern int ioc_enable;
  71 extern unsigned long perip_base, perip_end;
  72
  73 #endif  /* !__ASSEMBLY__ */
  74
  75 /* Instruction cache related Auxiliary registers */
  76 #define ARC_REG_IC_BCR          0x77    /* Build Config reg */
  77 #define ARC_REG_IC_IVIC         0x10
  78 #define ARC_REG_IC_CTRL         0x11
  79 #define ARC_REG_IC_IVIR         0x16
  80 #define ARC_REG_IC_ENDR         0x17
  81 #define ARC_REG_IC_IVIL         0x19
  82 #define ARC_REG_IC_PTAG         0x1E
  83 #define ARC_REG_IC_PTAG_HI      0x1F
  84
  85 /* Bit val in IC_CTRL */
  86 #define IC_CTRL_DIS             0x1
  87
  88 /* Data cache related Auxiliary registers */
  89 #define ARC_REG_DC_BCR          0x72    /* Build Config reg */
  90 #define ARC_REG_DC_IVDC         0x47
  91 #define ARC_REG_DC_CTRL         0x48
  92 #define ARC_REG_DC_IVDL         0x4A
  93 #define ARC_REG_DC_FLSH         0x4B
  94 #define ARC_REG_DC_FLDL         0x4C
  95 #define ARC_REG_DC_STARTR       0x4D
  96 #define ARC_REG_DC_ENDR         0x4E
  97 #define ARC_REG_DC_PTAG         0x5C
  98 #define ARC_REG_DC_PTAG_HI      0x5F
  99
 100 /* Bit val in DC_CTRL */
 101 #define DC_CTRL_DIS             0x001
 102 #define DC_CTRL_INV_MODE_FLUSH  0x040
 103 #define DC_CTRL_FLUSH_STATUS    0x100
 104 #define DC_CTRL_RGN_OP_INV      0x200
 105 #define DC_CTRL_RGN_OP_MSK      0x200
 106
 107 /*System-level cache (L2 cache) related Auxiliary registers */
 108 #define ARC_REG_SLC_CFG         0x901
 109 #define ARC_REG_SLC_CTRL        0x903
 110 #define ARC_REG_SLC_FLUSH       0x904
 111 #define ARC_REG_SLC_INVALIDATE  0x905
 112 #define ARC_AUX_SLC_IVDL        0x910
 113 #define ARC_AUX_SLC_FLDL        0x912
 114 #define ARC_REG_SLC_RGN_START   0x914
 115 #define ARC_REG_SLC_RGN_START1  0x915
 116 #define ARC_REG_SLC_RGN_END     0x916
 117 #define ARC_REG_SLC_RGN_END1    0x917
 118
 119 /* Bit val in SLC_CONTROL */
 120 #define SLC_CTRL_DIS            0x001
 121 #define SLC_CTRL_IM             0x040
 122 #define SLC_CTRL_BUSY           0x100
 123 #define SLC_CTRL_RGN_OP_INV     0x200
 124
 125 /* IO coherency related Auxiliary registers */
 126 #define ARC_REG_IO_COH_ENABLE   0x500
 127 #define ARC_IO_COH_ENABLE_BIT   BIT(0)
 128 #define ARC_REG_IO_COH_PARTIAL  0x501
 129 #define ARC_IO_COH_PARTIAL_BIT  BIT(0)
 130 #define ARC_REG_IO_COH_AP0_BASE 0x508
 131 #define ARC_REG_IO_COH_AP0_SIZE 0x509
 132
 133 #endif /* _ASM_CACHE_H */