| blob | 697ea05107298bf145453f267f6bb4d1c385a10d |
1 # SPDX-License-Identifier: GPL-2.0-only
2 config ARM64
3 def_bool y
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_CLOCKSOURCE_DATA
13 select ARCH_HAS_DEBUG_VIRTUAL
14 select ARCH_HAS_DEVMEM_IS_ALLOWED
15 select ARCH_HAS_DMA_COHERENT_TO_PFN
16 select ARCH_HAS_DMA_MMAP_PGPROT
17 select ARCH_HAS_DMA_PREP_COHERENT
18 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
19 select ARCH_HAS_ELF_RANDOMIZE
20 select ARCH_HAS_FAST_MULTIPLIER
21 select ARCH_HAS_FORTIFY_SOURCE
22 select ARCH_HAS_GCOV_PROFILE_ALL
23 select ARCH_HAS_GIGANTIC_PAGE
24 select ARCH_HAS_KCOV
25 select ARCH_HAS_KEEPINITRD
26 select ARCH_HAS_MEMBARRIER_SYNC_CORE
27 select ARCH_HAS_PTE_SPECIAL
28 select ARCH_HAS_SETUP_DMA_OPS
29 select ARCH_HAS_SET_MEMORY
30 select ARCH_HAS_STRICT_KERNEL_RWX
31 select ARCH_HAS_STRICT_MODULE_RWX
32 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
33 select ARCH_HAS_SYNC_DMA_FOR_CPU
34 select ARCH_HAS_SYSCALL_WRAPPER
35 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
36 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
37 select ARCH_HAVE_NMI_SAFE_CMPXCHG
38 select ARCH_INLINE_READ_LOCK if !PREEMPT
39 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
40 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
41 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
42 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
43 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
44 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
45 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
46 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
47 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
48 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
49 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
50 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
51 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
52 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
53 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
54 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
55 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
56 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
57 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
58 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
59 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
60 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
61 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
62 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
63 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
64 select ARCH_KEEP_MEMBLOCK
65 select ARCH_USE_CMPXCHG_LOCKREF
66 select ARCH_USE_QUEUED_RWLOCKS
67 select ARCH_USE_QUEUED_SPINLOCKS
68 select ARCH_SUPPORTS_MEMORY_FAILURE
69 select ARCH_SUPPORTS_ATOMIC_RMW
70 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
71 select ARCH_SUPPORTS_NUMA_BALANCING
72 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
73 select ARCH_WANT_FRAME_POINTERS
74 select ARCH_HAS_UBSAN_SANITIZE_ALL
75 select ARM_AMBA
76 select ARM_ARCH_TIMER
77 select ARM_GIC
78 select AUDIT_ARCH_COMPAT_GENERIC
79 select ARM_GIC_V2M if PCI
80 select ARM_GIC_V3
81 select ARM_GIC_V3_ITS if PCI
82 select ARM_PSCI_FW
83 select BUILDTIME_EXTABLE_SORT
84 select CLONE_BACKWARDS
85 select COMMON_CLK
86 select CPU_PM if (SUSPEND || CPU_IDLE)
87 select CRC32
88 select DCACHE_WORD_ACCESS
89 select DMA_DIRECT_REMAP
90 select EDAC_SUPPORT
91 select FRAME_POINTER
92 select GENERIC_ALLOCATOR
93 select GENERIC_ARCH_TOPOLOGY
94 select GENERIC_CLOCKEVENTS
95 select GENERIC_CLOCKEVENTS_BROADCAST
96 select GENERIC_CPU_AUTOPROBE
97 select GENERIC_CPU_VULNERABILITIES
98 select GENERIC_EARLY_IOREMAP
99 select GENERIC_IDLE_POLL_SETUP
100 select GENERIC_IRQ_MULTI_HANDLER
101 select GENERIC_IRQ_PROBE
102 select GENERIC_IRQ_SHOW
103 select GENERIC_IRQ_SHOW_LEVEL
104 select GENERIC_PCI_IOMAP
105 select GENERIC_SCHED_CLOCK
106 select GENERIC_SMP_IDLE_THREAD
107 select GENERIC_STRNCPY_FROM_USER
108 select GENERIC_STRNLEN_USER
109 select GENERIC_TIME_VSYSCALL
110 select HANDLE_DOMAIN_IRQ
111 select HARDIRQS_SW_RESEND
112 select HAVE_PCI
113 select HAVE_ACPI_APEI if (ACPI && EFI)
114 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
115 select HAVE_ARCH_AUDITSYSCALL
116 select HAVE_ARCH_BITREVERSE
117 select HAVE_ARCH_HUGE_VMAP
118 select HAVE_ARCH_JUMP_LABEL
119 select HAVE_ARCH_JUMP_LABEL_RELATIVE
120 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
121 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
122 select HAVE_ARCH_KGDB
123 select HAVE_ARCH_MMAP_RND_BITS
124 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
125 select HAVE_ARCH_PREL32_RELOCATIONS
126 select HAVE_ARCH_SECCOMP_FILTER
127 select HAVE_ARCH_STACKLEAK
128 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
129 select HAVE_ARCH_TRACEHOOK
130 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
131 select HAVE_ARCH_VMAP_STACK
132 select HAVE_ARM_SMCCC
133 select HAVE_EBPF_JIT
134 select HAVE_C_RECORDMCOUNT
135 select HAVE_CMPXCHG_DOUBLE
136 select HAVE_CMPXCHG_LOCAL
137 select HAVE_CONTEXT_TRACKING
138 select HAVE_DEBUG_BUGVERBOSE
139 select HAVE_DEBUG_KMEMLEAK
140 select HAVE_DMA_CONTIGUOUS
141 select HAVE_DYNAMIC_FTRACE
142 select HAVE_EFFICIENT_UNALIGNED_ACCESS
143 select HAVE_FTRACE_MCOUNT_RECORD
144 select HAVE_FUNCTION_TRACER
145 select HAVE_FUNCTION_GRAPH_TRACER
146 select HAVE_GCC_PLUGINS
147 select HAVE_HW_BREAKPOINT if PERF_EVENTS
148 select HAVE_IRQ_TIME_ACCOUNTING
149 select HAVE_MEMBLOCK_NODE_MAP if NUMA
150 select HAVE_NMI
151 select HAVE_PATA_PLATFORM
152 select HAVE_PERF_EVENTS
153 select HAVE_PERF_REGS
154 select HAVE_PERF_USER_STACK_DUMP
155 select HAVE_REGS_AND_STACK_ACCESS_API
156 select HAVE_FUNCTION_ARG_ACCESS_API
157 select HAVE_RCU_TABLE_FREE
158 select HAVE_RSEQ
159 select HAVE_STACKPROTECTOR
160 select HAVE_SYSCALL_TRACEPOINTS
161 select HAVE_KPROBES
162 select HAVE_KRETPROBES
163 select IOMMU_DMA if IOMMU_SUPPORT
164 select IRQ_DOMAIN
165 select IRQ_FORCED_THREADING
166 select MODULES_USE_ELF_RELA
167 select NEED_DMA_MAP_STATE
168 select NEED_SG_DMA_LENGTH
169 select OF
170 select OF_EARLY_FLATTREE
171 select PCI_DOMAINS_GENERIC if PCI
172 select PCI_ECAM if (ACPI && PCI)
173 select PCI_SYSCALL if PCI
174 select POWER_RESET
175 select POWER_SUPPLY
176 select REFCOUNT_FULL
177 select SPARSE_IRQ
178 select SWIOTLB
179 select SYSCTL_EXCEPTION_TRACE
180 select THREAD_INFO_IN_TASK
181 help
182 ARM 64-bit (AArch64) Linux support.
184 config 64BIT
185 def_bool y
187 config MMU
188 def_bool y
190 config ARM64_PAGE_SHIFT
191 int
192 default 16 if ARM64_64K_PAGES
193 default 14 if ARM64_16K_PAGES
194 default 12
196 config ARM64_CONT_SHIFT
197 int
198 default 5 if ARM64_64K_PAGES
199 default 7 if ARM64_16K_PAGES
200 default 4
202 config ARCH_MMAP_RND_BITS_MIN
203 default 14 if ARM64_64K_PAGES
204 default 16 if ARM64_16K_PAGES
205 default 18
207 # max bits determined by the following formula:
208 # VA_BITS - PAGE_SHIFT - 3
209 config ARCH_MMAP_RND_BITS_MAX
210 default 19 if ARM64_VA_BITS=36
211 default 24 if ARM64_VA_BITS=39
212 default 27 if ARM64_VA_BITS=42
213 default 30 if ARM64_VA_BITS=47
214 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
215 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
216 default 33 if ARM64_VA_BITS=48
217 default 14 if ARM64_64K_PAGES
218 default 16 if ARM64_16K_PAGES
219 default 18
221 config ARCH_MMAP_RND_COMPAT_BITS_MIN
222 default 7 if ARM64_64K_PAGES
223 default 9 if ARM64_16K_PAGES
224 default 11
226 config ARCH_MMAP_RND_COMPAT_BITS_MAX
227 default 16
229 config NO_IOPORT_MAP
230 def_bool y if !PCI
232 config STACKTRACE_SUPPORT
233 def_bool y
235 config ILLEGAL_POINTER_VALUE
236 hex
237 default 0xdead000000000000
239 config LOCKDEP_SUPPORT
240 def_bool y
242 config TRACE_IRQFLAGS_SUPPORT
243 def_bool y
245 config GENERIC_BUG
246 def_bool y
247 depends on BUG
249 config GENERIC_BUG_RELATIVE_POINTERS
250 def_bool y
251 depends on GENERIC_BUG
253 config GENERIC_HWEIGHT
254 def_bool y
256 config GENERIC_CSUM
257 def_bool y
259 config GENERIC_CALIBRATE_DELAY
260 def_bool y
262 config ZONE_DMA32
263 def_bool y
265 config HAVE_GENERIC_GUP
266 def_bool y
268 config ARCH_ENABLE_MEMORY_HOTPLUG
269 def_bool y
271 config SMP
272 def_bool y
274 config KERNEL_MODE_NEON
275 def_bool y
277 config FIX_EARLYCON_MEM
278 def_bool y
280 config PGTABLE_LEVELS
281 int
282 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
283 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
284 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52)
285 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
286 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
287 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
289 config ARCH_SUPPORTS_UPROBES
290 def_bool y
292 config ARCH_PROC_KCORE_TEXT
293 def_bool y
295 source "arch/arm64/Kconfig.platforms"
297 menu "Kernel Features"
299 menu "ARM errata workarounds via the alternatives framework"
301 config ARM64_WORKAROUND_CLEAN_CACHE
302 bool
304 config ARM64_ERRATUM_826319
305 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
306 default y
307 select ARM64_WORKAROUND_CLEAN_CACHE
308 help
309 This option adds an alternative code sequence to work around ARM
310 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
311 AXI master interface and an L2 cache.
313 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
314 and is unable to accept a certain write via this interface, it will
315 not progress on read data presented on the read data channel and the
316 system can deadlock.
318 The workaround promotes data cache clean instructions to
319 data cache clean-and-invalidate.
320 Please note that this does not necessarily enable the workaround,
321 as it depends on the alternative framework, which will only patch
322 the kernel if an affected CPU is detected.
324 If unsure, say Y.
326 config ARM64_ERRATUM_827319
327 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
328 default y
329 select ARM64_WORKAROUND_CLEAN_CACHE
330 help
331 This option adds an alternative code sequence to work around ARM
332 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
333 master interface and an L2 cache.
335 Under certain conditions this erratum can cause a clean line eviction
336 to occur at the same time as another transaction to the same address
337 on the AMBA 5 CHI interface, which can cause data corruption if the
338 interconnect reorders the two transactions.
340 The workaround promotes data cache clean instructions to
341 data cache clean-and-invalidate.
342 Please note that this does not necessarily enable the workaround,
343 as it depends on the alternative framework, which will only patch
344 the kernel if an affected CPU is detected.
346 If unsure, say Y.
348 config ARM64_ERRATUM_824069
349 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
350 default y
351 select ARM64_WORKAROUND_CLEAN_CACHE
352 help
353 This option adds an alternative code sequence to work around ARM
354 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
355 to a coherent interconnect.
357 If a Cortex-A53 processor is executing a store or prefetch for
358 write instruction at the same time as a processor in another
359 cluster is executing a cache maintenance operation to the same
360 address, then this erratum might cause a clean cache line to be
361 incorrectly marked as dirty.
363 The workaround promotes data cache clean instructions to
364 data cache clean-and-invalidate.
365 Please note that this option does not necessarily enable the
366 workaround, as it depends on the alternative framework, which will
367 only patch the kernel if an affected CPU is detected.
369 If unsure, say Y.
371 config ARM64_ERRATUM_819472
372 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
373 default y
374 select ARM64_WORKAROUND_CLEAN_CACHE
375 help
376 This option adds an alternative code sequence to work around ARM
377 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
378 present when it is connected to a coherent interconnect.
380 If the processor is executing a load and store exclusive sequence at
381 the same time as a processor in another cluster is executing a cache
382 maintenance operation to the same address, then this erratum might
383 cause data corruption.
385 The workaround promotes data cache clean instructions to
386 data cache clean-and-invalidate.
387 Please note that this does not necessarily enable the workaround,
388 as it depends on the alternative framework, which will only patch
389 the kernel if an affected CPU is detected.
391 If unsure, say Y.
393 config ARM64_ERRATUM_832075
394 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
395 default y
396 help
397 This option adds an alternative code sequence to work around ARM
398 erratum 832075 on Cortex-A57 parts up to r1p2.
400 Affected Cortex-A57 parts might deadlock when exclusive load/store
401 instructions to Write-Back memory are mixed with Device loads.
403 The workaround is to promote device loads to use Load-Acquire
404 semantics.
405 Please note that this does not necessarily enable the workaround,
406 as it depends on the alternative framework, which will only patch
407 the kernel if an affected CPU is detected.
409 If unsure, say Y.
411 config ARM64_ERRATUM_834220
412 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
413 depends on KVM
414 default y
415 help
416 This option adds an alternative code sequence to work around ARM
417 erratum 834220 on Cortex-A57 parts up to r1p2.
419 Affected Cortex-A57 parts might report a Stage 2 translation
420 fault as the result of a Stage 1 fault for load crossing a
421 page boundary when there is a permission or device memory
422 alignment fault at Stage 1 and a translation fault at Stage 2.
424 The workaround is to verify that the Stage 1 translation
425 doesn't generate a fault before handling the Stage 2 fault.
426 Please note that this does not necessarily enable the workaround,
427 as it depends on the alternative framework, which will only patch
428 the kernel if an affected CPU is detected.
430 If unsure, say Y.
432 config ARM64_ERRATUM_845719
433 bool "Cortex-A53: 845719: a load might read incorrect data"
434 depends on COMPAT
435 default y
436 help
437 This option adds an alternative code sequence to work around ARM
438 erratum 845719 on Cortex-A53 parts up to r0p4.
440 When running a compat (AArch32) userspace on an affected Cortex-A53
441 part, a load at EL0 from a virtual address that matches the bottom 32
442 bits of the virtual address used by a recent load at (AArch64) EL1
443 might return incorrect data.
445 The workaround is to write the contextidr_el1 register on exception
446 return to a 32-bit task.
447 Please note that this does not necessarily enable the workaround,
448 as it depends on the alternative framework, which will only patch
449 the kernel if an affected CPU is detected.
451 If unsure, say Y.
453 config ARM64_ERRATUM_843419
454 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
455 default y
456 select ARM64_MODULE_PLTS if MODULES
457 help
458 This option links the kernel with '--fix-cortex-a53-843419' and
459 enables PLT support to replace certain ADRP instructions, which can
460 cause subsequent memory accesses to use an incorrect address on
461 Cortex-A53 parts up to r0p4.
463 If unsure, say Y.
465 config ARM64_ERRATUM_1024718
466 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
467 default y
468 help
469 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
471 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
472 update of the hardware dirty bit when the DBM/AP bits are updated
473 without a break-before-make. The workaround is to disable the usage
474 of hardware DBM locally on the affected cores. CPUs not affected by
475 this erratum will continue to use the feature.
477 If unsure, say Y.
479 config ARM64_ERRATUM_1418040
480 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
481 default y
482 depends on COMPAT
483 help
484 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
485 errata 1188873 and 1418040.
487 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
488 cause register corruption when accessing the timer registers
489 from AArch32 userspace.
491 If unsure, say Y.
493 config ARM64_ERRATUM_1165522
494 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
495 default y
496 help
497 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
499 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
500 corrupted TLBs by speculating an AT instruction during a guest
501 context switch.
503 If unsure, say Y.
505 config ARM64_ERRATUM_1286807
506 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
507 default y
508 select ARM64_WORKAROUND_REPEAT_TLBI
509 help
510 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
512 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
513 address for a cacheable mapping of a location is being
514 accessed by a core while another core is remapping the virtual
515 address to a new physical page using the recommended
516 break-before-make sequence, then under very rare circumstances
517 TLBI+DSB completes before a read using the translation being
518 invalidated has been observed by other observers. The
519 workaround repeats the TLBI+DSB operation.
521 If unsure, say Y.
523 config ARM64_ERRATUM_1463225
524 bool "Cortex-A76: Software Step might prevent interrupt recognition"
525 default y
526 help
527 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
529 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
530 of a system call instruction (SVC) can prevent recognition of
531 subsequent interrupts when software stepping is disabled in the
532 exception handler of the system call and either kernel debugging
533 is enabled or VHE is in use.
535 Work around the erratum by triggering a dummy step exception
536 when handling a system call from a task that is being stepped
537 in a VHE configuration of the kernel.
539 If unsure, say Y.
541 config CAVIUM_ERRATUM_22375
542 bool "Cavium erratum 22375, 24313"
543 default y
544 help
545 Enable workaround for errata 22375 and 24313.
547 This implements two gicv3-its errata workarounds for ThunderX. Both
548 with a small impact affecting only ITS table allocation.
550 erratum 22375: only alloc 8MB table size
551 erratum 24313: ignore memory access type
553 The fixes are in ITS initialization and basically ignore memory access
554 type and table size provided by the TYPER and BASER registers.
556 If unsure, say Y.
558 config CAVIUM_ERRATUM_23144
559 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
560 depends on NUMA
561 default y
562 help
563 ITS SYNC command hang for cross node io and collections/cpu mapping.
565 If unsure, say Y.
567 config CAVIUM_ERRATUM_23154
568 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
569 default y
570 help
571 The gicv3 of ThunderX requires a modified version for
572 reading the IAR status to ensure data synchronization
573 (access to icc_iar1_el1 is not sync'ed before and after).
575 If unsure, say Y.
577 config CAVIUM_ERRATUM_27456
578 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
579 default y
580 help
581 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
582 instructions may cause the icache to become corrupted if it
583 contains data for a non-current ASID. The fix is to
584 invalidate the icache when changing the mm context.
586 If unsure, say Y.
588 config CAVIUM_ERRATUM_30115
589 bool "Cavium erratum 30115: Guest may disable interrupts in host"
590 default y
591 help
592 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
593 1.2, and T83 Pass 1.0, KVM guest execution may disable
594 interrupts in host. Trapping both GICv3 group-0 and group-1
595 accesses sidesteps the issue.
597 If unsure, say Y.
599 config QCOM_FALKOR_ERRATUM_1003
600 bool "Falkor E1003: Incorrect translation due to ASID change"
601 default y
602 help
603 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
604 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
605 in TTBR1_EL1, this situation only occurs in the entry trampoline and
606 then only for entries in the walk cache, since the leaf translation
607 is unchanged. Work around the erratum by invalidating the walk cache
608 entries for the trampoline before entering the kernel proper.
610 config ARM64_WORKAROUND_REPEAT_TLBI
611 bool
613 config QCOM_FALKOR_ERRATUM_1009
614 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
615 default y
616 select ARM64_WORKAROUND_REPEAT_TLBI
617 help
618 On Falkor v1, the CPU may prematurely complete a DSB following a
619 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
620 one more time to fix the issue.
622 If unsure, say Y.
624 config QCOM_QDF2400_ERRATUM_0065
625 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
626 default y
627 help
628 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
629 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
630 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
632 If unsure, say Y.
634 config SOCIONEXT_SYNQUACER_PREITS
635 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
636 default y
637 help
638 Socionext Synquacer SoCs implement a separate h/w block to generate
639 MSI doorbell writes with non-zero values for the device ID.
641 If unsure, say Y.
643 config HISILICON_ERRATUM_161600802
644 bool "Hip07 161600802: Erroneous redistributor VLPI base"
645 default y
646 help
647 The HiSilicon Hip07 SoC uses the wrong redistributor base
648 when issued ITS commands such as VMOVP and VMAPP, and requires
649 a 128kB offset to be applied to the target address in this commands.
651 If unsure, say Y.
653 config QCOM_FALKOR_ERRATUM_E1041
654 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
655 default y
656 help
657 Falkor CPU may speculatively fetch instructions from an improper
658 memory location when MMU translation is changed from SCTLR_ELn[M]=1
659 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
661 If unsure, say Y.
663 config FUJITSU_ERRATUM_010001
664 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
665 default y
666 help
667 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
668 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
669 accesses may cause undefined fault (Data abort, DFSC=0b111111).
670 This fault occurs under a specific hardware condition when a
671 load/store instruction performs an address translation using:
672 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
673 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
674 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
675 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
677 The workaround is to ensure these bits are clear in TCR_ELx.
678 The workaround only affects the Fujitsu-A64FX.
680 If unsure, say Y.
682 endmenu
685 choice
686 prompt "Page size"
687 default ARM64_4K_PAGES
688 help
689 Page size (translation granule) configuration.
691 config ARM64_4K_PAGES
692 bool "4KB"
693 help
694 This feature enables 4KB pages support.
696 config ARM64_16K_PAGES
697 bool "16KB"
698 help
699 The system will use 16KB pages support. AArch32 emulation
700 requires applications compiled with 16K (or a multiple of 16K)
701 aligned segments.
703 config ARM64_64K_PAGES
704 bool "64KB"
705 help
706 This feature enables 64KB pages support (4KB by default)
707 allowing only two levels of page tables and faster TLB
708 look-up. AArch32 emulation requires applications compiled
709 with 64K aligned segments.
711 endchoice
713 choice
714 prompt "Virtual address space size"
715 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
716 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
717 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
718 help
719 Allows choosing one of multiple possible virtual address
720 space sizes. The level of translation table is determined by
721 a combination of page size and virtual address space size.
723 config ARM64_VA_BITS_36
724 bool "36-bit" if EXPERT
725 depends on ARM64_16K_PAGES
727 config ARM64_VA_BITS_39
728 bool "39-bit"
729 depends on ARM64_4K_PAGES
731 config ARM64_VA_BITS_42
732 bool "42-bit"
733 depends on ARM64_64K_PAGES
735 config ARM64_VA_BITS_47
736 bool "47-bit"
737 depends on ARM64_16K_PAGES
739 config ARM64_VA_BITS_48
740 bool "48-bit"
742 config ARM64_USER_VA_BITS_52
743 bool "52-bit (user)"
744 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
745 help
746 Enable 52-bit virtual addressing for userspace when explicitly
747 requested via a hint to mmap(). The kernel will continue to
748 use 48-bit virtual addresses for its own mappings.
750 NOTE: Enabling 52-bit virtual addressing in conjunction with
751 ARMv8.3 Pointer Authentication will result in the PAC being
752 reduced from 7 bits to 3 bits, which may have a significant
753 impact on its susceptibility to brute-force attacks.
755 If unsure, select 48-bit virtual addressing instead.
757 endchoice
759 config ARM64_FORCE_52BIT
760 bool "Force 52-bit virtual addresses for userspace"
761 depends on ARM64_USER_VA_BITS_52 && EXPERT
762 help
763 For systems with 52-bit userspace VAs enabled, the kernel will attempt
764 to maintain compatibility with older software by providing 48-bit VAs
765 unless a hint is supplied to mmap.
767 This configuration option disables the 48-bit compatibility logic, and
768 forces all userspace addresses to be 52-bit on HW that supports it. One
769 should only enable this configuration option for stress testing userspace
770 memory management code. If unsure say N here.
772 config ARM64_VA_BITS
773 int
774 default 36 if ARM64_VA_BITS_36
775 default 39 if ARM64_VA_BITS_39
776 default 42 if ARM64_VA_BITS_42
777 default 47 if ARM64_VA_BITS_47
778 default 48 if ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52
780 choice
781 prompt "Physical address space size"
782 default ARM64_PA_BITS_48
783 help
784 Choose the maximum physical address range that the kernel will
785 support.
787 config ARM64_PA_BITS_48
788 bool "48-bit"
790 config ARM64_PA_BITS_52
791 bool "52-bit (ARMv8.2)"
792 depends on ARM64_64K_PAGES
793 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
794 help
795 Enable support for a 52-bit physical address space, introduced as
796 part of the ARMv8.2-LPA extension.
798 With this enabled, the kernel will also continue to work on CPUs that
799 do not support ARMv8.2-LPA, but with some added memory overhead (and
800 minor performance overhead).
802 endchoice
804 config ARM64_PA_BITS
805 int
806 default 48 if ARM64_PA_BITS_48
807 default 52 if ARM64_PA_BITS_52
809 config CPU_BIG_ENDIAN
810 bool "Build big-endian kernel"
811 help
812 Say Y if you plan on running a kernel in big-endian mode.
814 config SCHED_MC
815 bool "Multi-core scheduler support"
816 help
817 Multi-core scheduler support improves the CPU scheduler's decision
818 making when dealing with multi-core CPU chips at a cost of slightly
819 increased overhead in some places. If unsure say N here.
821 config SCHED_SMT
822 bool "SMT scheduler support"
823 help
824 Improves the CPU scheduler's decision making when dealing with
825 MultiThreading at a cost of slightly increased overhead in some
826 places. If unsure say N here.
828 config NR_CPUS
829 int "Maximum number of CPUs (2-4096)"
830 range 2 4096
831 default "256"
833 config HOTPLUG_CPU
834 bool "Support for hot-pluggable CPUs"
835 select GENERIC_IRQ_MIGRATION
836 help
837 Say Y here to experiment with turning CPUs off and on. CPUs
838 can be controlled through /sys/devices/system/cpu.
840 # Common NUMA Features
841 config NUMA
842 bool "Numa Memory Allocation and Scheduler Support"
843 select ACPI_NUMA if ACPI
844 select OF_NUMA
845 help
846 Enable NUMA (Non Uniform Memory Access) support.
848 The kernel will try to allocate memory used by a CPU on the
849 local memory of the CPU and add some more
850 NUMA awareness to the kernel.
852 config NODES_SHIFT
853 int "Maximum NUMA Nodes (as a power of 2)"
854 range 1 10
855 default "2"
856 depends on NEED_MULTIPLE_NODES
857 help
858 Specify the maximum number of NUMA Nodes available on the target
859 system. Increases memory reserved to accommodate various tables.
861 config USE_PERCPU_NUMA_NODE_ID
862 def_bool y
863 depends on NUMA
865 config HAVE_SETUP_PER_CPU_AREA
866 def_bool y
867 depends on NUMA
869 config NEED_PER_CPU_EMBED_FIRST_CHUNK
870 def_bool y
871 depends on NUMA
873 config HOLES_IN_ZONE
874 def_bool y
876 source "kernel/Kconfig.hz"
878 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
879 def_bool y
881 config ARCH_SPARSEMEM_ENABLE
882 def_bool y
883 select SPARSEMEM_VMEMMAP_ENABLE
885 config ARCH_SPARSEMEM_DEFAULT
886 def_bool ARCH_SPARSEMEM_ENABLE
888 config ARCH_SELECT_MEMORY_MODEL
889 def_bool ARCH_SPARSEMEM_ENABLE
891 config ARCH_FLATMEM_ENABLE
892 def_bool !NUMA
894 config HAVE_ARCH_PFN_VALID
895 def_bool y
897 config HW_PERF_EVENTS
898 def_bool y
899 depends on ARM_PMU
901 config SYS_SUPPORTS_HUGETLBFS
902 def_bool y
904 config ARCH_WANT_HUGE_PMD_SHARE
905 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
907 config ARCH_HAS_CACHE_LINE_SIZE
908 def_bool y
910 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
911 def_bool y if PGTABLE_LEVELS > 2
913 config SECCOMP
914 bool "Enable seccomp to safely compute untrusted bytecode"
915 ---help---
916 This kernel feature is useful for number crunching applications
917 that may need to compute untrusted bytecode during their
918 execution. By using pipes or other transports made available to
919 the process as file descriptors supporting the read/write
920 syscalls, it's possible to isolate those applications in
921 their own address space using seccomp. Once seccomp is
922 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
923 and the task is only allowed to execute a few safe syscalls
924 defined by each seccomp mode.
926 config PARAVIRT
927 bool "Enable paravirtualization code"
928 help
929 This changes the kernel so it can modify itself when it is run
930 under a hypervisor, potentially improving performance significantly
931 over full virtualization.
933 config PARAVIRT_TIME_ACCOUNTING
934 bool "Paravirtual steal time accounting"
935 select PARAVIRT
936 default n
937 help
938 Select this option to enable fine granularity task steal time
939 accounting. Time spent executing other tasks in parallel with
940 the current vCPU is discounted from the vCPU power. To account for
941 that, there can be a small performance impact.
943 If in doubt, say N here.
945 config KEXEC
946 depends on PM_SLEEP_SMP
947 select KEXEC_CORE
948 bool "kexec system call"
949 ---help---
950 kexec is a system call that implements the ability to shutdown your
951 current kernel, and to start another kernel. It is like a reboot
952 but it is independent of the system firmware. And like a reboot
953 you can start any kernel with it, not just Linux.
955 config KEXEC_FILE
956 bool "kexec file based system call"
957 select KEXEC_CORE
958 help
959 This is new version of kexec system call. This system call is
960 file based and takes file descriptors as system call argument
961 for kernel and initramfs as opposed to list of segments as
962 accepted by previous system call.
964 config KEXEC_VERIFY_SIG
965 bool "Verify kernel signature during kexec_file_load() syscall"
966 depends on KEXEC_FILE
967 help
968 Select this option to verify a signature with loaded kernel
969 image. If configured, any attempt of loading a image without
970 valid signature will fail.
972 In addition to that option, you need to enable signature
973 verification for the corresponding kernel image type being
974 loaded in order for this to work.
976 config KEXEC_IMAGE_VERIFY_SIG
977 bool "Enable Image signature verification support"
978 default y
979 depends on KEXEC_VERIFY_SIG
980 depends on EFI && SIGNED_PE_FILE_VERIFICATION
981 help
982 Enable Image signature verification support.
984 comment "Support for PE file signature verification disabled"
985 depends on KEXEC_VERIFY_SIG
986 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
988 config CRASH_DUMP
989 bool "Build kdump crash kernel"
990 help
991 Generate crash dump after being started by kexec. This should
992 be normally only set in special crash dump kernels which are
993 loaded in the main kernel with kexec-tools into a specially
994 reserved region and then later executed after a crash by
995 kdump/kexec.
997 For more details see Documentation/kdump/kdump.txt
999 config XEN_DOM0
1000 def_bool y
1001 depends on XEN
1003 config XEN
1004 bool "Xen guest support on ARM64"
1005 depends on ARM64 && OF
1006 select SWIOTLB_XEN
1007 select PARAVIRT
1008 help
1009 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1011 config FORCE_MAX_ZONEORDER
1012 int
1013 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1014 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1015 default "11"
1016 help
1017 The kernel memory allocator divides physically contiguous memory
1018 blocks into "zones", where each zone is a power of two number of
1019 pages. This option selects the largest power of two that the kernel
1020 keeps in the memory allocator. If you need to allocate very large
1021 blocks of physically contiguous memory, then you may need to
1022 increase this value.
1024 This config option is actually maximum order plus one. For example,
1025 a value of 11 means that the largest free memory block is 2^10 pages.
1027 We make sure that we can allocate upto a HugePage size for each configuration.
1028 Hence we have :
1029 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1031 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1032 4M allocations matching the default size used by generic code.
1034 config UNMAP_KERNEL_AT_EL0
1035 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1036 default y
1037 help
1038 Speculation attacks against some high-performance processors can
1039 be used to bypass MMU permission checks and leak kernel data to
1040 userspace. This can be defended against by unmapping the kernel
1041 when running in userspace, mapping it back in on exception entry
1042 via a trampoline page in the vector table.
1044 If unsure, say Y.
1046 config HARDEN_BRANCH_PREDICTOR
1047 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1048 default y
1049 help
1050 Speculation attacks against some high-performance processors rely on
1051 being able to manipulate the branch predictor for a victim context by
1052 executing aliasing branches in the attacker context. Such attacks
1053 can be partially mitigated against by clearing internal branch
1054 predictor state and limiting the prediction logic in some situations.
1056 This config option will take CPU-specific actions to harden the
1057 branch predictor against aliasing attacks and may rely on specific
1058 instruction sequences or control bits being set by the system
1059 firmware.
1061 If unsure, say Y.
1063 config HARDEN_EL2_VECTORS
1064 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1065 default y
1066 help
1067 Speculation attacks against some high-performance processors can
1068 be used to leak privileged information such as the vector base
1069 register, resulting in a potential defeat of the EL2 layout
1070 randomization.
1072 This config option will map the vectors to a fixed location,
1073 independent of the EL2 code mapping, so that revealing VBAR_EL2
1074 to an attacker does not give away any extra information. This
1075 only gets enabled on affected CPUs.
1077 If unsure, say Y.
1079 config ARM64_SSBD
1080 bool "Speculative Store Bypass Disable" if EXPERT
1081 default y
1082 help
1083 This enables mitigation of the bypassing of previous stores
1084 by speculative loads.
1086 If unsure, say Y.
1088 config RODATA_FULL_DEFAULT_ENABLED
1089 bool "Apply r/o permissions of VM areas also to their linear aliases"
1090 default y
1091 help
1092 Apply read-only attributes of VM areas to the linear alias of
1093 the backing pages as well. This prevents code or read-only data
1094 from being modified (inadvertently or intentionally) via another
1095 mapping of the same memory page. This additional enhancement can
1096 be turned off at runtime by passing rodata=[off|on] (and turned on
1097 with rodata=full if this option is set to 'n')
1099 This requires the linear region to be mapped down to pages,
1100 which may adversely affect performance in some cases.
1102 config ARM64_SW_TTBR0_PAN
1103 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1104 help
1105 Enabling this option prevents the kernel from accessing
1106 user-space memory directly by pointing TTBR0_EL1 to a reserved
1107 zeroed area and reserved ASID. The user access routines
1108 restore the valid TTBR0_EL1 temporarily.
1110 menuconfig COMPAT
1111 bool "Kernel support for 32-bit EL0"
1112 depends on ARM64_4K_PAGES || EXPERT
1113 select COMPAT_BINFMT_ELF if BINFMT_ELF
1114 select HAVE_UID16
1115 select OLD_SIGSUSPEND3
1116 select COMPAT_OLD_SIGACTION
1117 help
1118 This option enables support for a 32-bit EL0 running under a 64-bit
1119 kernel at EL1. AArch32-specific components such as system calls,
1120 the user helper functions, VFP support and the ptrace interface are
1121 handled appropriately by the kernel.
1123 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1124 that you will only be able to execute AArch32 binaries that were compiled
1125 with page size aligned segments.
1127 If you want to execute 32-bit userspace applications, say Y.
1129 if COMPAT
1131 config KUSER_HELPERS
1132 bool "Enable kuser helpers page for 32 bit applications"
1133 default y
1134 help
1135 Warning: disabling this option may break 32-bit user programs.
1137 Provide kuser helpers to compat tasks. The kernel provides
1138 helper code to userspace in read only form at a fixed location
1139 to allow userspace to be independent of the CPU type fitted to
1140 the system. This permits binaries to be run on ARMv4 through
1141 to ARMv8 without modification.
1143 See Documentation/arm/kernel_user_helpers.txt for details.
1145 However, the fixed address nature of these helpers can be used
1146 by ROP (return orientated programming) authors when creating
1147 exploits.
1149 If all of the binaries and libraries which run on your platform
1150 are built specifically for your platform, and make no use of
1151 these helpers, then you can turn this option off to hinder
1152 such exploits. However, in that case, if a binary or library
1153 relying on those helpers is run, it will not function correctly.
1155 Say N here only if you are absolutely certain that you do not
1156 need these helpers; otherwise, the safe option is to say Y.
1159 menuconfig ARMV8_DEPRECATED
1160 bool "Emulate deprecated/obsolete ARMv8 instructions"
1161 depends on SYSCTL
1162 help
1163 Legacy software support may require certain instructions
1164 that have been deprecated or obsoleted in the architecture.
1166 Enable this config to enable selective emulation of these
1167 features.
1169 If unsure, say Y
1171 if ARMV8_DEPRECATED
1173 config SWP_EMULATION
1174 bool "Emulate SWP/SWPB instructions"
1175 help
1176 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1177 they are always undefined. Say Y here to enable software
1178 emulation of these instructions for userspace using LDXR/STXR.
1180 In some older versions of glibc [<=2.8] SWP is used during futex
1181 trylock() operations with the assumption that the code will not
1182 be preempted. This invalid assumption may be more likely to fail
1183 with SWP emulation enabled, leading to deadlock of the user
1184 application.
1186 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1187 on an external transaction monitoring block called a global
1188 monitor to maintain update atomicity. If your system does not
1189 implement a global monitor, this option can cause programs that
1190 perform SWP operations to uncached memory to deadlock.
1192 If unsure, say Y
1194 config CP15_BARRIER_EMULATION
1195 bool "Emulate CP15 Barrier instructions"
1196 help
1197 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1198 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1199 strongly recommended to use the ISB, DSB, and DMB
1200 instructions instead.
1202 Say Y here to enable software emulation of these
1203 instructions for AArch32 userspace code. When this option is
1204 enabled, CP15 barrier usage is traced which can help
1205 identify software that needs updating.
1207 If unsure, say Y
1209 config SETEND_EMULATION
1210 bool "Emulate SETEND instruction"
1211 help
1212 The SETEND instruction alters the data-endianness of the
1213 AArch32 EL0, and is deprecated in ARMv8.
1215 Say Y here to enable software emulation of the instruction
1216 for AArch32 userspace code.
1218 Note: All the cpus on the system must have mixed endian support at EL0
1219 for this feature to be enabled. If a new CPU - which doesn't support mixed
1220 endian - is hotplugged in after this feature has been enabled, there could
1221 be unexpected results in the applications.
1223 If unsure, say Y
1224 endif
1226 endif
1228 menu "ARMv8.1 architectural features"
1230 config ARM64_HW_AFDBM
1231 bool "Support for hardware updates of the Access and Dirty page flags"
1232 default y
1233 help
1234 The ARMv8.1 architecture extensions introduce support for
1235 hardware updates of the access and dirty information in page
1236 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1237 capable processors, accesses to pages with PTE_AF cleared will
1238 set this bit instead of raising an access flag fault.
1239 Similarly, writes to read-only pages with the DBM bit set will
1240 clear the read-only bit (AP[2]) instead of raising a
1241 permission fault.
1243 Kernels built with this configuration option enabled continue
1244 to work on pre-ARMv8.1 hardware and the performance impact is
1245 minimal. If unsure, say Y.
1247 config ARM64_PAN
1248 bool "Enable support for Privileged Access Never (PAN)"
1249 default y
1250 help
1251 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1252 prevents the kernel or hypervisor from accessing user-space (EL0)
1253 memory directly.
1255 Choosing this option will cause any unprotected (not using
1256 copy_to_user et al) memory access to fail with a permission fault.
1258 The feature is detected at runtime, and will remain as a 'nop'
1259 instruction if the cpu does not implement the feature.
1261 config ARM64_LSE_ATOMICS
1262 bool "Atomic instructions"
1263 default y
1264 help
1265 As part of the Large System Extensions, ARMv8.1 introduces new
1266 atomic instructions that are designed specifically to scale in
1267 very large systems.
1269 Say Y here to make use of these instructions for the in-kernel
1270 atomic routines. This incurs a small overhead on CPUs that do
1271 not support these instructions and requires the kernel to be
1272 built with binutils >= 2.25 in order for the new instructions
1273 to be used.
1275 config ARM64_VHE
1276 bool "Enable support for Virtualization Host Extensions (VHE)"
1277 default y
1278 help
1279 Virtualization Host Extensions (VHE) allow the kernel to run
1280 directly at EL2 (instead of EL1) on processors that support
1281 it. This leads to better performance for KVM, as they reduce
1282 the cost of the world switch.
1284 Selecting this option allows the VHE feature to be detected
1285 at runtime, and does not affect processors that do not
1286 implement this feature.
1288 endmenu
1290 menu "ARMv8.2 architectural features"
1292 config ARM64_UAO
1293 bool "Enable support for User Access Override (UAO)"
1294 default y
1295 help
1296 User Access Override (UAO; part of the ARMv8.2 Extensions)
1297 causes the 'unprivileged' variant of the load/store instructions to
1298 be overridden to be privileged.
1300 This option changes get_user() and friends to use the 'unprivileged'
1301 variant of the load/store instructions. This ensures that user-space
1302 really did have access to the supplied memory. When addr_limit is
1303 set to kernel memory the UAO bit will be set, allowing privileged
1304 access to kernel memory.
1306 Choosing this option will cause copy_to_user() et al to use user-space
1307 memory permissions.
1309 The feature is detected at runtime, the kernel will use the
1310 regular load/store instructions if the cpu does not implement the
1311 feature.
1313 config ARM64_PMEM
1314 bool "Enable support for persistent memory"
1315 select ARCH_HAS_PMEM_API
1316 select ARCH_HAS_UACCESS_FLUSHCACHE
1317 help
1318 Say Y to enable support for the persistent memory API based on the
1319 ARMv8.2 DCPoP feature.
1321 The feature is detected at runtime, and the kernel will use DC CVAC
1322 operations if DC CVAP is not supported (following the behaviour of
1323 DC CVAP itself if the system does not define a point of persistence).
1325 config ARM64_RAS_EXTN
1326 bool "Enable support for RAS CPU Extensions"
1327 default y
1328 help
1329 CPUs that support the Reliability, Availability and Serviceability
1330 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1331 errors, classify them and report them to software.
1333 On CPUs with these extensions system software can use additional
1334 barriers to determine if faults are pending and read the
1335 classification from a new set of registers.
1337 Selecting this feature will allow the kernel to use these barriers
1338 and access the new registers if the system supports the extension.
1339 Platform RAS features may additionally depend on firmware support.
1341 config ARM64_CNP
1342 bool "Enable support for Common Not Private (CNP) translations"
1343 default y
1344 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1345 help
1346 Common Not Private (CNP) allows translation table entries to
1347 be shared between different PEs in the same inner shareable
1348 domain, so the hardware can use this fact to optimise the
1349 caching of such entries in the TLB.
1351 Selecting this option allows the CNP feature to be detected
1352 at runtime, and does not affect PEs that do not implement
1353 this feature.
1355 endmenu
1357 menu "ARMv8.3 architectural features"
1359 config ARM64_PTR_AUTH
1360 bool "Enable support for pointer authentication"
1361 default y
1362 depends on !KVM || ARM64_VHE
1363 help
1364 Pointer authentication (part of the ARMv8.3 Extensions) provides
1365 instructions for signing and authenticating pointers against secret
1366 keys, which can be used to mitigate Return Oriented Programming (ROP)
1367 and other attacks.
1369 This option enables these instructions at EL0 (i.e. for userspace).
1371 Choosing this option will cause the kernel to initialise secret keys
1372 for each process at exec() time, with these keys being
1373 context-switched along with the process.
1375 The feature is detected at runtime. If the feature is not present in
1376 hardware it will not be advertised to userspace/KVM guest nor will it
1377 be enabled. However, KVM guest also require VHE mode and hence
1378 CONFIG_ARM64_VHE=y option to use this feature.
1380 endmenu
1382 config ARM64_SVE
1383 bool "ARM Scalable Vector Extension support"
1384 default y
1385 depends on !KVM || ARM64_VHE
1386 help
1387 The Scalable Vector Extension (SVE) is an extension to the AArch64
1388 execution state which complements and extends the SIMD functionality
1389 of the base architecture to support much larger vectors and to enable
1390 additional vectorisation opportunities.
1392 To enable use of this extension on CPUs that implement it, say Y.
1394 On CPUs that support the SVE2 extensions, this option will enable
1395 those too.
1397 Note that for architectural reasons, firmware _must_ implement SVE
1398 support when running on SVE capable hardware. The required support
1399 is present in:
1401 * version 1.5 and later of the ARM Trusted Firmware
1402 * the AArch64 boot wrapper since commit 5e1261e08abf
1403 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1405 For other firmware implementations, consult the firmware documentation
1406 or vendor.
1408 If you need the kernel to boot on SVE-capable hardware with broken
1409 firmware, you may need to say N here until you get your firmware
1410 fixed. Otherwise, you may experience firmware panics or lockups when
1411 booting the kernel. If unsure and you are not observing these
1412 symptoms, you should assume that it is safe to say Y.
1414 CPUs that support SVE are architecturally required to support the
1415 Virtualization Host Extensions (VHE), so the kernel makes no
1416 provision for supporting SVE alongside KVM without VHE enabled.
1417 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1418 KVM in the same kernel image.
1420 config ARM64_MODULE_PLTS
1421 bool
1422 select HAVE_MOD_ARCH_SPECIFIC
1424 config ARM64_PSEUDO_NMI
1425 bool "Support for NMI-like interrupts"
1426 depends on BROKEN # 1556553607-46531-1-git-send-email-julien.thierry@arm.com
1427 select CONFIG_ARM_GIC_V3
1428 help
1429 Adds support for mimicking Non-Maskable Interrupts through the use of
1430 GIC interrupt priority. This support requires version 3 or later of
1431 ARM GIC.
1433 This high priority configuration for interrupts needs to be
1434 explicitly enabled by setting the kernel parameter
1435 "irqchip.gicv3_pseudo_nmi" to 1.
1437 If unsure, say N
1439 config RELOCATABLE
1440 bool
1441 help
1442 This builds the kernel as a Position Independent Executable (PIE),
1443 which retains all relocation metadata required to relocate the
1444 kernel binary at runtime to a different virtual address than the
1445 address it was linked at.
1446 Since AArch64 uses the RELA relocation format, this requires a
1447 relocation pass at runtime even if the kernel is loaded at the
1448 same address it was linked at.
1450 config RANDOMIZE_BASE
1451 bool "Randomize the address of the kernel image"
1452 select ARM64_MODULE_PLTS if MODULES
1453 select RELOCATABLE
1454 help
1455 Randomizes the virtual address at which the kernel image is
1456 loaded, as a security feature that deters exploit attempts
1457 relying on knowledge of the location of kernel internals.
1459 It is the bootloader's job to provide entropy, by passing a
1460 random u64 value in /chosen/kaslr-seed at kernel entry.
1462 When booting via the UEFI stub, it will invoke the firmware's
1463 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1464 to the kernel proper. In addition, it will randomise the physical
1465 location of the kernel Image as well.
1467 If unsure, say N.
1469 config RANDOMIZE_MODULE_REGION_FULL
1470 bool "Randomize the module region over a 4 GB range"
1471 depends on RANDOMIZE_BASE
1472 default y
1473 help
1474 Randomizes the location of the module region inside a 4 GB window
1475 covering the core kernel. This way, it is less likely for modules
1476 to leak information about the location of core kernel data structures
1477 but it does imply that function calls between modules and the core
1478 kernel will need to be resolved via veneers in the module PLT.
1480 When this option is not set, the module region will be randomized over
1481 a limited range that contains the [_stext, _etext] interval of the
1482 core kernel, so branch relocations are always in range.
1484 config CC_HAVE_STACKPROTECTOR_SYSREG
1485 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1487 config STACKPROTECTOR_PER_TASK
1488 def_bool y
1489 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1491 endmenu
1493 menu "Boot options"
1495 config ARM64_ACPI_PARKING_PROTOCOL
1496 bool "Enable support for the ARM64 ACPI parking protocol"
1497 depends on ACPI
1498 help
1499 Enable support for the ARM64 ACPI parking protocol. If disabled
1500 the kernel will not allow booting through the ARM64 ACPI parking
1501 protocol even if the corresponding data is present in the ACPI
1502 MADT table.
1504 config CMDLINE
1505 string "Default kernel command string"
1506 default ""
1507 help
1508 Provide a set of default command-line options at build time by
1509 entering them here. As a minimum, you should specify the the
1510 root device (e.g. root=/dev/nfs).
1512 config CMDLINE_FORCE
1513 bool "Always use the default kernel command string"
1514 help
1515 Always use the default kernel command string, even if the boot
1516 loader passes other arguments to the kernel.
1517 This is useful if you cannot or don't want to change the
1518 command-line options your boot loader passes to the kernel.
1520 config EFI_STUB
1521 bool
1523 config EFI
1524 bool "UEFI runtime support"
1525 depends on OF && !CPU_BIG_ENDIAN
1526 depends on KERNEL_MODE_NEON
1527 select ARCH_SUPPORTS_ACPI
1528 select LIBFDT
1529 select UCS2_STRING
1530 select EFI_PARAMS_FROM_FDT
1531 select EFI_RUNTIME_WRAPPERS
1532 select EFI_STUB
1533 select EFI_ARMSTUB
1534 default y
1535 help
1536 This option provides support for runtime services provided
1537 by UEFI firmware (such as non-volatile variables, realtime
1538 clock, and platform reset). A UEFI stub is also provided to
1539 allow the kernel to be booted as an EFI application. This
1540 is only useful on systems that have UEFI firmware.
1542 config DMI
1543 bool "Enable support for SMBIOS (DMI) tables"
1544 depends on EFI
1545 default y
1546 help
1547 This enables SMBIOS/DMI feature for systems.
1549 This option is only useful on systems that have UEFI firmware.
1550 However, even with this option, the resultant kernel should
1551 continue to boot on existing non-UEFI platforms.
1553 endmenu
1555 config SYSVIPC_COMPAT
1556 def_bool y
1557 depends on COMPAT && SYSVIPC
1559 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1560 def_bool y
1561 depends on HUGETLB_PAGE && MIGRATION
1563 menu "Power management options"
1565 source "kernel/power/Kconfig"
1567 config ARCH_HIBERNATION_POSSIBLE
1568 def_bool y
1569 depends on CPU_PM
1571 config ARCH_HIBERNATION_HEADER
1572 def_bool y
1573 depends on HIBERNATION
1575 config ARCH_SUSPEND_POSSIBLE
1576 def_bool y
1578 endmenu
1580 menu "CPU Power Management"
1582 source "drivers/cpuidle/Kconfig"
1584 source "drivers/cpufreq/Kconfig"
1586 endmenu
1588 source "drivers/firmware/Kconfig"
1590 source "drivers/acpi/Kconfig"
1592 source "arch/arm64/kvm/Kconfig"
1594 if CRYPTO
1595 source "arch/arm64/crypto/Kconfig"
1596 endif